Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T7,T10
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T13,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T13,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T13,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T7,T10
1	0	Covered	T7,T10,T11
1	1	Covered	T13,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T7,T10
0	1	Covered	T13,T42,T69
1	0	Covered	T69,T78,T112

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T11
1	-	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T7,T10
DetectSt	168	Covered	T13,T7,T10
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T7,T10
DebounceSt->IdleSt	163	Covered	T201,T74,T229
DetectSt->IdleSt	186	Covered	T13,T42,T69
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T13,T7,T10
StableSt->IdleSt	206	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T7,T10
0	1	Covered	T13,T7,T10
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T7,T10
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T13,T7,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T201,T74,T229
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T13,T42,T69
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T13,T7,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	2881	0	0
CntIncr_A	8272513	98064	0	0
CntNoWrap_A	8272513	7600273	0	0
DetectStDropOut_A	8272513	449	0	0
DetectedOut_A	8272513	69395	0	0
DetectedPulseOut_A	8272513	789	0	0
DisabledIdleSt_A	8272513	7150610	0	0
DisabledNoDetection_A	8272513	7152715	0	0
EnterDebounceSt_A	8272513	1459	0	0
EnterDetectSt_A	8272513	1424	0	0
EnterStableSt_A	8272513	789	0	0
PulseIsPulse_A	8272513	789	0	0
StayInStableSt	8272513	68508	0	0
gen_high_event_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	689	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	2881	0	0
T4	930	0	0	0
T7	16409	18	0	0
T10	0	32	0	0
T11	0	36	0	0
T13	4971	22	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	14	0	0
T41	0	44	0	0
T42	0	42	0	0
T69	0	38	0	0
T70	0	50	0	0
T71	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	98064	0	0
T4	930	0	0	0
T7	16409	657	0	0
T10	0	832	0	0
T11	0	1134	0	0
T13	4971	512	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	532	0	0
T41	0	1980	0	0
T42	0	1306	0	0
T69	0	1012	0	0
T70	0	1326	0	0
T71	0	1380	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7600273	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	15982	0	0
T13	4971	4548	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	449	0	0
T4	930	0	0	0
T7	16409	0	0	0
T13	4971	11	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T42	0	21	0	0
T69	0	12	0	0
T70	0	25	0	0
T71	0	27	0	0
T74	0	1	0	0
T78	0	1	0	0
T89	0	24	0	0
T90	0	29	0	0
T112	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	69395	0	0
T4	930	0	0	0
T7	16409	468	0	0
T10	0	866	0	0
T11	0	493	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	190	0	0
T41	0	2307	0	0
T47	403	0	0	0
T69	0	2	0	0
T113	0	1127	0	0
T201	0	205	0	0
T204	0	2568	0	0
T208	0	2738	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	789	0	0
T4	930	0	0	0
T7	16409	9	0	0
T10	0	16	0	0
T11	0	18	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	7	0	0
T41	0	22	0	0
T47	403	0	0	0
T69	0	2	0	0
T113	0	11	0	0
T201	0	9	0	0
T204	0	25	0	0
T208	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7150610	0	0
T1	1033	632	0	0
T2	14513	14104	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	11627	0	0
T13	4971	2014	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7152715	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	11629	0	0
T13	4971	2014	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1459	0	0
T4	930	0	0	0
T7	16409	9	0	0
T10	0	16	0	0
T11	0	18	0	0
T13	4971	11	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	7	0	0
T41	0	22	0	0
T42	0	21	0	0
T69	0	19	0	0
T70	0	25	0	0
T71	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	1424	0	0
T4	930	0	0	0
T7	16409	9	0	0
T10	0	16	0	0
T11	0	18	0	0
T13	4971	11	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	7	0	0
T41	0	22	0	0
T42	0	21	0	0
T69	0	19	0	0
T70	0	25	0	0
T71	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	789	0	0
T4	930	0	0	0
T7	16409	9	0	0
T10	0	16	0	0
T11	0	18	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	7	0	0
T41	0	22	0	0
T47	403	0	0	0
T69	0	2	0	0
T113	0	11	0	0
T201	0	9	0	0
T204	0	25	0	0
T208	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	789	0	0
T4	930	0	0	0
T7	16409	9	0	0
T10	0	16	0	0
T11	0	18	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	7	0	0
T41	0	22	0	0
T47	403	0	0	0
T69	0	2	0	0
T113	0	11	0	0
T201	0	9	0	0
T204	0	25	0	0
T208	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	68508	0	0
T4	930	0	0	0
T7	16409	456	0	0
T10	0	849	0	0
T11	0	475	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	183	0	0
T41	0	2281	0	0
T47	403	0	0	0
T94	0	1902	0	0
T113	0	1115	0	0
T201	0	196	0	0
T204	0	2535	0	0
T208	0	2713	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	689	0	0
T4	930	0	0	0
T7	16409	6	0	0
T10	0	15	0	0
T11	0	18	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T23	1385	0	0	0
T24	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T31	0	7	0	0
T41	0	18	0	0
T47	403	0	0	0
T94	0	13	0	0
T113	0	10	0	0
T201	0	9	0	0
T204	0	17	0	0
T208	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T7
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T7
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T2,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T13,T7
1	1	Covered	T2,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T9,T21,T91
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T10
0	1	Covered	T2,T7,T10
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T10
1	-	Covered	T2,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T9
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T2,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T2,T10,T38
DetectSt->IdleSt	186	Covered	T9,T21,T91
DetectSt->StableSt	191	Covered	T2,T7,T10
IdleSt->DebounceSt	148	Covered	T2,T7,T9
StableSt->IdleSt	206	Covered	T2,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T10,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T21,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8272513	800	0	0
CntIncr_A	8272513	40404	0	0
CntNoWrap_A	8272513	7602354	0	0
DetectStDropOut_A	8272513	40	0	0
DetectedOut_A	8272513	14013	0	0
DetectedPulseOut_A	8272513	330	0	0
DisabledIdleSt_A	8272513	7266944	0	0
DisabledNoDetection_A	8272513	7268622	0	0
EnterDebounceSt_A	8272513	426	0	0
EnterDetectSt_A	8272513	375	0	0
EnterStableSt_A	8272513	330	0	0
PulseIsPulse_A	8272513	330	0	0
StayInStableSt	8272513	13650	0	0
gen_high_level_sva.HighLevelEvent_A	8272513	7605449	0	0
gen_not_sticky_sva.StableStDropOut_A	8272513	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	800	0	0
T2	14513	9	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	2	0	0
T9	0	4	0	0
T10	0	3	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	2	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	4	0	0
T38	0	7	0	0
T41	0	6	0	0
T44	0	2	0	0
T114	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	40404	0	0
T2	14513	567	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	84	0	0
T9	0	288	0	0
T10	0	99	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	133	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	278	0	0
T38	0	421	0	0
T41	0	234	0	0
T44	0	171	0	0
T114	0	345	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7602354	0	0
T1	1033	632	0	0
T2	14513	14095	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	15998	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	40	0	0
T9	18685	2	0	0
T10	25660	0	0	0
T11	15105	0	0	0
T12	682	0	0	0
T21	0	1	0	0
T25	522	0	0	0
T27	61982	0	0	0
T28	21366	0	0	0
T49	422	0	0	0
T50	493	0	0	0
T91	0	5	0	0
T230	0	6	0	0
T231	0	1	0	0
T232	0	4	0	0
T233	0	3	0	0
T234	0	1	0	0
T235	0	3	0	0
T236	0	4	0	0
T237	467	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	14013	0	0
T2	14513	18	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	52	0	0
T10	0	76	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	102	0	0
T38	0	130	0	0
T41	0	101	0	0
T44	0	46	0	0
T114	0	166	0	0
T188	0	122	0	0
T238	0	262	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	330	0	0
T2	14513	4	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	1	0	0
T10	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	2	0	0
T38	0	3	0	0
T41	0	3	0	0
T44	0	1	0	0
T114	0	3	0	0
T188	0	6	0	0
T238	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7266944	0	0
T1	1033	632	0	0
T2	14513	10073	0	0
T3	958	557	0	0
T4	930	529	0	0
T5	735	334	0	0
T6	523	122	0	0
T7	16409	15535	0	0
T13	4971	4570	0	0
T14	507	106	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7268622	0	0
T1	1033	633	0	0
T2	14513	10073	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	15537	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	426	0	0
T2	14513	5	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	2	0	0
T38	0	4	0	0
T41	0	3	0	0
T44	0	1	0	0
T114	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	375	0	0
T2	14513	4	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T21	0	1	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	2	0	0
T38	0	3	0	0
T41	0	3	0	0
T44	0	1	0	0
T114	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	330	0	0
T2	14513	4	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	1	0	0
T10	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	2	0	0
T38	0	3	0	0
T41	0	3	0	0
T44	0	1	0	0
T114	0	3	0	0
T188	0	6	0	0
T238	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	330	0	0
T2	14513	4	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	1	0	0
T10	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	2	0	0
T38	0	3	0	0
T41	0	3	0	0
T44	0	1	0	0
T114	0	3	0	0
T188	0	6	0	0
T238	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	13650	0	0
T2	14513	14	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	51	0	0
T10	0	75	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	100	0	0
T38	0	127	0	0
T41	0	98	0	0
T44	0	45	0	0
T114	0	163	0	0
T188	0	116	0	0
T238	0	253	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	7605449	0	0
T1	1033	633	0	0
T2	14513	14109	0	0
T3	958	558	0	0
T4	930	530	0	0
T5	735	335	0	0
T6	523	123	0	0
T7	16409	16005	0	0
T13	4971	4571	0	0
T14	507	107	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8272513	292	0	0
T2	14513	4	0	0
T3	958	0	0	0
T4	930	0	0	0
T7	16409	1	0	0
T10	0	1	0	0
T13	4971	0	0	0
T14	507	0	0	0
T15	408	0	0	0
T22	496	0	0	0
T26	696	0	0	0
T29	469	0	0	0
T32	0	2	0	0
T38	0	3	0	0
T41	0	3	0	0
T44	0	1	0	0
T114	0	3	0	0
T188	0	6	0	0
T238	0	8	0	0