Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1292524677	10176	0	0
auto_block_debounce_ctl_rd_A	1292524677	1497	0	0
auto_block_out_ctl_rd_A	1292524677	2348	0	0
com_det_ctl_0_rd_A	1292524677	3498	0	0
com_det_ctl_1_rd_A	1292524677	3923	0	0
com_det_ctl_2_rd_A	1292524677	3705	0	0
com_det_ctl_3_rd_A	1292524677	3605	0	0
com_out_ctl_0_rd_A	1292524677	4233	0	0
com_out_ctl_1_rd_A	1292524677	4163	0	0
com_out_ctl_2_rd_A	1292524677	4157	0	0
com_out_ctl_3_rd_A	1292524677	4048	0	0
com_pre_det_ctl_0_rd_A	1292524677	1176	0	0
com_pre_det_ctl_1_rd_A	1292524677	1167	0	0
com_pre_det_ctl_2_rd_A	1292524677	1242	0	0
com_pre_det_ctl_3_rd_A	1292524677	1093	0	0
com_pre_sel_ctl_0_rd_A	1292524677	4062	0	0
com_pre_sel_ctl_1_rd_A	1292524677	4255	0	0
com_pre_sel_ctl_2_rd_A	1292524677	4288	0	0
com_pre_sel_ctl_3_rd_A	1292524677	4351	0	0
com_sel_ctl_0_rd_A	1292524677	3985	0	0
com_sel_ctl_1_rd_A	1292524677	4107	0	0
com_sel_ctl_2_rd_A	1292524677	4251	0	0
com_sel_ctl_3_rd_A	1292524677	4241	0	0
ec_rst_ctl_rd_A	1292524677	2153	0	0
intr_enable_rd_A	1292524677	1773	0	0
key_intr_ctl_rd_A	1292524677	3016	0	0
key_intr_debounce_ctl_rd_A	1292524677	1062	0	0
key_invert_ctl_rd_A	1292524677	4768	0	0
pin_allowed_ctl_rd_A	1292524677	4818	0	0
pin_out_ctl_rd_A	1292524677	3411	0	0
pin_out_value_rd_A	1292524677	3408	0	0
regwen_rd_A	1292524677	1357	0	0
ulp_ac_debounce_ctl_rd_A	1292524677	1232	0	0
ulp_ctl_rd_A	1292524677	1230	0	0
ulp_lid_debounce_ctl_rd_A	1292524677	1199	0	0
ulp_pwrb_debounce_ctl_rd_A	1292524677	1259	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	10176	0	0
T20	215542	0	0	0
T21	0	13	0	0
T37	0	15	0	0
T38	154260	2	0	0
T39	139921	0	0	0
T44	139898	9	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T83	0	1	0	0
T111	0	21	0	0
T123	0	4	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	8	0	0
T267	0	8	0	0
T268	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1497	0	0
T19	66977	0	0	0
T28	117517	15	0	0
T31	545811	0	0	0
T32	686341	0	0	0
T33	0	8	0	0
T40	123509	0	0	0
T43	0	10	0	0
T44	0	10	0	0
T45	0	11	0	0
T58	46780	0	0	0
T59	18132	0	0	0
T60	65754	0	0	0
T61	204315	0	0	0
T62	105807	0	0	0
T122	0	7	0	0
T267	0	38	0	0
T269	0	3	0	0
T270	0	9	0	0
T271	0	17	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	2348	0	0
T19	66977	0	0	0
T28	117517	4	0	0
T31	545811	0	0	0
T32	686341	0	0	0
T33	0	14	0	0
T40	123509	0	0	0
T43	0	5	0	0
T44	0	23	0	0
T45	0	12	0	0
T58	46780	0	0	0
T59	18132	0	0	0
T60	65754	0	0	0
T61	204315	0	0	0
T62	105807	0	0	0
T122	0	19	0	0
T267	0	53	0	0
T269	0	1	0	0
T270	0	6	0	0
T271	0	6	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3498	0	0
T2	703921	73	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	32	0	0
T10	0	46	0	0
T11	0	18	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	43	0	0
T44	0	13	0	0
T112	0	29	0	0
T114	0	53	0	0
T188	0	68	0	0
T238	0	37	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3923	0	0
T2	703921	70	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	56	0	0
T10	0	82	0	0
T11	0	26	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	33	0	0
T44	0	20	0	0
T112	0	35	0	0
T114	0	50	0	0
T188	0	66	0	0
T238	0	51	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3705	0	0
T2	703921	75	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	49	0	0
T10	0	79	0	0
T11	0	41	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	35	0	0
T44	0	13	0	0
T112	0	45	0	0
T114	0	36	0	0
T188	0	69	0	0
T238	0	47	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3605	0	0
T2	703921	60	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	54	0	0
T10	0	63	0	0
T11	0	22	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	30	0	0
T44	0	12	0	0
T112	0	45	0	0
T114	0	46	0	0
T188	0	59	0	0
T238	0	29	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4233	0	0
T2	703921	73	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	48	0	0
T10	0	79	0	0
T11	0	34	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	40	0	0
T112	0	30	0	0
T114	0	35	0	0
T188	0	70	0	0
T211	0	51	0	0
T238	0	55	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4163	0	0
T2	703921	81	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	39	0	0
T10	0	64	0	0
T11	0	15	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	19	0	0
T44	0	8	0	0
T112	0	24	0	0
T114	0	31	0	0
T188	0	63	0	0
T238	0	53	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4157	0	0
T2	703921	73	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	45	0	0
T10	0	69	0	0
T11	0	10	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	31	0	0
T44	0	8	0	0
T112	0	26	0	0
T114	0	39	0	0
T188	0	65	0	0
T238	0	42	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4048	0	0
T2	703921	38	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	29	0	0
T10	0	55	0	0
T11	0	42	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	38	0	0
T44	0	15	0	0
T112	0	34	0	0
T114	0	40	0	0
T188	0	76	0	0
T238	0	31	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1176	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	17	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	11	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T141	0	33	0	0
T162	0	1	0	0
T179	0	12	0	0
T267	0	36	0	0
T268	0	28	0	0
T272	0	5	0	0
T273	0	9	0	0
T274	0	28	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1167	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	8	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	6	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T141	0	24	0	0
T162	0	7	0	0
T179	0	16	0	0
T267	0	25	0	0
T268	0	17	0	0
T272	0	3	0	0
T273	0	2	0	0
T274	0	24	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1242	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	13	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	11	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T141	0	43	0	0
T179	0	10	0	0
T267	0	33	0	0
T268	0	14	0	0
T272	0	6	0	0
T273	0	4	0	0
T274	0	23	0	0
T275	0	26	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1093	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	3	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	2	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T141	0	5	0	0
T162	0	2	0	0
T179	0	17	0	0
T267	0	35	0	0
T268	0	27	0	0
T272	0	3	0	0
T273	0	7	0	0
T274	0	13	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4062	0	0
T2	703921	65	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	43	0	0
T10	0	56	0	0
T11	0	24	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	33	0	0
T44	0	18	0	0
T112	0	44	0	0
T114	0	55	0	0
T188	0	84	0	0
T238	0	29	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4255	0	0
T2	703921	69	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	40	0	0
T10	0	80	0	0
T11	0	18	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	33	0	0
T44	0	9	0	0
T112	0	29	0	0
T114	0	48	0	0
T188	0	64	0	0
T238	0	50	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4288	0	0
T2	703921	66	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	40	0	0
T10	0	73	0	0
T11	0	58	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	18	0	0
T44	0	14	0	0
T112	0	24	0	0
T114	0	50	0	0
T188	0	73	0	0
T238	0	35	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4351	0	0
T2	703921	68	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	38	0	0
T10	0	71	0	0
T11	0	38	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	48	0	0
T44	0	6	0	0
T112	0	39	0	0
T114	0	60	0	0
T188	0	107	0	0
T238	0	48	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3985	0	0
T2	703921	97	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	18	0	0
T10	0	65	0	0
T11	0	29	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	37	0	0
T44	0	13	0	0
T112	0	34	0	0
T114	0	29	0	0
T188	0	81	0	0
T238	0	36	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4107	0	0
T2	703921	76	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	47	0	0
T10	0	67	0	0
T11	0	46	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	9	0	0
T44	0	10	0	0
T112	0	28	0	0
T114	0	33	0	0
T188	0	60	0	0
T238	0	8	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4251	0	0
T2	703921	67	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	49	0	0
T10	0	61	0	0
T11	0	32	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	36	0	0
T44	0	15	0	0
T112	0	35	0	0
T114	0	32	0	0
T188	0	71	0	0
T238	0	59	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4241	0	0
T2	703921	69	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	30	0	0
T10	0	77	0	0
T11	0	38	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	23	0	0
T44	0	12	0	0
T112	0	17	0	0
T114	0	32	0	0
T188	0	87	0	0
T238	0	37	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	2153	0	0
T2	703921	19	0	0
T3	324674	0	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T9	0	9	0	0
T10	0	32	0	0
T11	0	5	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T31	0	9	0	0
T44	0	28	0	0
T112	0	3	0	0
T114	0	11	0	0
T188	0	16	0	0
T238	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1773	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	14	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	8	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T162	0	24	0	0
T172	0	2	0	0
T222	0	18	0	0
T232	0	18	0	0
T267	0	78	0	0
T268	0	39	0	0
T272	0	8	0	0
T273	0	5	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3016	0	0
T3	324674	4	0	0
T4	175226	0	0	0
T7	763058	0	0	0
T13	546860	0	0	0
T14	58412	0	0	0
T15	44838	0	0	0
T22	61947	0	0	0
T23	332675	0	0	0
T26	132249	0	0	0
T29	56288	0	0	0
T33	0	1	0	0
T44	0	8	0	0
T165	0	4	0	0
T166	0	1	0	0
T168	0	3	0	0
T172	0	2	0	0
T180	0	1	0	0
T267	0	22	0	0
T268	0	12	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1062	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	9	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	2	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T141	0	29	0	0
T162	0	5	0	0
T179	0	14	0	0
T267	0	37	0	0
T268	0	15	0	0
T272	0	1	0	0
T274	0	12	0	0
T275	0	18	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4768	0	0
T8	215910	0	0	0
T9	934258	0	0	0
T10	641521	0	0	0
T11	717523	0	0	0
T23	332675	87	0	0
T24	62063	0	0	0
T44	0	43	0	0
T47	185527	0	0	0
T48	209521	0	0	0
T49	202521	0	0	0
T50	234106	0	0	0
T224	0	40	0	0
T267	0	256	0	0
T268	0	24	0	0
T276	0	78	0	0
T277	0	21	0	0
T278	0	54	0	0
T279	0	52	0	0
T280	0	83	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	4818	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	16	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	4	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T143	0	63	0	0
T265	0	26	0	0
T267	0	31	0	0
T268	0	6	0	0
T272	0	101	0	0
T281	0	80	0	0
T282	0	69	0	0
T283	0	47	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3411	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	4	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	8	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T143	0	58	0	0
T265	0	37	0	0
T267	0	38	0	0
T268	0	16	0	0
T272	0	95	0	0
T281	0	54	0	0
T282	0	60	0	0
T283	0	46	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	3408	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	5	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	6	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T143	0	68	0	0
T265	0	53	0	0
T267	0	25	0	0
T268	0	18	0	0
T272	0	76	0	0
T281	0	77	0	0
T282	0	66	0	0
T283	0	76	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1357	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	24	0	0
T45	22539	0	0	0
T68	261198	0	0	0
T125	0	10	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T141	0	33	0	0
T162	0	2	0	0
T179	0	10	0	0
T267	0	38	0	0
T268	0	15	0	0
T272	0	5	0	0
T273	0	6	0	0
T274	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1232	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	8	0	0
T45	22539	0	0	0
T55	0	13	0	0
T68	261198	0	0	0
T72	0	17	0	0
T73	0	12	0	0
T85	0	7	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T267	0	26	0	0
T268	0	22	0	0
T272	0	3	0	0
T284	0	6	0	0
T285	0	15	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1230	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	11	0	0
T45	22539	0	0	0
T52	0	2	0	0
T55	0	3	0	0
T68	261198	0	0	0
T72	0	11	0	0
T73	0	10	0	0
T85	0	4	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T267	0	38	0	0
T268	0	21	0	0
T272	0	6	0	0
T285	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1199	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	9	0	0
T45	22539	0	0	0
T52	0	2	0	0
T68	261198	0	0	0
T72	0	1	0	0
T73	0	9	0	0
T85	0	1	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T267	0	28	0	0
T268	0	33	0	0
T272	0	2	0	0
T284	0	3	0	0
T285	0	8	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1292524677	1259	0	0
T20	215542	0	0	0
T38	154260	0	0	0
T39	139921	0	0	0
T44	139898	6	0	0
T45	22539	0	0	0
T52	0	1	0	0
T55	0	5	0	0
T68	261198	0	0	0
T72	0	5	0	0
T73	0	13	0	0
T85	0	4	0	0
T130	133410	0	0	0
T131	60695	0	0	0
T132	44948	0	0	0
T133	144092	0	0	0
T267	0	23	0	0
T268	0	24	0	0
T272	0	5	0	0
T284	0	1	0	0