Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T19,T20,T51

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T2,T13
1	0	Covered	T19,T20,T51
1	1	Covered	T5,T2,T13

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	226571	0	0
SrcPulseCheck_M	2147483647	229174	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	226571
T2	9325129	15
T3	4232258	0
T4	3698346	0
T5	176717	0
T6	125560	0
T7	16352398	15
T8	432804	0
T9	1905886	21
T10	1334362	27
T11	0	12
T13	11583480	3
T14	1236792	0
T15	949758	0
T21	0	38
T22	1310807	0
T23	3340600	0
T24	625590	0
T26	2924790	12
T27	0	16
T28	0	16
T29	1135140	2
T31	0	6
T32	0	33
T33	0	18
T40	0	16
T41	0	8
T42	0	1
T43	0	16
T44	0	36
T45	0	14
T46	0	14
T47	371860	0
T48	419880	0
T49	405886	0
T50	469198	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	229174
T2	8635721	15
T3	3908542	0
T4	3524050	0
T5	735	0
T6	523	0
T7	15605749	15
T8	432804	0
T9	1905886	21
T10	1334362	27
T11	0	12
T13	11041591	3
T14	1178887	0
T15	905328	0
T21	0	38
T22	1249356	0
T23	3340600	0
T24	625590	0
T26	2924790	12
T27	0	16
T28	0	16
T29	1135140	2
T31	0	6
T32	0	33
T33	0	18
T40	0	16
T41	0	8
T42	0	1
T43	0	16
T44	0	36
T45	0	14
T46	0	14
T47	371860	0
T48	419880	0
T49	405886	0
T50	469198	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T16,T17,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T2,T13
1	0	Covered	T16,T17,T18
1	1	Covered	T5,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1872	0	0
SrcPulseCheck_M	1292524677	1947	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1872
T2	14513	5
T3	958	0
T4	930	0
T5	735	1
T6	523	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T29	0	1
T31	0	2
T32	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1947
T2	703921	5
T3	324674	0
T4	175226	0
T5	176717	1
T6	125560	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T29	0	1
T31	0	2
T32	0	11

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T16,T17,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T2,T13
1	0	Covered	T16,T17,T18
1	1	Covered	T5,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1938	0	0
SrcPulseCheck_M	8529885	1938	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1938
T2	703921	5
T3	324674	0
T4	175226	0
T5	176717	1
T6	125560	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T29	0	1
T31	0	2
T32	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1938
T2	14513	5
T3	958	0
T4	930	0
T5	735	1
T6	523	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T29	0	1
T31	0	2
T32	0	11

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T51,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T51,T53
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	993	0	0
SrcPulseCheck_M	1292524677	1067	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	993
T19	813634	3
T20	0	1
T21	0	2
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1067
T19	66977	3
T20	0	1
T21	0	2
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T51,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T51,T53
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1058	0	0
SrcPulseCheck_M	8529885	1058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1058
T19	66977	3
T20	0	1
T21	0	2
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1058
T19	813634	3
T20	0	1
T21	0	2
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T51,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T51,T53
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	992	0	0
SrcPulseCheck_M	1292524677	1067	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	992
T19	813634	3
T20	0	1
T21	0	2
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1067
T19	66977	3
T20	0	1
T21	0	2
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T51,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T51,T53
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1058	0	0
SrcPulseCheck_M	8529885	1058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1058
T19	66977	3
T20	0	1
T21	0	2
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1058
T19	813634	3
T20	0	1
T21	0	2
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T51,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T51,T53
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	998	0	0
SrcPulseCheck_M	1292524677	1075	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	998
T19	813634	3
T20	0	1
T21	0	2
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1075
T19	66977	3
T20	0	1
T21	0	2
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T51,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T51,T53
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1061	0	0
SrcPulseCheck_M	8529885	1061	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1061
T19	66977	3
T20	0	1
T21	0	2
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1061
T19	813634	3
T20	0	1
T21	0	2
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	3
T52	0	1
T53	0	3
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	995	0	0
SrcPulseCheck_M	1292524677	1069	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	995
T19	813634	6
T20	0	2
T21	0	4
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	2
T54	0	4
T55	0	1
T56	0	6
T57	0	2
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0
T72	0	2
T73	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1069
T19	66977	6
T20	0	2
T21	0	4
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	2
T54	0	4
T55	0	1
T56	0	6
T57	0	2
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0
T72	0	2
T73	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1061	0	0
SrcPulseCheck_M	8529885	1061	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1061
T19	66977	6
T20	0	2
T21	0	4
T31	545811	0
T32	686341	0
T40	123509	0
T51	0	2
T54	0	4
T55	0	1
T56	0	6
T57	0	2
T58	46780	0
T59	18132	0
T60	65754	0
T61	204315	0
T62	105807	0
T63	199235	0
T72	0	2
T73	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1061
T19	813634	6
T20	0	2
T21	0	4
T31	11371	0
T32	28014	0
T40	2520	0
T51	0	2
T54	0	4
T55	0	1
T56	0	6
T57	0	2
T58	425	0
T59	518	0
T60	526	0
T61	426	0
T62	423	0
T63	402	0
T72	0	2
T73	0	4

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9
1	1	Covered	T19,T38,T54

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T7,T9
1	0	Covered	T19,T38,T54
1	1	Covered	T2,T7,T9

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1009	0	0
SrcPulseCheck_M	1292524677	1078	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1009
T2	14513	4
T3	958	0
T4	930	0
T7	16409	4
T9	0	5
T10	0	4
T11	0	3
T13	4971	0
T14	507	0
T15	408	0
T19	0	3
T20	0	1
T22	496	0
T26	696	0
T29	469	0
T31	0	1
T32	0	7
T41	0	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1078
T2	703921	4
T3	324674	0
T4	175226	0
T7	763058	4
T9	0	5
T10	0	4
T11	0	3
T13	546860	0
T14	58412	0
T15	44838	0
T19	0	3
T20	0	1
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	1
T32	0	7
T41	0	7

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	3027	0	0
SrcPulseCheck_M	1292524677	3100	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	3027
T8	492	0
T9	18685	0
T10	25660	0
T21	0	20
T22	496	20
T23	1385	40
T24	496	20
T26	696	0
T29	469	0
T34	0	20
T40	0	20
T44	0	20
T47	403	0
T48	419	0
T50	0	20
T64	0	20
T65	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	3100
T8	215910	0
T9	934258	0
T10	641521	0
T21	0	20
T22	61947	20
T23	332675	40
T24	62063	20
T26	132249	0
T29	56288	0
T34	0	20
T40	0	20
T44	0	20
T47	185527	0
T48	209521	0
T50	0	20
T64	0	20
T65	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	3094	0	0
SrcPulseCheck_M	8529885	3094	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	3094
T8	215910	0
T9	934258	0
T10	641521	0
T21	0	20
T22	61947	20
T23	332675	40
T24	62063	20
T26	132249	0
T29	56288	0
T34	0	20
T40	0	20
T44	0	20
T47	185527	0
T48	209521	0
T50	0	20
T64	0	20
T65	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	3094
T8	492	0
T9	18685	0
T10	25660	0
T21	0	20
T22	496	20
T23	1385	40
T24	496	20
T26	696	0
T29	469	0
T34	0	20
T40	0	20
T44	0	20
T47	403	0
T48	419	0
T50	0	20
T64	0	20
T65	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T22
1	0	Covered	T6,T14,T22
1	1	Covered	T6,T14,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T22
1	0	Covered	T6,T14,T25
1	1	Covered	T6,T14,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	6615	0	0
SrcPulseCheck_M	1292524677	6700	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	6615
T2	14513	0
T3	958	0
T4	930	0
T6	523	20
T7	16409	0
T13	4971	0
T14	507	20
T15	408	0
T22	496	1
T23	0	2
T24	0	1
T25	0	20
T29	469	0
T40	0	21
T50	0	1
T59	0	20
T60	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	6700
T2	703921	0
T3	324674	0
T4	175226	0
T6	125560	20
T7	763058	0
T13	546860	0
T14	58412	20
T15	44838	0
T22	61947	1
T23	0	2
T24	0	1
T25	0	20
T29	56288	0
T40	0	21
T50	0	1
T59	0	20
T60	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T22
1	0	Covered	T6,T14,T22
1	1	Covered	T6,T14,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T22
1	0	Covered	T6,T14,T25
1	1	Covered	T6,T14,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	6688	0	0
SrcPulseCheck_M	8529885	6688	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	6688
T2	703921	0
T3	324674	0
T4	175226	0
T6	125560	20
T7	763058	0
T13	546860	0
T14	58412	20
T15	44838	0
T22	61947	1
T23	0	2
T24	0	1
T25	0	20
T29	56288	0
T40	0	21
T50	0	1
T59	0	20
T60	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	6688
T2	14513	0
T3	958	0
T4	930	0
T6	523	20
T7	16409	0
T13	4971	0
T14	507	20
T15	408	0
T22	496	1
T23	0	2
T24	0	1
T25	0	20
T29	469	0
T40	0	21
T50	0	1
T59	0	20
T60	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T2
1	1	Covered	T6,T14,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T6,T2
1	0	Covered	T6,T14,T25
1	1	Covered	T5,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7689	0	0
SrcPulseCheck_M	1292524677	7772	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7689
T2	14513	5
T3	958	0
T4	930	0
T5	735	1
T6	523	20
T7	16409	5
T13	4971	1
T14	507	20
T15	408	0
T22	496	1
T23	0	2
T24	0	1
T29	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7772
T2	703921	5
T3	324674	0
T4	175226	0
T5	176717	1
T6	125560	20
T7	763058	5
T13	546860	1
T14	58412	20
T15	44838	0
T22	61947	1
T23	0	2
T24	0	1
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T6,T2
1	0	Covered	T5,T6,T2
1	1	Covered	T6,T14,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T5,T6,T2
1	0	Covered	T6,T14,T25
1	1	Covered	T5,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7757	0	0
SrcPulseCheck_M	8529885	7757	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7757
T2	703921	5
T3	324674	0
T4	175226	0
T5	176717	1
T6	125560	20
T7	763058	5
T13	546860	1
T14	58412	20
T15	44838	0
T22	61947	1
T23	0	2
T24	0	1
T29	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7757
T2	14513	5
T3	958	0
T4	930	0
T5	735	1
T6	523	20
T7	16409	5
T13	4971	1
T14	507	20
T15	408	0
T22	496	1
T23	0	2
T24	0	1
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T25
1	0	Covered	T6,T14,T25
1	1	Covered	T6,T14,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T25
1	0	Covered	T6,T14,T25
1	1	Covered	T6,T14,T25

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	6511	0	0
SrcPulseCheck_M	1292524677	6593	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	6511
T2	14513	0
T3	958	0
T4	930	0
T6	523	20
T7	16409	0
T13	4971	0
T14	507	20
T15	408	0
T22	496	0
T25	0	20
T29	469	0
T40	0	20
T44	0	20
T59	0	20
T60	0	20
T66	0	20
T67	0	20
T68	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	6593
T2	703921	0
T3	324674	0
T4	175226	0
T6	125560	20
T7	763058	0
T13	546860	0
T14	58412	20
T15	44838	0
T22	61947	0
T25	0	20
T29	56288	0
T40	0	20
T44	0	20
T59	0	20
T60	0	20
T66	0	20
T67	0	20
T68	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T25
1	0	Covered	T6,T14,T25
1	1	Covered	T6,T14,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T6,T14,T25
1	0	Covered	T6,T14,T25
1	1	Covered	T6,T14,T25

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	6580	0	0
SrcPulseCheck_M	8529885	6580	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	6580
T2	703921	0
T3	324674	0
T4	175226	0
T6	125560	20
T7	763058	0
T13	546860	0
T14	58412	20
T15	44838	0
T22	61947	0
T25	0	20
T29	56288	0
T40	0	20
T44	0	20
T59	0	20
T60	0	20
T66	0	20
T67	0	20
T68	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	6580
T2	14513	0
T3	958	0
T4	930	0
T6	523	20
T7	16409	0
T13	4971	0
T14	507	20
T15	408	0
T22	496	0
T25	0	20
T29	469	0
T40	0	20
T44	0	20
T59	0	20
T60	0	20
T66	0	20
T67	0	20
T68	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T3,T4
1	0	Covered	T74,T75,T16
1	1	Covered	T1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	970	0	0
SrcPulseCheck_M	1292524677	1046	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	970
T1	1033	1
T2	14513	0
T3	958	1
T4	930	1
T5	735	0
T6	523	0
T7	16409	0
T8	0	1
T12	0	1
T13	4971	0
T14	507	0
T15	408	0
T33	0	3
T34	0	1
T38	0	1
T39	0	1
T44	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1046
T1	67271	1
T2	703921	0
T3	324674	1
T4	175226	1
T5	176717	0
T6	125560	0
T7	763058	0
T8	0	1
T12	0	1
T13	546860	0
T14	58412	0
T15	44838	0
T33	0	3
T34	0	1
T38	0	1
T39	0	1
T44	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T3,T4
1	0	Covered	T74,T75,T16
1	1	Covered	T1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1037	0	0
SrcPulseCheck_M	8529885	1037	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1037
T1	67271	1
T2	703921	0
T3	324674	1
T4	175226	1
T5	176717	0
T6	125560	0
T7	763058	0
T8	0	1
T12	0	1
T13	546860	0
T14	58412	0
T15	44838	0
T33	0	3
T34	0	1
T38	0	1
T39	0	1
T44	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1037
T1	1033	1
T2	14513	0
T3	958	1
T4	930	1
T5	735	0
T6	523	0
T7	16409	0
T8	0	1
T12	0	1
T13	4971	0
T14	507	0
T15	408	0
T33	0	3
T34	0	1
T38	0	1
T39	0	1
T44	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T75,T16
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1876	0	0
SrcPulseCheck_M	1292524677	1952	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1876
T1	1033	1
T2	14513	5
T3	958	1
T4	930	1
T5	735	0
T6	523	0
T7	16409	5
T8	0	1
T9	0	7
T10	0	9
T13	4971	1
T14	507	0
T15	408	0
T29	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1952
T1	67271	1
T2	703921	5
T3	324674	1
T4	175226	1
T5	176717	0
T6	125560	0
T7	763058	5
T8	0	1
T9	0	7
T10	0	9
T13	546860	1
T14	58412	0
T15	44838	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T75,T16
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1943	0	0
SrcPulseCheck_M	8529885	1943	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1943
T1	67271	1
T2	703921	5
T3	324674	1
T4	175226	1
T5	176717	0
T6	125560	0
T7	763058	5
T8	0	1
T9	0	7
T10	0	9
T13	546860	1
T14	58412	0
T15	44838	0
T29	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1943
T1	1033	1
T2	14513	5
T3	958	1
T4	930	1
T5	735	0
T6	523	0
T7	16409	5
T8	0	1
T9	0	7
T10	0	9
T13	4971	1
T14	507	0
T15	408	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1338	0	0
SrcPulseCheck_M	1292524677	1417	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1338
T8	492	0
T9	18685	0
T10	25660	0
T21	0	11
T23	1385	0
T24	496	0
T26	696	3
T27	0	5
T28	0	5
T33	0	5
T40	0	5
T43	0	5
T44	0	12
T45	0	4
T46	0	4
T47	403	0
T48	419	0
T49	422	0
T50	493	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1417
T8	215910	0
T9	934258	0
T10	641521	0
T21	0	11
T23	332675	0
T24	62063	0
T26	132249	3
T27	0	5
T28	0	5
T33	0	5
T40	0	5
T43	0	5
T44	0	12
T45	0	4
T46	0	4
T47	185527	0
T48	209521	0
T49	202521	0
T50	234106	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1407	0	0
SrcPulseCheck_M	8529885	1407	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1407
T8	215910	0
T9	934258	0
T10	641521	0
T21	0	11
T23	332675	0
T24	62063	0
T26	132249	3
T27	0	5
T28	0	5
T33	0	5
T40	0	5
T43	0	5
T44	0	12
T45	0	4
T46	0	4
T47	185527	0
T48	209521	0
T49	202521	0
T50	234106	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1407
T8	492	0
T9	18685	0
T10	25660	0
T21	0	11
T23	1385	0
T24	496	0
T26	696	3
T27	0	5
T28	0	5
T33	0	5
T40	0	5
T43	0	5
T44	0	12
T45	0	4
T46	0	4
T47	403	0
T48	419	0
T49	422	0
T50	493	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1146	0	0
SrcPulseCheck_M	1292524677	1220	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1146
T8	492	0
T9	18685	0
T10	25660	0
T21	0	8
T23	1385	0
T24	496	0
T26	696	3
T27	0	3
T28	0	3
T33	0	3
T40	0	3
T43	0	3
T44	0	6
T45	0	3
T46	0	3
T47	403	0
T48	419	0
T49	422	0
T50	493	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1220
T8	215910	0
T9	934258	0
T10	641521	0
T21	0	8
T23	332675	0
T24	62063	0
T26	132249	3
T27	0	3
T28	0	3
T33	0	3
T40	0	3
T43	0	3
T44	0	6
T45	0	3
T46	0	3
T47	185527	0
T48	209521	0
T49	202521	0
T50	234106	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T27,T28
1	0	Covered	T26,T27,T28
1	1	Covered	T26,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1211	0	0
SrcPulseCheck_M	8529885	1211	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1211
T8	215910	0
T9	934258	0
T10	641521	0
T21	0	8
T23	332675	0
T24	62063	0
T26	132249	3
T27	0	3
T28	0	3
T33	0	3
T40	0	3
T43	0	3
T44	0	6
T45	0	3
T46	0	3
T47	185527	0
T48	209521	0
T49	202521	0
T50	234106	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1211
T8	492	0
T9	18685	0
T10	25660	0
T21	0	8
T23	1385	0
T24	496	0
T26	696	3
T27	0	3
T28	0	3
T33	0	3
T40	0	3
T43	0	3
T44	0	6
T45	0	3
T46	0	3
T47	403	0
T48	419	0
T49	422	0
T50	493	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T13,T7,T29
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7086	0	0
SrcPulseCheck_M	1292524677	7167	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7086
T4	930	0
T7	16409	59
T10	0	66
T11	0	73
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	1
T31	0	66
T41	0	97
T42	0	51
T69	0	71
T70	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7167
T4	175226	0
T7	763058	60
T10	0	66
T11	0	73
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	1
T31	0	66
T41	0	97
T42	0	51
T69	0	71
T70	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T13,T7,T29
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7158	0	0
SrcPulseCheck_M	8529885	7158	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7158
T4	175226	0
T7	763058	60
T10	0	66
T11	0	73
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	1
T31	0	66
T41	0	97
T42	0	51
T69	0	71
T70	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7158
T4	930	0
T7	16409	60
T10	0	66
T11	0	73
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	1
T31	0	66
T41	0	97
T42	0	51
T69	0	71
T70	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	6855	0	0
SrcPulseCheck_M	1292524677	6935	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	6855
T4	930	0
T7	16409	58
T10	0	81
T11	0	72
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	64
T41	0	72
T42	0	51
T69	0	51
T70	0	51
T71	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	6935
T4	175226	0
T7	763058	59
T10	0	81
T11	0	72
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	64
T41	0	72
T42	0	51
T69	0	51
T70	0	51
T71	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	6924	0	0
SrcPulseCheck_M	8529885	6924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	6924
T4	175226	0
T7	763058	59
T10	0	81
T11	0	72
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	64
T41	0	72
T42	0	51
T69	0	51
T70	0	51
T71	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	6924
T4	930	0
T7	16409	59
T10	0	81
T11	0	72
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	64
T41	0	72
T42	0	51
T69	0	51
T70	0	51
T71	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7008	0	0
SrcPulseCheck_M	1292524677	7089	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7008
T4	930	0
T7	16409	63
T10	0	81
T11	0	75
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	67
T41	0	91
T42	0	51
T69	0	71
T70	0	51
T71	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7089
T4	175226	0
T7	763058	64
T10	0	81
T11	0	75
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	67
T41	0	91
T42	0	51
T69	0	71
T70	0	51
T71	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7081	0	0
SrcPulseCheck_M	8529885	7081	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7081
T4	175226	0
T7	763058	64
T10	0	81
T11	0	75
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	67
T41	0	91
T42	0	51
T69	0	71
T70	0	51
T71	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7081
T4	930	0
T7	16409	64
T10	0	81
T11	0	75
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	67
T41	0	91
T42	0	51
T69	0	71
T70	0	51
T71	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7011	0	0
SrcPulseCheck_M	1292524677	7095	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7011
T4	930	0
T7	16409	63
T10	0	79
T11	0	81
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	71
T41	0	75
T42	0	51
T69	0	71
T70	0	51
T71	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7095
T4	175226	0
T7	763058	64
T10	0	79
T11	0	81
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	71
T41	0	75
T42	0	51
T69	0	71
T70	0	51
T71	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7085	0	0
SrcPulseCheck_M	8529885	7085	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7085
T4	175226	0
T7	763058	64
T10	0	79
T11	0	81
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	71
T41	0	75
T42	0	51
T69	0	71
T70	0	51
T71	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7085
T4	930	0
T7	16409	64
T10	0	79
T11	0	81
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	71
T41	0	75
T42	0	51
T69	0	71
T70	0	51
T71	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T13,T7,T29
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1165	0	0
SrcPulseCheck_M	1292524677	1238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1165
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	1
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1238
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	1
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T13,T7,T29
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T29
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T29

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1232	0	0
SrcPulseCheck_M	8529885	1232	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1232
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	1
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1232
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	1
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1174	0	0
SrcPulseCheck_M	1292524677	1248	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1174
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1248
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1242	0	0
SrcPulseCheck_M	8529885	1242	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1242
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1242
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1171	0	0
SrcPulseCheck_M	1292524677	1247	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1171
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1247
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1237	0	0
SrcPulseCheck_M	8529885	1237	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1237
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1237
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1163	0	0
SrcPulseCheck_M	1292524677	1233	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1163
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1233
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T13,T7,T10
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T13,T7,T10
1	0	Covered	T74,T75,T16
1	1	Covered	T13,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1223	0	0
SrcPulseCheck_M	8529885	1223	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1223
T4	175226	0
T7	763058	5
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T23	332675	0
T24	62063	0
T26	132249	0
T29	56288	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1223
T4	930	0
T7	16409	5
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T23	1385	0
T24	496	0
T26	696	0
T29	469	0
T31	0	2
T41	0	8
T42	0	1
T69	0	1
T70	0	1
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7702	0	0
SrcPulseCheck_M	1292524677	7779	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7702
T2	14513	5
T3	958	0
T4	930	0
T7	16409	59
T9	0	7
T10	0	66
T11	0	73
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	1
T31	0	66
T32	0	11
T33	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7779
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	60
T9	0	7
T10	0	66
T11	0	73
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	1
T31	0	66
T32	0	11
T33	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7769	0	0
SrcPulseCheck_M	8529885	7769	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7769
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	60
T9	0	7
T10	0	66
T11	0	73
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	1
T31	0	66
T32	0	11
T33	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7769
T2	14513	5
T3	958	0
T4	930	0
T7	16409	60
T9	0	7
T10	0	66
T11	0	73
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	1
T31	0	66
T32	0	11
T33	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7399	0	0
SrcPulseCheck_M	1292524677	7478	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7399
T2	14513	5
T3	958	0
T4	930	0
T7	16409	58
T9	0	7
T10	0	81
T11	0	72
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	64
T32	0	11
T41	0	72
T42	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7478
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	59
T9	0	7
T10	0	81
T11	0	72
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	64
T32	0	11
T41	0	72
T42	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7468	0	0
SrcPulseCheck_M	8529885	7468	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7468
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	59
T9	0	7
T10	0	81
T11	0	72
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	64
T32	0	11
T41	0	72
T42	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7468
T2	14513	5
T3	958	0
T4	930	0
T7	16409	59
T9	0	7
T10	0	81
T11	0	72
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	64
T32	0	11
T41	0	72
T42	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7551	0	0
SrcPulseCheck_M	1292524677	7632	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7551
T2	14513	5
T3	958	0
T4	930	0
T7	16409	63
T9	0	7
T10	0	81
T11	0	75
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	67
T32	0	11
T41	0	91
T42	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7632
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	64
T9	0	7
T10	0	81
T11	0	75
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	67
T32	0	11
T41	0	91
T42	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7623	0	0
SrcPulseCheck_M	8529885	7623	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7623
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	64
T9	0	7
T10	0	81
T11	0	75
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	67
T32	0	11
T41	0	91
T42	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7623
T2	14513	5
T3	958	0
T4	930	0
T7	16409	64
T9	0	7
T10	0	81
T11	0	75
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	67
T32	0	11
T41	0	91
T42	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	7573	0	0
SrcPulseCheck_M	1292524677	7653	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	7573
T2	14513	5
T3	958	0
T4	930	0
T7	16409	63
T9	0	7
T10	0	79
T11	0	81
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	71
T32	0	11
T41	0	75
T42	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	7653
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	64
T9	0	7
T10	0	79
T11	0	81
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	71
T32	0	11
T41	0	75
T42	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T13,T7,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T13,T7,T10
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	7644	0	0
SrcPulseCheck_M	8529885	7644	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	7644
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	64
T9	0	7
T10	0	79
T11	0	81
T13	546860	51
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	71
T32	0	11
T41	0	75
T42	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	7644
T2	14513	5
T3	958	0
T4	930	0
T7	16409	64
T9	0	7
T10	0	79
T11	0	81
T13	4971	51
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	71
T32	0	11
T41	0	75
T42	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1785	0	0
SrcPulseCheck_M	1292524677	1857	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1785
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	1
T31	0	2
T32	0	11
T33	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1857
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	1
T31	0	2
T32	0	11
T33	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1846	0	0
SrcPulseCheck_M	8529885	1846	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1846
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	1
T31	0	2
T32	0	11
T33	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1846
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	1
T31	0	2
T32	0	11
T33	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1656	0	0
SrcPulseCheck_M	1292524677	1730	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1656
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1730
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1721	0	0
SrcPulseCheck_M	8529885	1721	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1721
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1721
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1715	0	0
SrcPulseCheck_M	1292524677	1788	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1715
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1788
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1778	0	0
SrcPulseCheck_M	8529885	1778	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1778
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1778
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1679	0	0
SrcPulseCheck_M	1292524677	1756	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1679
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1756
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1745	0	0
SrcPulseCheck_M	8529885	1745	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1745
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1745
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1794	0	0
SrcPulseCheck_M	1292524677	1869	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1794
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	1
T31	0	2
T32	0	11
T33	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1869
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	1
T31	0	2
T32	0	11
T33	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1859	0	0
SrcPulseCheck_M	8529885	1859	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1859
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	1
T31	0	2
T32	0	11
T33	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1859
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	1
T31	0	2
T32	0	11
T33	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1720	0	0
SrcPulseCheck_M	1292524677	1794	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1720
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1794
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1785	0	0
SrcPulseCheck_M	8529885	1785	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1785
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1785
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1722	0	0
SrcPulseCheck_M	1292524677	1797	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1722
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1797
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1788	0	0
SrcPulseCheck_M	8529885	1788	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1788
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1788
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8529885	1722	0	0
SrcPulseCheck_M	1292524677	1797	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8529885	1722
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1292524677	1797
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T2,T13,T7
1	1	Covered	T74,T75,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T2,T13,T7
1	0	Covered	T74,T75,T16
1	1	Covered	T2,T13,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1292524677	1788	0	0
SrcPulseCheck_M	8529885	1788	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1292524677	1788
T2	703921	5
T3	324674	0
T4	175226	0
T7	763058	5
T9	0	7
T10	0	9
T11	0	4
T13	546860	1
T14	58412	0
T15	44838	0
T22	61947	0
T26	132249	0
T29	56288	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8529885	1788
T2	14513	5
T3	958	0
T4	930	0
T7	16409	5
T9	0	7
T10	0	9
T11	0	4
T13	4971	1
T14	507	0
T15	408	0
T22	496	0
T26	696	0
T29	469	0
T31	0	2
T32	0	11
T41	0	8
T42	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc