Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2042

1

T1

2

T3

20

T6

2

auto[1]

829

1

T6

2

T7

15

T8

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2238

1

T1

1

T3

17

T6

3

auto[1]

633

1

T1

1

T3

3

T6

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2195

1

T1

1

T3

13

T6

2

auto[1]

676

1

T1

1

T3

7

T6

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2215

1

T1

1

T3

11

T6

2

auto[1]

656

1

T1

1

T3

9

T6

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2669

1

T1

2

T3

15

T6

4

auto[1]

202

1

T3

5

T10

12

T46

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2642

1

T1

2

T3

14

T6

4

auto[1]

229

1

T3

6

T10

15

T30

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2654

1

T1

2

T3

20

T6

4

auto[1]

217

1

T30

21

T46

3

T62

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2650

1

T1

2

T3

20

T6

4

auto[1]

221

1

T10

9

T30

8

T46

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2615

1

T1

2

T3

18

T6

4

auto[1]

256

1

T3

2

T10

3

T30

13

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2247

1

T3

20

T6

2

T7

7

auto[1]

624

1

T1

2

T6

2

T7

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	953	1			T1	2		T6	3		T7	3
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	67	1			T3	3		T304	6		T300	7
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	99	1			T47	22		T62	5		T305	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	26	1			T304	3		T71	6		T397	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	105	1			T46	3		T62	7		T398	12
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T47	11		T300	1		T303	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	16	1			T47	10		T71	3		T399	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	10	1			T10	1		T78	1		T397	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	79	1			T62	3		T65	2		T305	9
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T46	3		T300	3		T393	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	44	1			T30	7		T398	5		T400	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T384	1		T392	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T30	8		T386	1		T401	10
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T402	1		T249	1		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	5	1			T78	1		T403	4		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	93	1			T3	4		T64	1		T298	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	24	1			T10	8		T313	2		T398	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	14	1			T299	6		T394	2		T404	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	12	1			T3	2		T199	1		T286	9
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	21	1			T10	5		T398	4		T395	5
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	13	1			T405	1		T392	12		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	10	1			T303	1		T406	9		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T403	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T30	6		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T407	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

165

1

T30

6

T32

12

T305

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

106

1

T30

8

T62

3

T300

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T44

6

T307

2

T65

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

107

1

T3

2

T10

8

T312

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

87

1

T47

22

T314

7

T299

15

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T1

1

T46

3

T53

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T11

6

T111

3

T80

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

140

1

T10

6

T36

1

T62

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

88

1

T6

1

T8

4

T299

15

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

58

1

T8

3

T75

3

T33

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T44

2

T32

2

T33

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

67

1

T3

4

T408

4

T80

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T81

1

T82

2

T409

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

28

1

T6

1

T32

3

T313

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T76

3

T64

1

T381

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

130

1

T47

10

T78

1

T400

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

71

1

T398

5

T381

4

T410

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T6

1

T8

6

T47

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T312

5

T178

2

T272

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T304

3

T300

7

T303

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T30

7

T312

2

T53

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T11

4

T77

6

T298

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T411

2

T382

1

T316

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T46

3

T412

6

T215

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T413

3

T397

9

T390

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T1

1

T33

2

T100

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T414

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

15

1

T3

3

T36

1

T111

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T7

3

T209

2

T388

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T381

3

T405

1

T142

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T11

3

T142

3

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded