Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T1

9

T15

14

T48

14

auto[1]

1026

1

T1

11

T15

6

T48

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T1

5

T15

5

T48

5

from_0to1

506

1

T1

5

T15

5

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T1

11

T15

10

T48

5

auto[1]

1066

1

T1

9

T15

10

T48

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T1

12

T15

10

T48

8

auto[1]

1070

1

T1

8

T15

10

T48

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T1

1

T15

2

T59

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T15

2

T25

2

T23

2

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T15

1

T25

1

T95

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T48

4

T59

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T59

2

T25

2

T23

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T1

1

T15

1

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T15

1

T48

1

T59

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T48

1

T59

1

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T1

2

T59

2

T25

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T48

1

T59

2

T23

2

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T59

1

T95

1

T422

2

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T1

2

T60

1

T31

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T1

2

T15

1

T95

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T1

1

T15

1

T48

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T1

1

T15

1

T59

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T48

1

T95

1

T36

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T1

13

T15

8

T48

11

auto[1]

1067

1

T1

7

T15

12

T48

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T1

5

T15

3

T48

4

from_0to1

498

1

T1

5

T15

2

T48

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T1

10

T15

10

T48

10

auto[1]

1059

1

T1

10

T15

10

T48

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T1

11

T15

10

T48

10

auto[1]

1062

1

T1

9

T15

10

T48

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T59

1

T25

1

T36

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T1

1

T15

1

T59

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T1

1

T48

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T48

1

T59

1

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T1

1

T15

1

T59

2

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T1

1

T48

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T1

1

T59

1

T25

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T48

1

T25

1

T23

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T48

1

T60

2

T95

2

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T1

1

T59

1

T95

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T1

1

T15

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T1

1

T15

1

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T25

2

T31

1

T23

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T1

2

T15

1

T59

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T59

1

T25

1

T31

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T48

2

T60

1

T95

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T1

9

T15

8

T48

8

auto[1]

1065

1

T1

11

T15

12

T48

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T1

4

T15

7

T48

4

from_0to1

513

1

T1

4

T15

6

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T1

10

T15

7

T48

10

auto[1]

1040

1

T1

10

T15

13

T48

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T1

9

T15

9

T48

12

auto[1]

1049

1

T1

11

T15

11

T48

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T15

1

T48

1

T95

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T1

1

T59

2

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T15

1

T25

2

T31

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T15

1

T48

1

T59

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T1

2

T48

2

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T15

1

T48

1

T25

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T15

2

T59

1

T95

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T1

1

T48

1

T59

1

auto[1]

from_1to0

auto[0]

auto[0]

82

1

T15

1

T25

2

T95

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T1

1

T15

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T1

2

T59

1

T25

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T15

2

T48

1

T59

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T109

1

T422

2

T36

3

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T48

1

T59

1

T25

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T59

1

T25

1

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T1

1

T15

3

T59

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T1

9

T15

12

T48

12

auto[1]

1106

1

T1

11

T15

8

T48

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T1

5

T15

3

T48

7

from_0to1

517

1

T1

5

T15

4

T48

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T1

10

T15

11

T48

8

auto[1]

1095

1

T1

10

T15

9

T48

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T1

11

T15

12

T48

9

auto[1]

1032

1

T1

9

T15

8

T48

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T25

1

T95

1

T23

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T48

1

T60

2

T23

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T1

1

T15

1

T48

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T15

1

T59

2

T25

4

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T1

1

T15

2

T48

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T1

1

T15

1

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

81

1

T1

1

T48

1

T59

2

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T1

1

T48

2

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T48

1

T59

2

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T59

1

T60

1

T25

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T15

1

T48

1

T25

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T1

4

T48

2

T31

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T1

1

T25

1

T95

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T15

1

T60

1

T95

1

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T48

1

T59

1

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T48

1

T59

1

T25

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T1

14

T15

11

T48

10

auto[1]

1068

1

T1

6

T15

9

T48

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T1

3

T15

4

T48

6

from_0to1

488

1

T1

3

T15

4

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T1

7

T15

11

T48

11

auto[1]

1060

1

T1

13

T15

9

T48

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T1

11

T15

10

T48

15

auto[1]

1030

1

T1

9

T15

10

T48

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T59

1

T25

1

T95

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T1

2

T15

2

T48

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T109

1

T36

1

T423

2

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T48

2

T60

1

T95

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T48

2

T60

1

T23

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T422

1

T36

2

T423

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T1

1

T59

1

T95

3

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T15

1

T48

1

T59

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T15

1

T48

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T48

1

T25

1

T95

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T15

1

T48

1

T59

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T1

1

T59

2

T25

3

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T1

1

T48

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T15

1

T59

1

T25

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T1

1

T15

1

T48

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T15

1

T59

1

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T1

9

T15

12

T48

10

auto[1]

1047

1

T1

11

T15

8

T48

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T1

5

T15

5

T48

3

from_0to1

510

1

T1

5

T15

5

T48

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T1

11

T15

11

T48

12

auto[1]

1111

1

T1

9

T15

9

T48

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T1

6

T15

10

T48

9

auto[1]

1102

1

T1

14

T15

10

T48

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T1

1

T15

1

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T25

1

T31

2

T109

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T48

1

T59

1

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T15

1

T23

2

T36

3

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T15

1

T95

1

T109

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T15

1

T48

2

T23

3

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T15

2

T25

1

T31

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T1

1

T60

1

T25

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T1

1

T15

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T1

1

T15

1

T59

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T1

1

T25

1

T95

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T1

1

T15

1

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T1

2

T15

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T48

2

T60

1

T25

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T59

3

T60

2

T31

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T1

2

T59

1

T95

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T1

11

T15

11

T48

11

auto[1]

1111

1

T1

9

T15

9

T48

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T1

5

T15

4

T48

4

from_0to1

481

1

T1

5

T15

4

T48

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T1

10

T15

9

T48

6

auto[1]

1084

1

T1

10

T15

11

T48

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T1

13

T15

10

T48

10

auto[1]

1060

1

T1

7

T15

10

T48

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T59

1

T23

1

T422

2

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T95

2

T31

2

T23

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T1

2

T59

2

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T1

1

T59

1

T25

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T1

1

T48

1

T59

2

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T1

1

T15

1

T25

3

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T1

2

T15

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T48

2

T23

1

T36

2

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T15

1

T59

1

T60

3

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T15

1

T48

1

T31

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T1

1

T48

2

T25

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T1

1

T15

2

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T1

1

T23

2

T109

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T15

1

T59

1

T60

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T15

1

T48

2

T59

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T59

2

T95

1

T31

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T1

11

T15

12

T48

8

auto[1]

1093

1

T1

9

T15

8

T48

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T1

3

T15

7

T48

5

from_0to1

511

1

T1

4

T15

6

T48

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T1

14

T15

12

T48

9

auto[1]

1031

1

T1

6

T15

8

T48

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T1

15

T15

9

T48

11

auto[1]

1041

1

T1

5

T15

11

T48

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T1

1

T15

1

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T15

1

T25

1

T31

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T1

2

T15

1

T59

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T15

1

T48

2

T59

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T1

2

T15

1

T59

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T1

1

T15

2

T59

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T48

1

T59

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T15

1

T25

1

T95

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T48

1

T60

1

T25

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T15

2

T48

1

T59

1

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T59

1

T60

1

T23

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T15

1

T60

1

T31

3

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T48

1

T23

3

T109

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T48

1

T60

3

T25

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T1

1

T15

1

T48

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T15

1

T48

2

T25

1