Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	161078	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122011

1

T1

322

T4

147

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146365	1			T1	444		T4	37		T5	10
values[0x0]	68005	1			T1	94		T4	131		T5	1
values[0x1]	68719	1			T1	75		T4	108		T13	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130645	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152444

1

T1

391

T4

166

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	948	1			T1	1		T48	2		T3	2
valid_sources[0x01]	801	1			T1	2		T3	8		T7	2
valid_sources[0x02]	1064	1			T1	2		T3	1		T59	1
valid_sources[0x03]	901	1			T1	3		T3	3		T6	2
valid_sources[0x04]	1243	1			T1	8		T48	1		T3	5
valid_sources[0x05]	801	1			T1	4		T3	3		T59	1
valid_sources[0x06]	2527	1			T3	6		T6	3		T60	5
valid_sources[0x07]	1108	1			T1	4		T15	13		T48	2
valid_sources[0x08]	1227	1			T1	2		T48	1		T3	4
valid_sources[0x09]	959	1			T1	2		T3	4		T6	9
valid_sources[0x0a]	984	1			T1	2		T5	1		T3	3
valid_sources[0x0b]	1297	1			T1	3		T3	6		T59	1
valid_sources[0x0c]	1081	1			T1	3		T3	2		T59	1
valid_sources[0x0d]	677	1			T1	1		T13	1		T48	1
valid_sources[0x0e]	1038	1			T1	3		T3	1		T6	13
valid_sources[0x0f]	942	1			T1	1		T3	3		T60	1
valid_sources[0x10]	953	1			T1	4		T48	1		T3	5
valid_sources[0x11]	1301	1			T1	6		T3	3		T6	9
valid_sources[0x12]	776	1			T1	2		T3	5		T59	1
valid_sources[0x13]	827	1			T1	3		T13	1		T3	4
valid_sources[0x14]	1725	1			T1	2		T40	3		T3	6
valid_sources[0x15]	1372	1			T1	3		T4	276		T48	1
valid_sources[0x16]	1290	1			T1	3		T3	3		T59	1
valid_sources[0x17]	1990	1			T39	1		T3	3		T145	2
valid_sources[0x18]	897	1			T1	2		T13	1		T48	2
valid_sources[0x19]	1036	1			T1	3		T48	2		T3	5
valid_sources[0x1a]	968	1			T3	5		T59	1		T6	3
valid_sources[0x1b]	762	1			T1	1		T3	3		T59	2
valid_sources[0x1c]	927	1			T1	1		T3	7		T42	1
valid_sources[0x1d]	769	1			T1	4		T5	1		T14	3
valid_sources[0x1e]	865	1			T1	3		T3	2		T60	1
valid_sources[0x1f]	925	1			T1	4		T48	5		T3	2
valid_sources[0x20]	845	1			T1	2		T3	3		T6	2
valid_sources[0x21]	811	1			T59	1		T7	7		T8	1
valid_sources[0x22]	733	1			T1	1		T48	1		T6	11
valid_sources[0x23]	999	1			T1	3		T3	6		T7	5
valid_sources[0x24]	1157	1			T1	4		T48	1		T2	4
valid_sources[0x25]	735	1			T48	3		T40	3		T3	2
valid_sources[0x26]	947	1			T1	6		T3	6		T6	11
valid_sources[0x27]	1435	1			T1	1		T13	2		T3	7
valid_sources[0x28]	2054	1			T1	2		T48	2		T3	4
valid_sources[0x29]	1186	1			T1	3		T3	8		T59	1
valid_sources[0x2a]	1103	1			T1	4		T3	3		T59	2
valid_sources[0x2b]	997	1			T1	1		T3	1		T59	2
valid_sources[0x2c]	1040	1			T1	3		T13	4		T48	4
valid_sources[0x2d]	1114	1			T1	3		T3	5		T6	21
valid_sources[0x2e]	1346	1			T1	1		T3	5		T42	1
valid_sources[0x2f]	1402	1			T1	2		T13	1		T48	4
valid_sources[0x30]	928	1			T1	2		T3	2		T6	1
valid_sources[0x31]	886	1			T1	5		T48	2		T3	3
valid_sources[0x32]	1202	1			T1	2		T3	5		T59	1
valid_sources[0x33]	1024	1			T1	3		T48	1		T3	6
valid_sources[0x34]	1604	1			T1	4		T48	1		T3	8
valid_sources[0x35]	1082	1			T1	1		T16	1		T3	1
valid_sources[0x36]	964	1			T5	1		T3	5		T41	4
valid_sources[0x37]	784	1			T1	3		T3	5		T60	2
valid_sources[0x38]	1348	1			T1	2		T48	2		T3	7
valid_sources[0x39]	689	1			T1	1		T3	3		T59	1
valid_sources[0x3a]	808	1			T1	1		T3	3		T59	1
valid_sources[0x3b]	1991	1			T1	3		T3	2		T59	1
valid_sources[0x3c]	931	1			T1	6		T19	6		T3	5
valid_sources[0x3d]	2267	1			T1	6		T48	1		T3	3
valid_sources[0x3e]	2014	1			T1	3		T3	2		T25	1
valid_sources[0x3f]	986	1			T206	9		T3	3		T6	3
valid_sources[0x40]	1758	1			T1	3		T13	3		T3	3
valid_sources[0x41]	882	1			T3	1		T6	14		T7	4
valid_sources[0x42]	792	1			T1	2		T3	4		T60	1
valid_sources[0x43]	1459	1			T1	3		T13	1		T48	1
valid_sources[0x44]	958	1			T1	1		T3	4		T6	6
valid_sources[0x45]	880	1			T1	2		T13	1		T3	1
valid_sources[0x46]	1302	1			T1	1		T13	3		T39	2
valid_sources[0x47]	950	1			T1	5		T3	8		T59	1
valid_sources[0x48]	1049	1			T3	1		T7	3		T8	1
valid_sources[0x49]	938	1			T1	2		T5	1		T48	2
valid_sources[0x4a]	1070	1			T1	3		T16	1		T3	4
valid_sources[0x4b]	1121	1			T1	3		T16	1		T3	7
valid_sources[0x4c]	1182	1			T1	2		T48	2		T39	2
valid_sources[0x4d]	778	1			T1	3		T3	6		T42	2
valid_sources[0x4e]	1298	1			T1	5		T48	1		T2	6
valid_sources[0x4f]	1027	1			T1	1		T13	6		T3	2
valid_sources[0x50]	1534	1			T3	7		T7	2		T8	3
valid_sources[0x51]	1139	1			T1	2		T3	5		T59	1
valid_sources[0x52]	918	1			T3	1		T6	9		T60	2
valid_sources[0x53]	740	1			T1	2		T2	2		T3	3
valid_sources[0x54]	1021	1			T1	2		T3	2		T25	1
valid_sources[0x55]	1033	1			T1	5		T3	4		T60	2
valid_sources[0x56]	777	1			T1	3		T48	3		T3	2
valid_sources[0x57]	850	1			T1	3		T40	1		T3	2
valid_sources[0x58]	800	1			T40	3		T3	5		T59	1
valid_sources[0x59]	883	1			T1	1		T3	8		T6	7
valid_sources[0x5a]	1171	1			T1	3		T3	3		T59	2
valid_sources[0x5b]	889	1			T1	2		T3	3		T59	1
valid_sources[0x5c]	950	1			T1	2		T5	1		T39	2
valid_sources[0x5d]	965	1			T1	4		T3	2		T7	1
valid_sources[0x5e]	961	1			T1	2		T3	2		T6	24
valid_sources[0x5f]	966	1			T1	2		T48	2		T3	5
valid_sources[0x60]	1848	1			T1	1		T13	4		T48	1
valid_sources[0x61]	1620	1			T1	7		T13	2		T3	4
valid_sources[0x62]	987	1			T1	1		T13	4		T3	8
valid_sources[0x63]	823	1			T3	4		T6	6		T7	2
valid_sources[0x64]	2063	1			T1	1		T7	1		T8	2
valid_sources[0x65]	834	1			T3	5		T7	4		T9	2
valid_sources[0x66]	1976	1			T1	3		T13	1		T39	1
valid_sources[0x67]	744	1			T1	3		T3	1		T59	1
valid_sources[0x68]	817	1			T1	10		T3	2		T6	5
valid_sources[0x69]	874	1			T1	1		T3	2		T6	4
valid_sources[0x6a]	855	1			T1	4		T3	3		T6	5
valid_sources[0x6b]	928	1			T1	4		T3	2		T6	4
valid_sources[0x6c]	1151	1			T5	1		T3	4		T7	6
valid_sources[0x6d]	1080	1			T1	9		T6	5		T25	2
valid_sources[0x6e]	977	1			T1	1		T15	11		T3	1
valid_sources[0x6f]	769	1			T1	4		T3	5		T59	1
valid_sources[0x70]	1001	1			T1	1		T3	5		T7	2
valid_sources[0x71]	885	1			T1	4		T5	2		T48	1
valid_sources[0x72]	1167	1			T1	1		T17	31		T48	2
valid_sources[0x73]	782	1			T1	1		T48	1		T3	4
valid_sources[0x74]	1045	1			T1	1		T3	6		T59	1
valid_sources[0x75]	1058	1			T1	3		T39	2		T3	4
valid_sources[0x76]	1169	1			T1	4		T13	1		T3	2
valid_sources[0x77]	1713	1			T1	2		T3	7		T60	1
valid_sources[0x78]	1334	1			T1	6		T3	1		T6	2
valid_sources[0x79]	950	1			T1	4		T3	5		T24	1
valid_sources[0x7a]	2816	1			T1	3		T3	4		T6	2
valid_sources[0x7b]	866	1			T1	2		T3	2		T6	1
valid_sources[0x7c]	760	1			T1	1		T59	1		T60	3
valid_sources[0x7d]	672	1			T1	4		T3	3		T59	1
valid_sources[0x7e]	821	1			T1	4		T3	4		T59	2
valid_sources[0x7f]	1214	1			T1	5		T59	1		T6	2
valid_sources[0x80]	900	1			T1	4		T48	2		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66414

1

T1

248

T4

20

T5

6

values[0x0]

all_enables

biggest_size

32812

1

T1

46

T4

78

T13

10

values[0x1]

all_enables

biggest_size

22785

1

T1

28

T4

49

T13

3