Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T4,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T39
0	1	Covered	T88,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T39
0	1	Covered	T1,T14,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T39
1	-	Covered	T1,T14,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T14
DetectSt	168	Covered	T1,T14,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T14,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T39
DebounceSt->IdleSt	163	Covered	T4,T6,T31
DetectSt->IdleSt	186	Covered	T88,T91,T92
DetectSt->StableSt	191	Covered	T1,T14,T39
IdleSt->DebounceSt	148	Covered	T1,T4,T14
StableSt->IdleSt	206	Covered	T1,T14,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T14
0	1	Covered	T1,T4,T14
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T31,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T14
DetectSt	-	-	-	-	1	-	-	Covered	T88,T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T14,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	293	0	0
CntIncr_A	6439628	24491	0	0
CntNoWrap_A	6439628	5753235	0	0
DetectStDropOut_A	6439628	3	0	0
DetectedOut_A	6439628	795	0	0
DetectedPulseOut_A	6439628	125	0	0
DisabledIdleSt_A	6439628	5722375	0	0
DisabledNoDetection_A	6439628	5724814	0	0
EnterDebounceSt_A	6439628	166	0	0
EnterDetectSt_A	6439628	128	0	0
EnterStableSt_A	6439628	125	0	0
PulseIsPulse_A	6439628	125	0	0
StayInStableSt	6439628	670	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	7214	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	293	0	0
T1	9484	6	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	10	0	0
T9	0	4	0	0
T13	527	0	0	0
T14	729	4	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	24491	0	0
T1	9484	264	0	0
T4	7201	23	0	0
T5	409	0	0	0
T6	0	292	0	0
T9	0	98	0	0
T13	527	0	0	0
T14	729	158	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T39	0	27	0	0
T40	0	35	0	0
T41	0	33	0	0
T42	0	92	0	0
T74	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753235	0	0
T1	9484	5414	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	324	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3	0	0
T88	671	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T97	507	0	0	0
T98	4876	0	0	0
T99	3695	0	0	0
T100	20105	0	0	0
T101	560	0	0	0
T102	522	0	0	0
T103	489	0	0	0
T104	533	0	0	0
T105	528	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	795	0	0
T1	9484	24	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	38	0	0
T9	0	13	0	0
T13	527	0	0	0
T14	729	12	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	23	0	0
T39	0	3	0	0
T40	0	6	0	0
T41	0	7	0	0
T42	0	6	0	0
T74	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	125	0	0
T1	9484	3	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	4	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	2	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T74	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5722375	0	0
T1	9484	5017	0	0
T4	7201	6771	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	82	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5724814	0	0
T1	9484	5027	0	0
T4	7201	6772	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	83	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	166	0	0
T1	9484	3	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	6	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	2	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	128	0	0
T1	9484	3	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	4	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	2	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T74	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	125	0	0
T1	9484	3	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	4	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	2	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T74	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	125	0	0
T1	9484	3	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	4	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	2	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T74	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	670	0	0
T1	9484	21	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	34	0	0
T9	0	11	0	0
T13	527	0	0	0
T14	729	10	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	20	0	0
T39	0	2	0	0
T40	0	5	0	0
T41	0	6	0	0
T42	0	5	0	0
T74	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	7214	0	0
T1	9484	22	0	0
T4	7201	36	0	0
T5	409	0	0	0
T13	527	6	0	0
T14	729	3	0	0
T15	502	6	0	0
T16	405	0	0	0
T17	436	3	0	0
T18	435	4	0	0
T19	633	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	125	0	0
T1	9484	3	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	4	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	2	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T74	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T29,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T23
1	0	Covered	T1,T4,T13
1	1	Covered	T4,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T29,T51
0	1	Covered	T7,T66,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T29,T51
0	1	Unreachable
1	0	Covered	T7,T29,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T23
DetectSt	168	Covered	T7,T29,T51
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T29,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T29,T51
DebounceSt->IdleSt	163	Covered	T4,T7,T23
DetectSt->IdleSt	186	Covered	T7,T66,T73
DetectSt->StableSt	191	Covered	T7,T29,T51
IdleSt->DebounceSt	148	Covered	T4,T7,T23
StableSt->IdleSt	206	Covered	T7,T29,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T23
0	1	Covered	T4,T7,T23
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T29,T51
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T29,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T23,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T23
DetectSt	-	-	-	-	1	-	-	Covered	T7,T66,T73
DetectSt	-	-	-	-	0	1	-	Covered	T7,T29,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T29,T51
StableSt	-	-	-	-	-	-	0	Covered	T7,T29,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	194	0	0
CntIncr_A	6439628	14010	0	0
CntNoWrap_A	6439628	5753334	0	0
DetectStDropOut_A	6439628	21	0	0
DetectedOut_A	6439628	40791	0	0
DetectedPulseOut_A	6439628	44	0	0
DisabledIdleSt_A	6439628	5345620	0	0
DisabledNoDetection_A	6439628	5348106	0	0
EnterDebounceSt_A	6439628	131	0	0
EnterDetectSt_A	6439628	65	0	0
EnterStableSt_A	6439628	44	0	0
PulseIsPulse_A	6439628	44	0	0
StayInStableSt	6439628	40747	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	7214	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_sticky_sva.StableStDropOut_A	6439628	57535	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	194	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	2	0	0
T29	0	2	0	0
T36	0	2	0	0
T48	506	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	4	0	0
T54	0	2	0	0
T66	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	14010	0	0
T4	7201	74	0	0
T5	409	0	0	0
T7	0	194	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	54	0	0
T29	0	74	0	0
T36	0	97	0	0
T48	506	0	0	0
T51	0	40	0	0
T52	0	92	0	0
T53	0	145	0	0
T54	0	65	0	0
T66	0	356	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753334	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	21	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T50	1121	0	0	0
T66	0	1	0	0
T73	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T115	0	2	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	5	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40791	0	0
T7	295293	272	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	11	0	0
T36	0	385	0	0
T50	1121	0	0	0
T51	0	255	0	0
T52	0	52	0	0
T53	0	288	0	0
T54	0	29	0	0
T66	0	273	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	996	0	0
T114	0	239	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	44	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T66	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	3	0	0
T114	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5345620	0	0
T1	9484	5420	0	0
T4	7201	6720	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5348106	0	0
T1	9484	5431	0	0
T4	7201	6720	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	131	0	0
T4	7201	2	0	0
T5	409	0	0	0
T7	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	2	0	0
T29	0	1	0	0
T36	0	1	0	0
T48	506	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T66	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65	0	0
T7	295293	2	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T66	0	3	0	0
T73	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	44	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T66	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	3	0	0
T114	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	44	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T66	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	3	0	0
T114	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40747	0	0
T7	295293	271	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	10	0	0
T36	0	384	0	0
T50	1121	0	0	0
T51	0	254	0	0
T52	0	51	0	0
T53	0	286	0	0
T54	0	28	0	0
T66	0	271	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	993	0	0
T114	0	237	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	7214	0	0
T1	9484	22	0	0
T4	7201	36	0	0
T5	409	0	0	0
T13	527	6	0	0
T14	729	3	0	0
T15	502	6	0	0
T16	405	0	0	0
T17	436	3	0	0
T18	435	4	0	0
T19	633	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	57535	0	0
T7	295293	63	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T29	0	98	0	0
T36	0	304	0	0
T50	1121	0	0	0
T51	0	643	0	0
T52	0	25	0	0
T53	0	91	0	0
T54	0	49	0	0
T66	0	170	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T113	0	201	0	0
T114	0	49945	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T23,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T23
1	0	Covered	T1,T5,T13
1	1	Covered	T4,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T51
0	1	Covered	T7,T23,T29
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T51
0	1	Unreachable
1	0	Covered	T7,T23,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T23
DetectSt	168	Covered	T7,T23,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T23,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T23,T29
DebounceSt->IdleSt	163	Covered	T4,T7,T36
DetectSt->IdleSt	186	Covered	T7,T23,T29
DetectSt->StableSt	191	Covered	T7,T23,T51
IdleSt->DebounceSt	148	Covered	T4,T7,T23
StableSt->IdleSt	206	Covered	T7,T23,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T23
0	1	Covered	T4,T7,T23
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T23,T29
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T23,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T36,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T23
DetectSt	-	-	-	-	1	-	-	Covered	T7,T23,T29
DetectSt	-	-	-	-	0	1	-	Covered	T7,T23,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T23,T51
StableSt	-	-	-	-	-	-	0	Covered	T7,T23,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	196	0	0
CntIncr_A	6439628	8262	0	0
CntNoWrap_A	6439628	5753332	0	0
DetectStDropOut_A	6439628	13	0	0
DetectedOut_A	6439628	7836	0	0
DetectedPulseOut_A	6439628	50	0	0
DisabledIdleSt_A	6439628	5345620	0	0
DisabledNoDetection_A	6439628	5348106	0	0
EnterDebounceSt_A	6439628	135	0	0
EnterDetectSt_A	6439628	63	0	0
EnterStableSt_A	6439628	50	0	0
PulseIsPulse_A	6439628	50	0	0
StayInStableSt	6439628	7786	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_sticky_sva.StableStDropOut_A	6439628	334597	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	196	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	7	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	4	0	0
T29	0	2	0	0
T36	0	3	0	0
T48	506	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	6	0	0
T54	0	2	0	0
T66	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	8262	0	0
T4	7201	73	0	0
T5	409	0	0	0
T7	0	230	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	122	0	0
T29	0	92	0	0
T36	0	255	0	0
T48	506	0	0	0
T51	0	77	0	0
T52	0	19	0	0
T53	0	151	0	0
T54	0	79	0	0
T66	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753332	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	13	0	0
T7	295293	2	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T50	1121	0	0	0
T53	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T119	0	1	0	0
T122	0	3	0	0
T123	0	2	0	0
T124	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	7836	0	0
T7	295293	88	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T50	1121	0	0	0
T51	0	504	0	0
T52	0	18	0	0
T53	0	128	0	0
T54	0	42	0	0
T66	0	498	0	0
T73	0	140	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	14	0	0
T113	0	429	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	50	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T66	0	2	0	0
T73	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5345620	0	0
T1	9484	5420	0	0
T4	7201	6720	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5348106	0	0
T1	9484	5431	0	0
T4	7201	6720	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	135	0	0
T4	7201	2	0	0
T5	409	0	0	0
T7	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	2	0	0
T29	0	1	0	0
T36	0	3	0	0
T48	506	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T66	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	63	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	2	0	0
T29	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T66	0	2	0	0
T73	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	50	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T66	0	2	0	0
T73	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	50	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T50	1121	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T66	0	2	0	0
T73	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	7786	0	0
T7	295293	87	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T50	1121	0	0	0
T51	0	503	0	0
T52	0	17	0	0
T53	0	127	0	0
T54	0	41	0	0
T66	0	496	0	0
T73	0	139	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	13	0	0
T113	0	426	0	0
T115	0	171	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	334597	0	0
T7	295293	114	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	102	0	0
T50	1121	0	0	0
T51	0	355	0	0
T52	0	128	0	0
T53	0	84	0	0
T54	0	27	0	0
T66	0	258	0	0
T73	0	263	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	118	0	0
T113	0	860	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T23,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T23
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T29
0	1	Covered	T53,T54,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T29
0	1	Unreachable
1	0	Covered	T7,T23,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T23
DetectSt	168	Covered	T7,T23,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T23,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T23,T29
DebounceSt->IdleSt	163	Covered	T4,T7,T51
DetectSt->IdleSt	186	Covered	T53,T54,T72
DetectSt->StableSt	191	Covered	T7,T23,T29
IdleSt->DebounceSt	148	Covered	T4,T7,T23
StableSt->IdleSt	206	Covered	T7,T23,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T23
0	1	Covered	T4,T7,T23
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T23,T29
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T23,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T51,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T23
DetectSt	-	-	-	-	1	-	-	Covered	T53,T54,T72
DetectSt	-	-	-	-	0	1	-	Covered	T7,T23,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T23,T29
StableSt	-	-	-	-	-	-	0	Covered	T7,T23,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	194	0	0
CntIncr_A	6439628	304409	0	0
CntNoWrap_A	6439628	5753334	0	0
DetectStDropOut_A	6439628	17	0	0
DetectedOut_A	6439628	49218	0	0
DetectedPulseOut_A	6439628	43	0	0
DisabledIdleSt_A	6439628	5345620	0	0
DisabledNoDetection_A	6439628	5348106	0	0
EnterDebounceSt_A	6439628	136	0	0
EnterDetectSt_A	6439628	60	0	0
EnterStableSt_A	6439628	43	0	0
PulseIsPulse_A	6439628	43	0	0
StayInStableSt	6439628	49175	0	0
gen_high_event_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_sticky_sva.StableStDropOut_A	6439628	7580	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	194	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	2	0	0
T29	0	2	0	0
T36	0	3	0	0
T48	506	0	0	0
T51	0	5	0	0
T52	0	2	0	0
T53	0	6	0	0
T54	0	2	0	0
T66	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	304409	0	0
T4	7201	75	0	0
T5	409	0	0	0
T7	0	55	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	60	0	0
T29	0	92	0	0
T36	0	282	0	0
T48	506	0	0	0
T51	0	355	0	0
T52	0	52	0	0
T53	0	236	0	0
T54	0	58	0	0
T66	0	147	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753334	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	17	0	0
T53	29692	2	0	0
T54	594	1	0	0
T66	1818	0	0	0
T72	0	1	0	0
T77	35348	0	0	0
T117	0	1	0	0
T118	0	2	0	0
T124	0	4	0	0
T125	0	1	0	0
T126	0	2	0	0
T127	0	3	0	0
T128	452	0	0	0
T129	423	0	0	0
T130	417	0	0	0
T131	493	0	0	0
T132	507	0	0	0
T133	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	49218	0	0
T7	295293	88	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	175	0	0
T29	0	86	0	0
T50	1121	0	0	0
T52	0	39	0	0
T53	0	154	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	83	0	0
T113	0	330	0	0
T114	0	40720	0	0
T115	0	440	0	0
T116	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	43	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T50	1121	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0
T114	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5345620	0	0
T1	9484	5420	0	0
T4	7201	6720	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5348106	0	0
T1	9484	5431	0	0
T4	7201	6720	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	136	0	0
T4	7201	2	0	0
T5	409	0	0	0
T7	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T36	0	3	0	0
T48	506	0	0	0
T51	0	5	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T66	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	60	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T50	1121	0	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0
T114	0	2	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	43	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T50	1121	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0
T114	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	43	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T50	1121	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	1	0	0
T113	0	3	0	0
T114	0	2	0	0
T115	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	49175	0	0
T7	295293	87	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	174	0	0
T29	0	85	0	0
T50	1121	0	0	0
T52	0	38	0	0
T53	0	153	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	82	0	0
T113	0	327	0	0
T114	0	40718	0	0
T115	0	439	0	0
T116	0	1	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	7580	0	0
T7	295293	336	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T23	0	83	0	0
T29	0	24	0	0
T50	1121	0	0	0
T52	0	93	0	0
T53	0	32	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T112	0	31	0	0
T113	0	992	0	0
T114	0	211	0	0
T115	0	36	0	0
T116	0	109	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T12
0	1	Covered	T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T12
0	1	Covered	T6,T12,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T12
1	-	Covered	T6,T12,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T6,T7
DetectSt	168	Covered	T6,T7,T12
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T12
DebounceSt->IdleSt	163	Covered	T4,T33,T134
DetectSt->IdleSt	186	Covered	T92
DetectSt->StableSt	191	Covered	T6,T7,T12
IdleSt->DebounceSt	148	Covered	T4,T6,T7
StableSt->IdleSt	206	Covered	T6,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T92
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T12,T31
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	102	0	0
CntIncr_A	6439628	23702	0	0
CntNoWrap_A	6439628	5753426	0	0
DetectStDropOut_A	6439628	1	0	0
DetectedOut_A	6439628	22345	0	0
DetectedPulseOut_A	6439628	48	0	0
DisabledIdleSt_A	6439628	5620989	0	0
DisabledNoDetection_A	6439628	5623410	0	0
EnterDebounceSt_A	6439628	53	0	0
EnterDetectSt_A	6439628	49	0	0
EnterStableSt_A	6439628	48	0	0
PulseIsPulse_A	6439628	48	0	0
StayInStableSt	6439628	22271	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	102	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	2	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T33	0	3	0	0
T35	0	2	0	0
T36	0	2	0	0
T48	506	0	0	0
T68	0	2	0	0
T134	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	23702	0	0
T4	7201	30	0	0
T5	409	0	0	0
T6	0	94	0	0
T7	0	94	0	0
T12	0	73	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	62	0	0
T33	0	102	0	0
T35	0	23	0	0
T36	0	34	0	0
T48	506	0	0	0
T68	0	93	0	0
T134	0	164	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753426	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1	0	0
T92	16711	1	0	0
T135	652	0	0	0
T136	5219	0	0	0
T137	21472	0	0	0
T138	434	0	0	0
T139	1096	0	0	0
T140	615	0	0	0
T141	502	0	0	0
T142	19865	0	0	0
T143	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	22345	0	0
T6	14520	40	0	0
T7	295293	194	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	139	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	215	0	0
T33	0	54	0	0
T35	0	13	0	0
T36	0	42	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T68	0	41	0	0
T134	0	50	0	0
T144	0	503	0	0
T145	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	48	0	0
T6	14520	1	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T68	0	1	0	0
T134	0	1	0	0
T144	0	4	0	0
T145	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5620989	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5623410	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	53	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T48	506	0	0	0
T68	0	1	0	0
T134	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	49	0	0
T6	14520	1	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T68	0	1	0	0
T134	0	1	0	0
T144	0	4	0	0
T145	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	48	0	0
T6	14520	1	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T68	0	1	0	0
T134	0	1	0	0
T144	0	4	0	0
T145	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	48	0	0
T6	14520	1	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T68	0	1	0	0
T134	0	1	0	0
T144	0	4	0	0
T145	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	22271	0	0
T6	14520	39	0	0
T7	295293	192	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	138	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	214	0	0
T33	0	52	0	0
T35	0	12	0	0
T36	0	40	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T68	0	39	0	0
T134	0	49	0	0
T144	0	497	0	0
T145	426	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	22	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T69	0	1	0	0
T123	0	1	0	0
T134	0	1	0	0
T144	0	2	0	0
T145	426	0	0	0
T146	0	1	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T31,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T31,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T31,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T31,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T37,T38
0	1	Covered	T68,T124
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T37,T38
0	1	Covered	T31,T38,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T37,T38
1	-	Covered	T31,T38,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T31,T36
DetectSt	168	Covered	T31,T37,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T31,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T37,T38
DebounceSt->IdleSt	163	Covered	T4,T36,T148
DetectSt->IdleSt	186	Covered	T68,T124
DetectSt->StableSt	191	Covered	T31,T37,T38
IdleSt->DebounceSt	148	Covered	T4,T31,T36
StableSt->IdleSt	206	Covered	T31,T38,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T31,T36
0	1	Covered	T4,T31,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T31,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T148,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T31,T36
DetectSt	-	-	-	-	1	-	-	Covered	T68,T124
DetectSt	-	-	-	-	0	1	-	Covered	T31,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T38,T33
StableSt	-	-	-	-	-	-	0	Covered	T31,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	135	0	0
CntIncr_A	6439628	46864	0	0
CntNoWrap_A	6439628	5753393	0	0
DetectStDropOut_A	6439628	2	0	0
DetectedOut_A	6439628	25883	0	0
DetectedPulseOut_A	6439628	62	0	0
DisabledIdleSt_A	6439628	5623179	0	0
DisabledNoDetection_A	6439628	5625612	0	0
EnterDebounceSt_A	6439628	71	0	0
EnterDetectSt_A	6439628	64	0	0
EnterStableSt_A	6439628	62	0	0
PulseIsPulse_A	6439628	62	0	0
StayInStableSt	6439628	25795	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	2830	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	135	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	4	0	0
T33	0	4	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T48	506	0	0	0
T68	0	2	0	0
T134	0	8	0	0
T150	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	46864	0	0
T4	7201	30	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	68	0	0
T33	0	102	0	0
T36	0	34	0	0
T37	0	65	0	0
T38	0	23	0	0
T48	506	0	0	0
T68	0	93	0	0
T134	0	328	0	0
T150	0	50	0	0
T151	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753393	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2	0	0
T68	637	1	0	0
T124	0	1	0	0
T152	407	0	0	0
T153	503	0	0	0
T154	4411	0	0	0
T155	679	0	0	0
T156	881	0	0	0
T157	422	0	0	0
T158	499	0	0	0
T159	520	0	0	0
T160	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	25883	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	113	0	0
T33	0	203	0	0
T37	0	72	0	0
T38	0	40	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	680	0	0
T146	0	23	0	0
T150	0	37	0	0
T151	0	19	0	0
T161	0	12	0	0
T162	0	544	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	62	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	2	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	4	0	0
T146	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5623179	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5625612	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	71	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T48	506	0	0	0
T68	0	1	0	0
T134	0	4	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	64	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	2	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T68	0	1	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	4	0	0
T146	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	62	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	2	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	4	0	0
T146	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	62	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	2	0	0
T33	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	4	0	0
T146	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	25795	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	110	0	0
T33	0	201	0	0
T37	0	70	0	0
T38	0	39	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	674	0	0
T146	0	21	0	0
T150	0	35	0	0
T151	0	18	0	0
T161	0	11	0	0
T162	0	542	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2830	0	0
T1	9484	12	0	0
T4	7201	3	0	0
T5	409	1	0	0
T13	527	4	0	0
T14	729	0	0	0
T15	502	5	0	0
T16	405	0	0	0
T17	436	2	0	0
T18	435	5	0	0
T19	633	0	0	0
T48	0	6	0	0
T59	0	4	0	0
T110	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	36	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	1	0	0
T33	0	2	0	0
T38	0	1	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	2	0	0
T146	0	2	0	0
T147	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0