Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T9,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T9,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T32,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T9,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T32,T38
0	1	Covered	T162,T165
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T32,T38
0	1	Covered	T32,T38,T166
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T32,T38
1	-	Covered	T32,T38,T166

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T32
DetectSt	168	Covered	T9,T32,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T32,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T32,T38
DebounceSt->IdleSt	163	Covered	T4,T117,T67
DetectSt->IdleSt	186	Covered	T162,T165
DetectSt->StableSt	191	Covered	T9,T32,T38
IdleSt->DebounceSt	148	Covered	T4,T9,T32
StableSt->IdleSt	206	Covered	T9,T32,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T32
0	1	Covered	T4,T9,T32
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T32,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T32,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T168,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T32
DetectSt	-	-	-	-	1	-	-	Covered	T162,T165
DetectSt	-	-	-	-	0	1	-	Covered	T9,T32,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T38,T166
StableSt	-	-	-	-	-	-	0	Covered	T9,T32,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	90	0	0
CntIncr_A	6439628	2570	0	0
CntNoWrap_A	6439628	5753438	0	0
DetectStDropOut_A	6439628	2	0	0
DetectedOut_A	6439628	3310	0	0
DetectedPulseOut_A	6439628	40	0	0
DisabledIdleSt_A	6439628	5724371	0	0
DisabledNoDetection_A	6439628	5726798	0	0
EnterDebounceSt_A	6439628	49	0	0
EnterDetectSt_A	6439628	42	0	0
EnterStableSt_A	6439628	40	0	0
PulseIsPulse_A	6439628	40	0	0
StayInStableSt	6439628	3249	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	90	0	0
T4	7201	1	0	0
T5	409	0	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	2	0	0
T48	506	0	0	0
T151	0	4	0	0
T161	0	2	0	0
T162	0	2	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2570	0	0
T4	7201	30	0	0
T5	409	0	0	0
T9	0	51	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	94	0	0
T33	0	51	0	0
T35	0	23	0	0
T38	0	23	0	0
T48	506	0	0	0
T151	0	170	0	0
T161	0	54	0	0
T162	0	88	0	0
T166	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753438	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2	0	0
T162	1201	1	0	0
T165	0	1	0	0
T170	2915	0	0	0
T171	4402	0	0	0
T172	23917	0	0	0
T173	592	0	0	0
T174	449	0	0	0
T175	493	0	0	0
T176	709	0	0	0
T177	1932	0	0	0
T178	32927	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3310	0	0
T9	2888	37	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	1082	0	0	0
T32	0	78	0	0
T33	0	54	0	0
T35	0	77	0	0
T38	0	67	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T147	0	41	0	0
T151	0	193	0	0
T161	0	43	0	0
T166	0	137	0	0
T179	0	40	0	0
T180	91079	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	1082	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T147	0	1	0	0
T151	0	2	0	0
T161	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	91079	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5724371	0	0
T1	9484	5420	0	0
T4	7201	6767	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5726798	0	0
T1	9484	5431	0	0
T4	7201	6768	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	49	0	0
T4	7201	1	0	0
T5	409	0	0	0
T9	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T48	506	0	0	0
T151	0	2	0	0
T161	0	1	0	0
T162	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	1082	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T151	0	2	0	0
T161	0	1	0	0
T162	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	91079	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	1082	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T147	0	1	0	0
T151	0	2	0	0
T161	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	91079	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	1082	0	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T147	0	1	0	0
T151	0	2	0	0
T161	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	91079	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3249	0	0
T9	2888	35	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	1082	0	0	0
T32	0	75	0	0
T33	0	52	0	0
T35	0	75	0	0
T38	0	66	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T147	0	39	0	0
T151	0	190	0	0
T161	0	41	0	0
T166	0	136	0	0
T179	0	38	0	0
T180	91079	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	19	0	0
T32	34203	1	0	0
T38	2886	1	0	0
T124	0	1	0	0
T148	0	1	0	0
T151	0	1	0	0
T166	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0
T185	499	0	0	0
T186	703	0	0	0
T187	540	0	0	0
T188	407	0	0	0
T189	635	0	0	0
T190	404	0	0	0
T191	536	0	0	0
T192	495	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T12,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T36
0	1	Covered	T69,T117,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T36
0	1	Covered	T7,T12,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T12,T36
1	-	Covered	T7,T12,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T12
DetectSt	168	Covered	T7,T12,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T12,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T36
DebounceSt->IdleSt	163	Covered	T4,T69,T194
DetectSt->IdleSt	186	Covered	T69,T117,T193
DetectSt->StableSt	191	Covered	T7,T12,T36
IdleSt->DebounceSt	148	Covered	T4,T7,T12
StableSt->IdleSt	206	Covered	T7,T12,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T12
0	1	Covered	T4,T7,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T149,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T69,T117,T193
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T36
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	170	0	0
CntIncr_A	6439628	5223	0	0
CntNoWrap_A	6439628	5753358	0	0
DetectStDropOut_A	6439628	3	0	0
DetectedOut_A	6439628	6327	0	0
DetectedPulseOut_A	6439628	79	0	0
DisabledIdleSt_A	6439628	5726259	0	0
DisabledNoDetection_A	6439628	5728682	0	0
EnterDebounceSt_A	6439628	89	0	0
EnterDetectSt_A	6439628	82	0	0
EnterStableSt_A	6439628	79	0	0
PulseIsPulse_A	6439628	79	0	0
StayInStableSt	6439628	6213	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	3124	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	170	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	4	0	0
T12	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	4	0	0
T35	0	2	0	0
T36	0	4	0	0
T38	0	4	0	0
T48	506	0	0	0
T134	0	2	0	0
T150	0	2	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5223	0	0
T4	7201	30	0	0
T5	409	0	0	0
T7	0	142	0	0
T12	0	146	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	94	0	0
T35	0	23	0	0
T36	0	162	0	0
T38	0	46	0	0
T48	506	0	0	0
T134	0	92	0	0
T150	0	50	0	0
T196	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753358	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3	0	0
T69	996	1	0	0
T117	0	1	0	0
T193	0	1	0	0
T197	735	0	0	0
T198	580	0	0	0
T199	6964	0	0	0
T200	497	0	0	0
T201	551	0	0	0
T202	442	0	0	0
T203	823	0	0	0
T204	402	0	0	0
T205	498	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6327	0	0
T7	295293	103	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	290	0	0
T32	0	181	0	0
T35	0	43	0	0
T36	0	102	0	0
T38	0	138	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	55	0	0
T144	0	348	0	0
T150	0	42	0	0
T196	0	71	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T7	295293	2	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	1	0	0
T144	0	2	0	0
T150	0	1	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5726259	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5728682	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	89	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	2	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T48	506	0	0	0
T134	0	1	0	0
T150	0	1	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	82	0	0
T7	295293	2	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	1	0	0
T144	0	2	0	0
T150	0	1	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T7	295293	2	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	1	0	0
T144	0	2	0	0
T150	0	1	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T7	295293	2	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	2	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	1	0	0
T144	0	2	0	0
T150	0	1	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6213	0	0
T7	295293	100	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	287	0	0
T32	0	179	0	0
T35	0	42	0	0
T36	0	99	0	0
T38	0	135	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	53	0	0
T144	0	346	0	0
T150	0	41	0	0
T196	0	70	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3124	0	0
T1	9484	13	0	0
T4	7201	7	0	0
T5	409	2	0	0
T13	527	6	0	0
T14	729	0	0	0
T15	502	4	0	0
T16	405	0	0	0
T17	436	2	0	0
T18	435	3	0	0
T19	633	3	0	0
T48	0	8	0	0
T59	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	44	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	1	0	0
T32	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	2	0	0
T150	0	1	0	0
T166	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T12
0	1	Covered	T2,T31,T36
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T12
0	1	Covered	T7,T9,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T12
1	-	Covered	T7,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T7
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T4,T7,T36
DetectSt->IdleSt	186	Covered	T2,T31,T36
DetectSt->StableSt	191	Covered	T7,T9,T12
IdleSt->DebounceSt	148	Covered	T4,T2,T7
StableSt->IdleSt	206	Covered	T7,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T7
0	1	Covered	T4,T2,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T36,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T31,T36
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	164	0	0
CntIncr_A	6439628	25383	0	0
CntNoWrap_A	6439628	5753364	0	0
DetectStDropOut_A	6439628	5	0	0
DetectedOut_A	6439628	65588	0	0
DetectedPulseOut_A	6439628	73	0	0
DisabledIdleSt_A	6439628	5631355	0	0
DisabledNoDetection_A	6439628	5633784	0	0
EnterDebounceSt_A	6439628	86	0	0
EnterDetectSt_A	6439628	78	0	0
EnterStableSt_A	6439628	73	0	0
PulseIsPulse_A	6439628	73	0	0
StayInStableSt	6439628	65480	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	164	0	0
T2	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	7	0	0
T9	0	2	0	0
T12	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	4	0	0
T32	0	2	0	0
T36	0	5	0	0
T38	0	2	0	0
T48	506	0	0	0
T68	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	25383	0	0
T2	0	90	0	0
T4	7201	31	0	0
T5	409	0	0	0
T7	0	359	0	0
T9	0	51	0	0
T12	0	146	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	96	0	0
T32	0	47	0	0
T36	0	196	0	0
T38	0	23	0	0
T48	506	0	0	0
T68	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753364	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T31	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T72	0	1	0	0
T110	420	0	0	0
T206	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65588	0	0
T7	295293	120	0	0
T8	24750	0	0	0
T9	2888	38	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	172	0	0
T31	0	200	0	0
T32	0	38	0	0
T35	0	78	0	0
T36	0	41	0	0
T50	1121	0	0	0
T68	0	41	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	399	0	0
T144	0	458	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	73	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T68	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	3	0	0
T144	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5631355	0	0
T1	9484	5420	0	0
T4	7201	6767	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5633784	0	0
T1	9484	5431	0	0
T4	7201	6768	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	86	0	0
T2	0	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	4	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T36	0	3	0	0
T38	0	1	0	0
T48	506	0	0	0
T68	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	78	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	3	0	0
T9	0	1	0	0
T12	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T68	0	1	0	0
T110	420	0	0	0
T134	0	3	0	0
T206	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	73	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T68	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	3	0	0
T144	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	73	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T50	1121	0	0	0
T68	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	3	0	0
T144	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65480	0	0
T7	295293	115	0	0
T8	24750	0	0	0
T9	2888	37	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	169	0	0
T31	0	199	0	0
T32	0	36	0	0
T35	0	76	0	0
T36	0	39	0	0
T50	1121	0	0	0
T68	0	39	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	395	0	0
T144	0	455	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	38	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T12	0	1	0	0
T31	0	1	0	0
T50	1121	0	0	0
T69	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	2	0	0
T144	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T13
1	1	Covered	T4,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T207
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T7,T33,T166
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T7,T33,T166

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T7
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T4,T144,T208
DetectSt->IdleSt	186	Covered	T207
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T4,T2,T7
StableSt->IdleSt	206	Covered	T7,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T7
0	1	Covered	T4,T2,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T208,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T207
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T33,T166
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	82	0	0
CntIncr_A	6439628	4171	0	0
CntNoWrap_A	6439628	5753446	0	0
DetectStDropOut_A	6439628	1	0	0
DetectedOut_A	6439628	4572	0	0
DetectedPulseOut_A	6439628	37	0	0
DisabledIdleSt_A	6439628	5716439	0	0
DisabledNoDetection_A	6439628	5718866	0	0
EnterDebounceSt_A	6439628	44	0	0
EnterDetectSt_A	6439628	38	0	0
EnterStableSt_A	6439628	37	0	0
PulseIsPulse_A	6439628	37	0	0
StayInStableSt	6439628	4517	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	6926	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	82	0	0
T2	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T36	0	2	0	0
T48	506	0	0	0
T144	0	1	0	0
T150	0	2	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	4171	0	0
T2	0	90	0	0
T4	7201	29	0	0
T5	409	0	0	0
T7	0	71	0	0
T9	0	51	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T33	0	102	0	0
T34	0	66	0	0
T36	0	48	0	0
T48	506	0	0	0
T144	0	84	0	0
T150	0	50	0	0
T166	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753446	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1	0	0
T67	6307	0	0	0
T207	839	1	0	0
T209	52081	0	0	0
T210	491	0	0	0
T211	2394	0	0	0
T212	503	0	0	0
T213	402	0	0	0
T214	1365	0	0	0
T215	25429	0	0	0
T216	5468	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	4572	0	0
T2	631	40	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	42	0	0
T9	0	38	0	0
T33	0	97	0	0
T34	0	41	0	0
T36	0	43	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T150	0	38	0	0
T151	0	43	0	0
T161	0	111	0	0
T166	0	2	0	0
T206	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	37	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0
T206	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5716439	0	0
T1	9484	5420	0	0
T4	7201	6769	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5718866	0	0
T1	9484	5431	0	0
T4	7201	6770	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	44	0	0
T2	0	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T48	506	0	0	0
T144	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	38	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0
T206	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	37	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0
T206	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	37	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0
T206	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	4517	0	0
T2	631	38	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	41	0	0
T9	0	36	0	0
T33	0	94	0	0
T34	0	39	0	0
T36	0	41	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T150	0	36	0	0
T151	0	42	0	0
T161	0	109	0	0
T166	0	1	0	0
T206	405	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6926	0	0
T1	9484	22	0	0
T2	0	1	0	0
T3	0	24	0	0
T4	7201	24	0	0
T5	409	0	0	0
T13	527	4	0	0
T14	729	0	0	0
T15	502	5	0	0
T16	405	0	0	0
T17	436	3	0	0
T18	435	4	0	0
T19	633	0	0	0
T48	0	5	0	0
T59	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	19	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T33	0	1	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T99	0	1	0	0
T117	0	1	0	0
T148	0	1	0	0
T151	0	1	0	0
T166	0	1	0	0
T194	0	1	0	0
T208	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T9,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T36
0	1	Covered	T127,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T36
0	1	Covered	T7,T9,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T36
1	-	Covered	T7,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T9
DetectSt	168	Covered	T7,T9,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T36
DebounceSt->IdleSt	163	Covered	T4,T70,T218
DetectSt->IdleSt	186	Covered	T127,T92
DetectSt->StableSt	191	Covered	T7,T9,T36
IdleSt->DebounceSt	148	Covered	T4,T7,T9
StableSt->IdleSt	206	Covered	T7,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T9
0	1	Covered	T4,T7,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T70,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T127,T92
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	129	0	0
CntIncr_A	6439628	3759	0	0
CntNoWrap_A	6439628	5753399	0	0
DetectStDropOut_A	6439628	2	0	0
DetectedOut_A	6439628	5512	0	0
DetectedPulseOut_A	6439628	58	0	0
DisabledIdleSt_A	6439628	5735392	0	0
DisabledNoDetection_A	6439628	5737830	0	0
EnterDebounceSt_A	6439628	69	0	0
EnterDetectSt_A	6439628	60	0	0
EnterStableSt_A	6439628	58	0	0
PulseIsPulse_A	6439628	58	0	0
StayInStableSt	6439628	5431	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	129	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	6	0	0
T9	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	4	0	0
T48	506	0	0	0
T150	0	2	0	0
T166	0	4	0	0
T196	0	6	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3759	0	0
T4	7201	30	0	0
T5	409	0	0	0
T7	0	219	0	0
T9	0	102	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T34	0	66	0	0
T35	0	46	0	0
T36	0	129	0	0
T48	506	0	0	0
T150	0	50	0	0
T166	0	24	0	0
T196	0	66	0	0
T201	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753399	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2	0	0
T92	0	1	0	0
T127	21437	1	0	0
T220	505	0	0	0
T221	7986	0	0	0
T222	748	0	0	0
T223	493	0	0	0
T224	423	0	0	0
T225	450	0	0	0
T226	421	0	0	0
T227	501	0	0	0
T228	1416	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5512	0	0
T7	295293	262	0	0
T8	24750	0	0	0
T9	2888	81	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T34	0	53	0	0
T35	0	125	0	0
T36	0	368	0	0
T50	1121	0	0	0
T70	0	53	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T150	0	38	0	0
T166	0	15	0	0
T196	0	123	0	0
T201	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	58	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	2	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T50	1121	0	0	0
T70	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T150	0	1	0	0
T166	0	2	0	0
T196	0	3	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5735392	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5737830	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	69	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	3	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T48	506	0	0	0
T150	0	1	0	0
T166	0	2	0	0
T196	0	3	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	60	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	2	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T50	1121	0	0	0
T70	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T150	0	1	0	0
T166	0	2	0	0
T196	0	3	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	58	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	2	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T50	1121	0	0	0
T70	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T150	0	1	0	0
T166	0	2	0	0
T196	0	3	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	58	0	0
T7	295293	3	0	0
T8	24750	0	0	0
T9	2888	2	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0
T50	1121	0	0	0
T70	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T150	0	1	0	0
T166	0	2	0	0
T196	0	3	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5431	0	0
T7	295293	257	0	0
T8	24750	0	0	0
T9	2888	78	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T34	0	51	0	0
T35	0	122	0	0
T36	0	366	0	0
T50	1121	0	0	0
T70	0	50	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T150	0	36	0	0
T166	0	13	0	0
T196	0	119	0	0
T201	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	35	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T50	1121	0	0	0
T70	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T147	0	2	0	0
T162	0	1	0	0
T166	0	2	0	0
T196	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T6,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T6,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T12,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T1,T4,T13
1	1	Covered	T4,T6,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T31
0	1	Covered	T229
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T31
0	1	Covered	T31,T38,T134
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T31
1	-	Covered	T31,T38,T134

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T6,T12
DetectSt	168	Covered	T6,T12,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T12,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T12,T31
DebounceSt->IdleSt	163	Covered	T4,T134,T196
DetectSt->IdleSt	186	Covered	T229
DetectSt->StableSt	191	Covered	T6,T12,T31
IdleSt->DebounceSt	148	Covered	T4,T6,T12
StableSt->IdleSt	206	Covered	T6,T31,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T6,T12
0	1	Covered	T4,T6,T12
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T6,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T12,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T6,T12
DetectSt	-	-	-	-	1	-	-	Covered	T229
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T38,T134
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	96	0	0
CntIncr_A	6439628	23261	0	0
CntNoWrap_A	6439628	5753432	0	0
DetectStDropOut_A	6439628	1	0	0
DetectedOut_A	6439628	42489	0	0
DetectedPulseOut_A	6439628	45	0	0
DisabledIdleSt_A	6439628	5632609	0	0
DisabledNoDetection_A	6439628	5635043	0	0
EnterDebounceSt_A	6439628	50	0	0
EnterDetectSt_A	6439628	46	0	0
EnterStableSt_A	6439628	45	0	0
PulseIsPulse_A	6439628	45	0	0
StayInStableSt	6439628	42423	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	6448	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	96	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T38	0	4	0	0
T48	506	0	0	0
T70	0	4	0	0
T134	0	5	0	0
T144	0	6	0	0
T161	0	2	0	0
T196	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	23261	0	0
T4	7201	29	0	0
T5	409	0	0	0
T6	0	94	0	0
T12	0	73	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	62	0	0
T38	0	46	0	0
T48	506	0	0	0
T70	0	172	0	0
T134	0	220	0	0
T144	0	235	0	0
T161	0	54	0	0
T196	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753432	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1	0	0
T229	10550	1	0	0
T230	406	0	0	0
T231	422	0	0	0
T232	5316	0	0	0
T233	679	0	0	0
T234	402	0	0	0
T235	10351	0	0	0
T236	506	0	0	0
T237	450	0	0	0
T238	431	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42489	0	0
T6	14520	40	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	359	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	214	0	0
T38	0	79	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T70	0	170	0	0
T134	0	134	0	0
T144	0	528	0	0
T145	426	0	0	0
T161	0	44	0	0
T162	0	545	0	0
T196	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	45	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T70	0	2	0	0
T134	0	2	0	0
T144	0	3	0	0
T145	426	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5632609	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5635043	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	50	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	1	0	0
T12	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	1	0	0
T38	0	2	0	0
T48	506	0	0	0
T70	0	2	0	0
T134	0	3	0	0
T144	0	3	0	0
T161	0	1	0	0
T196	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	46	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T70	0	2	0	0
T134	0	2	0	0
T144	0	3	0	0
T145	426	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	45	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T70	0	2	0	0
T134	0	2	0	0
T144	0	3	0	0
T145	426	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	45	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	1	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T70	0	2	0	0
T134	0	2	0	0
T144	0	3	0	0
T145	426	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42423	0	0
T6	14520	38	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T12	0	357	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	213	0	0
T38	0	76	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T70	0	168	0	0
T134	0	131	0	0
T144	0	523	0	0
T145	426	0	0	0
T148	0	261	0	0
T161	0	42	0	0
T162	0	543	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6448	0	0
T1	9484	16	0	0
T3	0	35	0	0
T4	7201	37	0	0
T5	409	0	0	0
T13	527	4	0	0
T14	729	0	0	0
T15	502	5	0	0
T16	405	0	0	0
T17	436	2	0	0
T18	435	6	0	0
T19	633	0	0	0
T48	0	4	0	0
T59	0	4	0	0
T110	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	24	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	1	0	0
T38	0	1	0	0
T44	18688	0	0	0
T55	504	0	0	0
T56	496	0	0	0
T70	0	2	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T134	0	1	0	0
T144	0	1	0	0
T183	0	1	0	0
T196	0	1	0	0
T239	0	1	0	0
T240	0	1	0	0
T241	0	1	0	0