Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T36
0	1	Covered	T124,T149,T127
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T36
0	1	Covered	T6,T32,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T36
1	-	Covered	T6,T32,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T6,T7
DetectSt	168	Covered	T6,T7,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T36
DebounceSt->IdleSt	163	Covered	T4,T117,T242
DetectSt->IdleSt	186	Covered	T124,T149,T127
DetectSt->StableSt	191	Covered	T6,T7,T36
IdleSt->DebounceSt	148	Covered	T4,T6,T7
StableSt->IdleSt	206	Covered	T6,T7,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T117,T242,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T124,T149,T127
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T32,T38
StableSt	-	-	-	-	-	-	0	Covered	T6,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	170	0	0
CntIncr_A	6439628	8499	0	0
CntNoWrap_A	6439628	5753358	0	0
DetectStDropOut_A	6439628	3	0	0
DetectedOut_A	6439628	8605	0	0
DetectedPulseOut_A	6439628	79	0	0
DisabledIdleSt_A	6439628	5721104	0	0
DisabledNoDetection_A	6439628	5723532	0	0
EnterDebounceSt_A	6439628	88	0	0
EnterDetectSt_A	6439628	82	0	0
EnterStableSt_A	6439628	79	0	0
PulseIsPulse_A	6439628	79	0	0
StayInStableSt	6439628	8494	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	47	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	170	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	4	0	0
T7	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	6	0	0
T33	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T48	506	0	0	0
T134	0	6	0	0
T196	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	8499	0	0
T4	7201	30	0	0
T5	409	0	0	0
T6	0	188	0	0
T7	0	71	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	141	0	0
T33	0	102	0	0
T36	0	34	0	0
T37	0	65	0	0
T38	0	46	0	0
T48	506	0	0	0
T134	0	200	0	0
T196	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753358	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3	0	0
T124	9755	1	0	0
T127	0	1	0	0
T149	0	1	0	0
T243	23943	0	0	0
T244	522	0	0	0
T245	420	0	0	0
T246	17648	0	0	0
T247	32006	0	0	0
T248	288010	0	0	0
T249	17502	0	0	0
T250	20357	0	0	0
T251	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	8605	0	0
T6	14520	176	0	0
T7	295293	44	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	117	0	0
T33	0	88	0	0
T35	0	14	0	0
T36	0	42	0	0
T37	0	41	0	0
T38	0	85	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	351	0	0
T145	426	0	0	0
T196	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T6	14520	2	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	3	0	0
T145	426	0	0	0
T196	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5721104	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5723532	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	88	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T48	506	0	0	0
T134	0	3	0	0
T196	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	82	0	0
T6	14520	2	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	3	0	0
T145	426	0	0	0
T196	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T6	14520	2	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	3	0	0
T145	426	0	0	0
T196	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T6	14520	2	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	3	0	0
T145	426	0	0	0
T196	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	8494	0	0
T6	14520	173	0	0
T7	295293	42	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	113	0	0
T33	0	86	0	0
T35	0	13	0	0
T36	0	40	0	0
T37	0	39	0	0
T38	0	83	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	346	0	0
T145	426	0	0	0
T196	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	47	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T134	0	1	0	0
T145	426	0	0	0
T151	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T33,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T33,T164,T72
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T33,T164,T72

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T33,T34
DetectSt	168	Covered	T33,T34,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T34,T35
DebounceSt->IdleSt	163	Covered	T4,T229,T207
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T4,T33,T34
StableSt->IdleSt	206	Covered	T33,T35,T164

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T33,T34
0	1	Covered	T4,T33,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T35
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T229,T207,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T33,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T164,T72
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	85	0	0
CntIncr_A	6439628	6299	0	0
CntNoWrap_A	6439628	5753443	0	0
DetectStDropOut_A	6439628	0	0	0
DetectedOut_A	6439628	3210	0	0
DetectedPulseOut_A	6439628	40	0	0
DisabledIdleSt_A	6439628	5725149	0	0
DisabledNoDetection_A	6439628	5727588	0	0
EnterDebounceSt_A	6439628	45	0	0
EnterDetectSt_A	6439628	40	0	0
EnterStableSt_A	6439628	40	0	0
PulseIsPulse_A	6439628	40	0	0
StayInStableSt	6439628	3150	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	6481	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	85	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T48	506	0	0	0
T72	0	4	0	0
T147	0	2	0	0
T148	0	2	0	0
T161	0	2	0	0
T164	0	4	0	0
T252	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6299	0	0
T4	7201	30	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T33	0	102	0	0
T34	0	66	0	0
T35	0	23	0	0
T48	506	0	0	0
T72	0	154	0	0
T147	0	56	0	0
T148	0	62	0	0
T161	0	54	0	0
T164	0	3710	0	0
T252	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753443	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3210	0	0
T33	51166	108	0	0
T34	0	42	0	0
T35	0	40	0	0
T72	0	112	0	0
T114	84209	0	0	0
T117	0	40	0	0
T147	0	42	0	0
T148	0	137	0	0
T161	0	205	0	0
T164	0	85	0	0
T252	0	201	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T33	51166	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T72	0	2	0	0
T114	84209	0	0	0
T117	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T164	0	2	0	0
T252	0	1	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5725149	0	0
T1	9484	5420	0	0
T4	7201	6769	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5727588	0	0
T1	9484	5431	0	0
T4	7201	6770	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	45	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T48	506	0	0	0
T72	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T164	0	2	0	0
T252	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T33	51166	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T72	0	2	0	0
T114	84209	0	0	0
T117	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T164	0	2	0	0
T252	0	1	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T33	51166	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T72	0	2	0	0
T114	84209	0	0	0
T117	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T164	0	2	0	0
T252	0	1	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T33	51166	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T72	0	2	0	0
T114	84209	0	0	0
T117	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T164	0	2	0	0
T252	0	1	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3150	0	0
T33	51166	105	0	0
T34	0	40	0	0
T35	0	38	0	0
T72	0	109	0	0
T114	84209	0	0	0
T117	0	38	0	0
T147	0	40	0	0
T148	0	135	0	0
T161	0	203	0	0
T164	0	82	0	0
T252	0	199	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6481	0	0
T1	9484	22	0	0
T3	0	36	0	0
T4	7201	34	0	0
T5	409	2	0	0
T13	527	6	0	0
T14	729	0	0	0
T15	502	5	0	0
T16	405	0	0	0
T17	436	5	0	0
T18	435	6	0	0
T19	633	0	0	0
T48	0	4	0	0
T59	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	20	0	0
T33	51166	1	0	0
T72	0	1	0	0
T114	84209	0	0	0
T164	0	1	0	0
T207	0	1	0	0
T229	0	2	0	0
T239	0	1	0	0
T241	0	1	0	0
T253	422	0	0	0
T254	195734	0	0	0
T255	607	0	0	0
T256	504	0	0	0
T257	1975	0	0	0
T258	9274	0	0	0
T259	402	0	0	0
T260	405	0	0	0
T261	0	1	0	0
T262	0	1	0	0
T263	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T264,T229,T265
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T7,T9,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T7,T9,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T7
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T4,T33,T208
DetectSt->IdleSt	186	Covered	T264,T229,T265
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T4,T2,T7
StableSt->IdleSt	206	Covered	T7,T9,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T7
0	1	Covered	T4,T2,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T208,T229
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T264,T229,T265
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T31
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	144	0	0
CntIncr_A	6439628	25351	0	0
CntNoWrap_A	6439628	5753384	0	0
DetectStDropOut_A	6439628	4	0	0
DetectedOut_A	6439628	27218	0	0
DetectedPulseOut_A	6439628	65	0	0
DisabledIdleSt_A	6439628	5624881	0	0
DisabledNoDetection_A	6439628	5627313	0	0
EnterDebounceSt_A	6439628	75	0	0
EnterDetectSt_A	6439628	69	0	0
EnterStableSt_A	6439628	65	0	0
PulseIsPulse_A	6439628	65	0	0
StayInStableSt	6439628	27128	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	144	0	0
T2	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	6	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T33	0	3	0	0
T35	0	2	0	0
T36	0	4	0	0
T48	506	0	0	0
T134	0	4	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	25351	0	0
T2	0	90	0	0
T4	7201	29	0	0
T5	409	0	0	0
T7	0	265	0	0
T9	0	51	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	62	0	0
T33	0	102	0	0
T35	0	23	0	0
T36	0	82	0	0
T48	506	0	0	0
T134	0	184	0	0
T196	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753384	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	4	0	0
T85	4816	0	0	0
T165	0	1	0	0
T229	0	1	0	0
T264	727	1	0	0
T265	0	1	0	0
T266	522	0	0	0
T267	2164	0	0	0
T268	838	0	0	0
T269	647	0	0	0
T270	493	0	0	0
T271	424	0	0	0
T272	15678	0	0	0
T273	697	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	27218	0	0
T2	631	40	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	511	0	0
T9	0	183	0	0
T31	0	104	0	0
T33	0	54	0	0
T35	0	18	0	0
T36	0	121	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	238	0	0
T144	0	331	0	0
T196	0	126	0	0
T206	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	3	0	0
T9	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T144	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5624881	0	0
T1	9484	5420	0	0
T4	7201	6769	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5627313	0	0
T1	9484	5431	0	0
T4	7201	6770	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	75	0	0
T2	0	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	3	0	0
T9	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T48	506	0	0	0
T134	0	2	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	69	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	3	0	0
T9	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T144	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	3	0	0
T9	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T144	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	3	0	0
T9	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T144	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	27128	0	0
T2	631	38	0	0
T3	14919	0	0	0
T6	14520	0	0	0
T7	0	506	0	0
T9	0	182	0	0
T31	0	103	0	0
T33	0	52	0	0
T35	0	17	0	0
T36	0	117	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	235	0	0
T144	0	328	0	0
T196	0	125	0	0
T206	405	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	40	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T50	1121	0	0	0
T69	0	1	0	0
T81	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T134	0	1	0	0
T144	0	1	0	0
T151	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T7,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T32
0	1	Covered	T70,T262
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T32
0	1	Covered	T7,T32,T144
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T31,T32
1	-	Covered	T7,T32,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T31
DetectSt	168	Covered	T7,T31,T32
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T31,T32
DebounceSt->IdleSt	163	Covered	T4,T134,T261
DetectSt->IdleSt	186	Covered	T70,T262
DetectSt->StableSt	191	Covered	T7,T31,T32
IdleSt->DebounceSt	148	Covered	T4,T7,T31
StableSt->IdleSt	206	Covered	T7,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T31
0	1	Covered	T4,T7,T31
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T31,T32
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T261,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T31
DetectSt	-	-	-	-	1	-	-	Covered	T70,T262
DetectSt	-	-	-	-	0	1	-	Covered	T7,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T32,T144
StableSt	-	-	-	-	-	-	0	Covered	T7,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	98	0	0
CntIncr_A	6439628	3107	0	0
CntNoWrap_A	6439628	5753430	0	0
DetectStDropOut_A	6439628	3	0	0
DetectedOut_A	6439628	3524	0	0
DetectedPulseOut_A	6439628	42	0	0
DisabledIdleSt_A	6439628	5725925	0	0
DisabledNoDetection_A	6439628	5728354	0	0
EnterDebounceSt_A	6439628	53	0	0
EnterDetectSt_A	6439628	45	0	0
EnterStableSt_A	6439628	42	0	0
PulseIsPulse_A	6439628	42	0	0
StayInStableSt	6439628	3460	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	6459	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	98	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T32	0	6	0	0
T48	506	0	0	0
T69	0	2	0	0
T134	0	1	0	0
T144	0	4	0	0
T146	0	2	0	0
T151	0	2	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3107	0	0
T4	7201	30	0	0
T5	409	0	0	0
T7	0	94	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	62	0	0
T32	0	141	0	0
T48	506	0	0	0
T69	0	78	0	0
T134	0	92	0	0
T144	0	134	0	0
T146	0	76	0	0
T151	0	85	0	0
T196	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753430	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3	0	0
T70	1036	2	0	0
T161	764	0	0	0
T262	0	1	0	0
T274	7102	0	0	0
T275	640	0	0	0
T276	402	0	0	0
T277	489	0	0	0
T278	491	0	0	0
T279	523	0	0	0
T280	522	0	0	0
T281	443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3524	0	0
T7	295293	55	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	280	0	0
T32	0	115	0	0
T50	1121	0	0	0
T69	0	214	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	143	0	0
T146	0	124	0	0
T151	0	523	0	0
T161	0	43	0	0
T196	0	52	0	0
T201	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	1121	0	0	0
T69	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5725925	0	0
T1	9484	5420	0	0
T4	7201	6768	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5728354	0	0
T1	9484	5431	0	0
T4	7201	6769	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	53	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T48	506	0	0	0
T69	0	1	0	0
T134	0	1	0	0
T144	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	45	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	1121	0	0	0
T69	0	1	0	0
T70	0	2	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	1121	0	0	0
T69	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	1121	0	0	0
T69	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	2	0	0
T146	0	1	0	0
T151	0	1	0	0
T161	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3460	0	0
T7	295293	54	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	278	0	0
T32	0	111	0	0
T50	1121	0	0	0
T69	0	212	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T144	0	140	0	0
T146	0	123	0	0
T151	0	521	0	0
T161	0	41	0	0
T196	0	50	0	0
T201	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6459	0	0
T1	9484	21	0	0
T3	0	29	0	0
T4	7201	34	0	0
T5	409	1	0	0
T13	527	6	0	0
T14	729	0	0	0
T15	502	6	0	0
T16	405	0	0	0
T17	436	2	0	0
T18	435	2	0	0
T19	633	0	0	0
T48	0	5	0	0
T59	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	20	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T32	0	2	0	0
T50	1121	0	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T117	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T208	0	1	0	0
T261	0	1	0	0
T282	0	1	0	0
T283	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T6,T284
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T6,T31,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T6,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T6
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T4,T9,T68
DetectSt->IdleSt	186	Covered	T6,T284
DetectSt->StableSt	191	Covered	T2,T6,T7
IdleSt->DebounceSt	148	Covered	T4,T2,T6
StableSt->IdleSt	206	Covered	T6,T7,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T6
0	1	Covered	T4,T2,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T68,T261
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T6,T284
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	154	0	0
CntIncr_A	6439628	45789	0	0
CntNoWrap_A	6439628	5753374	0	0
DetectStDropOut_A	6439628	2	0	0
DetectedOut_A	6439628	6369	0	0
DetectedPulseOut_A	6439628	72	0	0
DisabledIdleSt_A	6439628	5622300	0	0
DisabledNoDetection_A	6439628	5624727	0	0
EnterDebounceSt_A	6439628	80	0	0
EnterDetectSt_A	6439628	74	0	0
EnterStableSt_A	6439628	72	0	0
PulseIsPulse_A	6439628	72	0	0
StayInStableSt	6439628	6267	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	154	0	0
T2	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	4	0	0
T7	0	2	0	0
T9	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T32	0	4	0	0
T33	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T48	506	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	45789	0	0
T2	0	90	0	0
T4	7201	31	0	0
T5	409	0	0	0
T6	0	188	0	0
T7	0	71	0	0
T9	0	51	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	34	0	0
T32	0	94	0	0
T33	0	51	0	0
T36	0	81	0	0
T38	0	23	0	0
T48	506	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753374	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T145	426	0	0	0
T284	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6369	0	0
T2	631	41	0	0
T3	14919	0	0	0
T6	14520	82	0	0
T7	0	235	0	0
T31	0	77	0	0
T32	0	77	0	0
T33	0	54	0	0
T36	0	270	0	0
T38	0	63	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	291	0	0
T196	0	225	0	0
T206	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	72	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	1	0	0
T7	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5622300	0	0
T1	9484	5420	0	0
T4	7201	6767	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5624727	0	0
T1	9484	5431	0	0
T4	7201	6768	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	80	0	0
T2	0	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T48	506	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	74	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	2	0	0
T7	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	72	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	1	0	0
T7	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	72	0	0
T2	631	1	0	0
T3	14919	0	0	0
T6	14520	1	0	0
T7	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	2	0	0
T196	0	1	0	0
T206	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	6267	0	0
T2	631	39	0	0
T3	14919	0	0	0
T6	14520	81	0	0
T7	0	233	0	0
T31	0	76	0	0
T32	0	74	0	0
T33	0	52	0	0
T36	0	268	0	0
T38	0	62	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T59	510	0	0	0
T60	502	0	0	0
T110	420	0	0	0
T134	0	288	0	0
T196	0	223	0	0
T206	405	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	42	0	0
T6	14520	1	0	0
T7	295293	0	0	0
T8	24750	0	0	0
T9	2888	0	0	0
T24	498	0	0	0
T25	502	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T43	40809	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T134	0	1	0	0
T144	0	3	0	0
T145	426	0	0	0
T148	0	1	0	0
T151	0	1	0	0
T162	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T9,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T4,T13
1	1	Covered	T4,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T31
0	1	Covered	T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T31
0	1	Covered	T32,T81,T70
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T31
1	-	Covered	T32,T81,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T9
DetectSt	168	Covered	T7,T9,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T9,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T31
DebounceSt->IdleSt	163	Covered	T4,T261,T67
DetectSt->IdleSt	186	Covered	T193
DetectSt->StableSt	191	Covered	T7,T9,T31
IdleSt->DebounceSt	148	Covered	T4,T7,T9
StableSt->IdleSt	206	Covered	T7,T9,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T9
0	1	Covered	T4,T7,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T261,T193,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T193
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T81,T70
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	79	0	0
CntIncr_A	6439628	4224	0	0
CntNoWrap_A	6439628	5753449	0	0
DetectStDropOut_A	6439628	1	0	0
DetectedOut_A	6439628	3126	0	0
DetectedPulseOut_A	6439628	35	0	0
DisabledIdleSt_A	6439628	5726178	0	0
DisabledNoDetection_A	6439628	5728620	0	0
EnterDebounceSt_A	6439628	43	0	0
EnterDetectSt_A	6439628	36	0	0
EnterStableSt_A	6439628	35	0	0
PulseIsPulse_A	6439628	35	0	0
StayInStableSt	6439628	3069	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6439628	7214	0	0
gen_low_level_sva.LowLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	2	0	0
T32	0	2	0	0
T38	0	2	0	0
T48	506	0	0	0
T70	0	4	0	0
T81	0	2	0	0
T146	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	4224	0	0
T4	7201	31	0	0
T5	409	0	0	0
T7	0	94	0	0
T9	0	51	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	34	0	0
T32	0	47	0	0
T38	0	23	0	0
T48	506	0	0	0
T70	0	172	0	0
T81	0	81	0	0
T146	0	76	0	0
T201	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5753449	0	0
T1	9484	5420	0	0
T4	7201	6799	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1	0	0
T126	10748	0	0	0
T193	660	1	0	0
T285	522	0	0	0
T286	28455	0	0	0
T287	523	0	0	0
T288	426	0	0	0
T289	446	0	0	0
T290	414	0	0	0
T291	522	0	0	0
T292	15858	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3126	0	0
T7	295293	45	0	0
T8	24750	0	0	0
T9	2888	224	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	202	0	0
T32	0	2	0	0
T38	0	167	0	0
T50	1121	0	0	0
T70	0	269	0	0
T81	0	9	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T146	0	46	0	0
T201	0	45	0	0
T264	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	35	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T70	0	2	0	0
T81	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T146	0	1	0	0
T201	0	1	0	0
T264	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5726178	0	0
T1	9484	5420	0	0
T4	7201	6767	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5728620	0	0
T1	9484	5431	0	0
T4	7201	6768	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	43	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T48	506	0	0	0
T70	0	2	0	0
T81	0	1	0	0
T146	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	36	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T70	0	2	0	0
T81	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T146	0	1	0	0
T201	0	1	0	0
T264	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	35	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T70	0	2	0	0
T81	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T146	0	1	0	0
T201	0	1	0	0
T264	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	35	0	0
T7	295293	1	0	0
T8	24750	0	0	0
T9	2888	1	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T38	0	1	0	0
T50	1121	0	0	0
T70	0	2	0	0
T81	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T146	0	1	0	0
T201	0	1	0	0
T264	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3069	0	0
T7	295293	43	0	0
T8	24750	0	0	0
T9	2888	222	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T31	0	200	0	0
T32	0	1	0	0
T38	0	165	0	0
T50	1121	0	0	0
T70	0	266	0	0
T81	0	8	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0
T146	0	44	0	0
T201	0	43	0	0
T264	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	7214	0	0
T1	9484	22	0	0
T4	7201	36	0	0
T5	409	0	0	0
T13	527	6	0	0
T14	729	3	0	0
T15	502	6	0	0
T16	405	0	0	0
T17	436	3	0	0
T18	435	4	0	0
T19	633	0	0	0
T39	0	3	0	0
T40	0	3	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	13	0	0
T32	34203	1	0	0
T38	2886	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T81	0	1	0	0
T124	0	1	0	0
T185	499	0	0	0
T186	703	0	0	0
T187	540	0	0	0
T188	407	0	0	0
T189	635	0	0	0
T190	404	0	0	0
T191	536	0	0	0
T192	495	0	0	0
T207	0	1	0	0
T208	0	1	0	0
T229	0	1	0	0
T261	0	1	0	0
T264	0	1	0	0