Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T3,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T10
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T10
0	1	Covered	T78,T79,T80
1	0	Covered	T4,T46,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T10
0	1	Covered	T4,T3,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T3,T10
1	-	Covered	T4,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T10
DetectSt	168	Covered	T4,T3,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T3,T10
DebounceSt->IdleSt	163	Covered	T4,T293,T98
DetectSt->IdleSt	186	Covered	T4,T46,T64
DetectSt->StableSt	191	Covered	T4,T3,T10
IdleSt->DebounceSt	148	Covered	T4,T3,T10
StableSt->IdleSt	206	Covered	T4,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T3,T10
0	1	Covered	T4,T3,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T3,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T3,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T293,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T4,T46,T64
DetectSt	-	-	-	-	0	1	-	Covered	T4,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T4,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T3,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	2855	0	0
CntIncr_A	6439628	91986	0	0
CntNoWrap_A	6439628	5750673	0	0
DetectStDropOut_A	6439628	294	0	0
DetectedOut_A	6439628	70136	0	0
DetectedPulseOut_A	6439628	960	0	0
DisabledIdleSt_A	6439628	5309904	0	0
DisabledNoDetection_A	6439628	5312187	0	0
EnterDebounceSt_A	6439628	1436	0	0
EnterDetectSt_A	6439628	1419	0	0
EnterStableSt_A	6439628	960	0	0
PulseIsPulse_A	6439628	960	0	0
StayInStableSt	6439628	69060	0	0
gen_high_event_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	843	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	2855	0	0
T3	0	56	0	0
T4	7201	15	0	0
T5	409	0	0	0
T10	0	26	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	18	0	0
T45	0	2	0	0
T46	0	12	0	0
T47	0	22	0	0
T48	506	0	0	0
T62	0	16	0	0
T63	0	38	0	0
T64	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	91986	0	0
T3	0	2100	0	0
T4	7201	329	0	0
T5	409	0	0	0
T10	0	1079	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	486	0	0
T45	0	21	0	0
T46	0	322	0	0
T47	0	891	0	0
T48	506	0	0	0
T62	0	616	0	0
T63	0	912	0	0
T64	0	821	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5750673	0	0
T1	9484	5420	0	0
T4	7201	6785	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	294	0	0
T35	5620	0	0	0
T78	9722	6	0	0
T79	0	10	0	0
T80	0	4	0	0
T84	0	2	0	0
T85	0	3	0	0
T86	0	11	0	0
T87	0	20	0	0
T89	0	24	0	0
T294	0	21	0	0
T295	0	18	0	0
T296	501	0	0	0
T297	404	0	0	0
T298	17418	0	0	0
T299	23556	0	0	0
T300	20972	0	0	0
T301	494	0	0	0
T302	521	0	0	0
T303	14427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	70136	0	0
T3	0	1651	0	0
T4	7201	403	0	0
T5	409	0	0	0
T10	0	1980	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	1567	0	0
T45	0	32	0	0
T47	0	2042	0	0
T48	506	0	0	0
T62	0	211	0	0
T63	0	420	0	0
T65	0	191	0	0
T304	0	1495	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	960	0	0
T3	0	28	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	13	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	9	0	0
T45	0	1	0	0
T47	0	11	0	0
T48	506	0	0	0
T62	0	8	0	0
T63	0	19	0	0
T65	0	7	0	0
T304	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5309904	0	0
T1	9484	5420	0	0
T4	7201	5981	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5312187	0	0
T1	9484	5431	0	0
T4	7201	5982	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1436	0	0
T3	0	28	0	0
T4	7201	9	0	0
T5	409	0	0	0
T10	0	13	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	9	0	0
T45	0	1	0	0
T46	0	6	0	0
T47	0	11	0	0
T48	506	0	0	0
T62	0	8	0	0
T63	0	19	0	0
T64	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1419	0	0
T3	0	28	0	0
T4	7201	6	0	0
T5	409	0	0	0
T10	0	13	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	9	0	0
T45	0	1	0	0
T46	0	6	0	0
T47	0	11	0	0
T48	506	0	0	0
T62	0	8	0	0
T63	0	19	0	0
T64	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	960	0	0
T3	0	28	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	13	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	9	0	0
T45	0	1	0	0
T47	0	11	0	0
T48	506	0	0	0
T62	0	8	0	0
T63	0	19	0	0
T65	0	7	0	0
T304	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	960	0	0
T3	0	28	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	13	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	9	0	0
T45	0	1	0	0
T47	0	11	0	0
T48	506	0	0	0
T62	0	8	0	0
T63	0	19	0	0
T65	0	7	0	0
T304	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	69060	0	0
T3	0	1620	0	0
T4	7201	398	0	0
T5	409	0	0	0
T10	0	1962	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	1556	0	0
T45	0	30	0	0
T47	0	2022	0	0
T48	506	0	0	0
T62	0	203	0	0
T63	0	401	0	0
T65	0	184	0	0
T304	0	1481	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	843	0	0
T3	0	25	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	8	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	7	0	0
T47	0	2	0	0
T48	506	0	0	0
T62	0	8	0	0
T63	0	19	0	0
T65	0	7	0	0
T304	0	10	0	0
T305	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T4,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T3
0	1	Covered	T7,T8,T44
1	0	Covered	T4,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T3
0	1	Covered	T1,T4,T3
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T3
1	-	Covered	T1,T4,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T3
DetectSt	168	Covered	T1,T4,T3
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T4,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T3
DebounceSt->IdleSt	163	Covered	T4,T6,T7
DetectSt->IdleSt	186	Covered	T4,T7,T8
DetectSt->StableSt	191	Covered	T1,T4,T3
IdleSt->DebounceSt	148	Covered	T1,T4,T3
StableSt->IdleSt	206	Covered	T1,T4,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T3
0	1	Covered	T1,T4,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T7,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T3
DetectSt	-	-	-	-	1	-	-	Covered	T4,T7,T8
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	1055	0	0
CntIncr_A	6439628	50283	0	0
CntNoWrap_A	6439628	5752473	0	0
DetectStDropOut_A	6439628	66	0	0
DetectedOut_A	6439628	16735	0	0
DetectedPulseOut_A	6439628	407	0	0
DisabledIdleSt_A	6439628	5364754	0	0
DisabledNoDetection_A	6439628	5366455	0	0
EnterDebounceSt_A	6439628	578	0	0
EnterDetectSt_A	6439628	477	0	0
EnterStableSt_A	6439628	407	0	0
PulseIsPulse_A	6439628	407	0	0
StayInStableSt	6439628	16275	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	352	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1055	0	0
T1	9484	2	0	0
T3	0	6	0	0
T4	7201	8	0	0
T5	409	0	0	0
T6	0	1	0	0
T7	0	8	0	0
T8	0	11	0	0
T10	0	10	0	0
T11	0	9	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T31	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	50283	0	0
T1	9484	99	0	0
T3	0	288	0	0
T4	7201	270	0	0
T5	409	0	0	0
T6	0	20	0	0
T7	0	278	0	0
T8	0	459	0	0
T10	0	435	0	0
T11	0	790	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	288	0	0
T31	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5752473	0	0
T1	9484	5418	0	0
T4	7201	6792	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	66	0	0
T7	295293	1	0	0
T8	24750	5	0	0
T9	2888	0	0	0
T10	33641	0	0	0
T11	22316	0	0	0
T44	0	5	0	0
T50	1121	0	0	0
T75	0	7	0	0
T76	0	5	0	0
T77	0	2	0	0
T81	0	2	0	0
T82	0	4	0	0
T83	0	2	0	0
T90	0	1	0	0
T93	521	0	0	0
T94	439	0	0	0
T95	502	0	0	0
T96	446	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	16735	0	0
T1	9484	14	0	0
T3	0	160	0	0
T4	7201	64	0	0
T5	409	0	0	0
T7	0	3	0	0
T10	0	116	0	0
T11	0	282	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	227	0	0
T31	0	3	0	0
T36	0	58	0	0
T47	0	714	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	407	0	0
T1	9484	1	0	0
T3	0	3	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T10	0	5	0	0
T11	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T31	0	1	0	0
T36	0	2	0	0
T47	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5364754	0	0
T1	9484	4372	0	0
T4	7201	6395	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5366455	0	0
T1	9484	4382	0	0
T4	7201	6396	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	578	0	0
T1	9484	1	0	0
T3	0	3	0	0
T4	7201	5	0	0
T5	409	0	0	0
T6	0	1	0	0
T7	0	6	0	0
T8	0	6	0	0
T10	0	5	0	0
T11	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T31	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	477	0	0
T1	9484	1	0	0
T3	0	3	0	0
T4	7201	3	0	0
T5	409	0	0	0
T7	0	2	0	0
T8	0	5	0	0
T10	0	5	0	0
T11	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T31	0	1	0	0
T44	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	407	0	0
T1	9484	1	0	0
T3	0	3	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T10	0	5	0	0
T11	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T31	0	1	0	0
T36	0	2	0	0
T47	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	407	0	0
T1	9484	1	0	0
T3	0	3	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T10	0	5	0	0
T11	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T31	0	1	0	0
T36	0	2	0	0
T47	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	16275	0	0
T1	9484	13	0	0
T3	0	155	0	0
T4	7201	63	0	0
T5	409	0	0	0
T7	0	2	0	0
T10	0	111	0	0
T11	0	278	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	223	0	0
T31	0	2	0	0
T36	0	56	0	0
T47	0	696	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	352	0	0
T1	9484	1	0	0
T3	0	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	1	0	0
T10	0	5	0	0
T11	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T31	0	1	0	0
T36	0	2	0	0
T111	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T3,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T10
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T10
0	1	Covered	T4,T30,T79
1	0	Covered	T4,T30,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T10
0	1	Covered	T4,T3,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T3,T10
1	-	Covered	T4,T3,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T10
DetectSt	168	Covered	T4,T3,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T3,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T3,T10
DebounceSt->IdleSt	163	Covered	T4,T293,T98
DetectSt->IdleSt	186	Covered	T4,T30,T47
DetectSt->StableSt	191	Covered	T4,T3,T10
IdleSt->DebounceSt	148	Covered	T4,T3,T10
StableSt->IdleSt	206	Covered	T4,T3,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T3,T10
0	1	Covered	T4,T3,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T3,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T3,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T293,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T4,T30,T47
DetectSt	-	-	-	-	0	1	-	Covered	T4,T3,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T4,T3,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T3,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	3374	0	0
CntIncr_A	6439628	111823	0	0
CntNoWrap_A	6439628	5750154	0	0
DetectStDropOut_A	6439628	322	0	0
DetectedOut_A	6439628	89399	0	0
DetectedPulseOut_A	6439628	1036	0	0
DisabledIdleSt_A	6439628	5293996	0	0
DisabledNoDetection_A	6439628	5296254	0	0
EnterDebounceSt_A	6439628	1696	0	0
EnterDetectSt_A	6439628	1678	0	0
EnterStableSt_A	6439628	1036	0	0
PulseIsPulse_A	6439628	1036	0	0
StayInStableSt	6439628	88222	0	0
gen_high_event_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	894	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3374	0	0
T3	0	48	0	0
T4	7201	16	0	0
T5	409	0	0	0
T10	0	10	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	52	0	0
T46	0	34	0	0
T47	0	8	0	0
T48	506	0	0	0
T62	0	52	0	0
T63	0	46	0	0
T64	0	42	0	0
T65	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	111823	0	0
T3	0	1656	0	0
T4	7201	586	0	0
T5	409	0	0	0
T10	0	430	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	1913	0	0
T46	0	731	0	0
T47	0	382	0	0
T48	506	0	0	0
T62	0	2210	0	0
T63	0	1035	0	0
T64	0	960	0	0
T65	0	384	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5750154	0	0
T1	9484	5420	0	0
T4	7201	6784	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	322	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	18	0	0
T48	506	0	0	0
T71	0	10	0	0
T79	0	20	0	0
T85	0	22	0	0
T86	0	14	0	0
T87	0	25	0	0
T89	0	7	0	0
T294	0	3	0	0
T306	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	89399	0	0
T3	0	1468	0	0
T4	7201	333	0	0
T5	409	0	0	0
T10	0	671	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	1005	0	0
T48	506	0	0	0
T62	0	2244	0	0
T63	0	2020	0	0
T65	0	59	0	0
T78	0	631	0	0
T293	0	32	0	0
T304	0	9440	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1036	0	0
T3	0	24	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	17	0	0
T48	506	0	0	0
T62	0	26	0	0
T63	0	23	0	0
T65	0	8	0	0
T78	0	3	0	0
T293	0	1	0	0
T304	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5293996	0	0
T1	9484	5420	0	0
T4	7201	5791	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5296254	0	0
T1	9484	5431	0	0
T4	7201	5792	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1696	0	0
T3	0	24	0	0
T4	7201	9	0	0
T5	409	0	0	0
T10	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	26	0	0
T46	0	17	0	0
T47	0	4	0	0
T48	506	0	0	0
T62	0	26	0	0
T63	0	23	0	0
T64	0	21	0	0
T65	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1678	0	0
T3	0	24	0	0
T4	7201	7	0	0
T5	409	0	0	0
T10	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	26	0	0
T46	0	17	0	0
T47	0	4	0	0
T48	506	0	0	0
T62	0	26	0	0
T63	0	23	0	0
T64	0	21	0	0
T65	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1036	0	0
T3	0	24	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	17	0	0
T48	506	0	0	0
T62	0	26	0	0
T63	0	23	0	0
T65	0	8	0	0
T78	0	3	0	0
T293	0	1	0	0
T304	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1036	0	0
T3	0	24	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	5	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	17	0	0
T48	506	0	0	0
T62	0	26	0	0
T63	0	23	0	0
T65	0	8	0	0
T78	0	3	0	0
T293	0	1	0	0
T304	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	88222	0	0
T3	0	1443	0	0
T4	7201	328	0	0
T5	409	0	0	0
T10	0	665	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	985	0	0
T48	506	0	0	0
T62	0	2211	0	0
T63	0	1997	0	0
T65	0	51	0	0
T78	0	627	0	0
T293	0	31	0	0
T304	0	9409	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	894	0	0
T3	0	23	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	14	0	0
T48	506	0	0	0
T62	0	19	0	0
T63	0	23	0	0
T65	0	8	0	0
T78	0	2	0	0
T293	0	1	0	0
T304	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T3
1	1	Covered	T4,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T7
0	1	Covered	T44,T75,T32
1	0	Covered	T4,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T7
0	1	Covered	T3,T7,T8
1	0	Covered	T4

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T3,T7
1	-	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T7
DetectSt	168	Covered	T4,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T3,T7
DebounceSt->IdleSt	163	Covered	T4,T307,T76
DetectSt->IdleSt	186	Covered	T4,T44,T75
DetectSt->StableSt	191	Covered	T4,T3,T7
IdleSt->DebounceSt	148	Covered	T4,T3,T7
StableSt->IdleSt	206	Covered	T4,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T3,T7
0	1	Covered	T4,T3,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T307,T76,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T4,T44,T75
DetectSt	-	-	-	-	0	1	-	Covered	T4,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T4,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T4,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T4,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	940	0	0
CntIncr_A	6439628	49184	0	0
CntNoWrap_A	6439628	5752588	0	0
DetectStDropOut_A	6439628	65	0	0
DetectedOut_A	6439628	19594	0	0
DetectedPulseOut_A	6439628	377	0	0
DisabledIdleSt_A	6439628	5341532	0	0
DisabledNoDetection_A	6439628	5343259	0	0
EnterDebounceSt_A	6439628	496	0	0
EnterDetectSt_A	6439628	446	0	0
EnterStableSt_A	6439628	377	0	0
PulseIsPulse_A	6439628	377	0	0
StayInStableSt	6439628	19155	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	940	0	0
T3	0	4	0	0
T4	7201	8	0	0
T5	409	0	0	0
T7	0	6	0	0
T8	0	12	0	0
T10	0	4	0	0
T11	0	6	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	2	0	0
T44	0	28	0	0
T48	506	0	0	0
T75	0	2	0	0
T307	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	49184	0	0
T3	0	110	0	0
T4	7201	198	0	0
T5	409	0	0	0
T7	0	336	0	0
T8	0	450	0	0
T10	0	158	0	0
T11	0	654	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	103	0	0
T44	0	2063	0	0
T48	506	0	0	0
T75	0	129	0	0
T307	0	441	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5752588	0	0
T1	9484	5420	0	0
T4	7201	6792	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	65	0	0
T32	0	3	0	0
T33	0	1	0	0
T44	18688	14	0	0
T55	504	0	0	0
T56	496	0	0	0
T57	490	0	0	0
T75	0	1	0	0
T76	0	9	0	0
T83	0	4	0	0
T90	0	4	0	0
T106	406	0	0	0
T107	404	0	0	0
T108	520	0	0	0
T109	504	0	0	0
T274	0	7	0	0
T308	0	1	0	0
T309	0	4	0	0
T310	422	0	0	0
T311	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	19594	0	0
T3	0	191	0	0
T4	7201	65	0	0
T5	409	0	0	0
T7	0	183	0	0
T8	0	26	0	0
T10	0	62	0	0
T11	0	42	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	87	0	0
T46	0	82	0	0
T48	506	0	0	0
T111	0	69	0	0
T307	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	377	0	0
T3	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	3	0	0
T8	0	6	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	1	0	0
T46	0	1	0	0
T48	506	0	0	0
T111	0	1	0	0
T307	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5341532	0	0
T1	9484	4372	0	0
T4	7201	6465	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5343259	0	0
T1	9484	4382	0	0
T4	7201	6466	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	496	0	0
T3	0	2	0	0
T4	7201	5	0	0
T5	409	0	0	0
T7	0	3	0	0
T8	0	6	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	1	0	0
T44	0	14	0	0
T48	506	0	0	0
T75	0	1	0	0
T307	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	446	0	0
T3	0	2	0	0
T4	7201	3	0	0
T5	409	0	0	0
T7	0	3	0	0
T8	0	6	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	1	0	0
T44	0	14	0	0
T48	506	0	0	0
T75	0	1	0	0
T307	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	377	0	0
T3	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	3	0	0
T8	0	6	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	1	0	0
T46	0	1	0	0
T48	506	0	0	0
T111	0	1	0	0
T307	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	377	0	0
T3	0	2	0	0
T4	7201	1	0	0
T5	409	0	0	0
T7	0	3	0	0
T8	0	6	0	0
T10	0	2	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	1	0	0
T46	0	1	0	0
T48	506	0	0	0
T111	0	1	0	0
T307	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	19155	0	0
T3	0	189	0	0
T4	7201	64	0	0
T5	409	0	0	0
T7	0	180	0	0
T8	0	20	0	0
T10	0	60	0	0
T11	0	39	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T36	0	86	0	0
T46	0	81	0	0
T48	506	0	0	0
T111	0	68	0	0
T307	0	52	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	311	0	0
T3	14919	2	0	0
T6	14520	0	0	0
T7	0	3	0	0
T8	0	6	0	0
T10	0	2	0	0
T11	0	3	0	0
T25	502	0	0	0
T36	0	1	0	0
T41	580	0	0	0
T42	649	0	0	0
T43	40809	0	0	0
T46	0	1	0	0
T59	510	0	0	0
T60	502	0	0	0
T61	2200	0	0	0
T110	420	0	0	0
T111	0	1	0	0
T307	0	2	0	0
T312	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T3,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T10
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T10
0	1	Covered	T4,T10,T313
1	0	Covered	T4,T10,T313

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T30
0	1	Covered	T4,T3,T30
1	0	Covered	T71,T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T3,T30
1	-	Covered	T4,T3,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T10
DetectSt	168	Covered	T4,T3,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T3,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T3,T10
DebounceSt->IdleSt	163	Covered	T4,T293,T98
DetectSt->IdleSt	186	Covered	T4,T10,T313
DetectSt->StableSt	191	Covered	T4,T3,T30
IdleSt->DebounceSt	148	Covered	T4,T3,T10
StableSt->IdleSt	206	Covered	T4,T3,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T3,T10
0	1	Covered	T4,T3,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T3,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T3,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T293,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T4,T10,T313
DetectSt	-	-	-	-	0	1	-	Covered	T4,T3,T30
DetectSt	-	-	-	-	0	0	-	Covered	T4,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T4,T3,T30
StableSt	-	-	-	-	-	-	0	Covered	T4,T3,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	3248	0	0
CntIncr_A	6439628	102919	0	0
CntNoWrap_A	6439628	5750280	0	0
DetectStDropOut_A	6439628	367	0	0
DetectedOut_A	6439628	80170	0	0
DetectedPulseOut_A	6439628	1059	0	0
DisabledIdleSt_A	6439628	5307207	0	0
DisabledNoDetection_A	6439628	5309506	0	0
EnterDebounceSt_A	6439628	1635	0	0
EnterDetectSt_A	6439628	1613	0	0
EnterStableSt_A	6439628	1059	0	0
PulseIsPulse_A	6439628	1059	0	0
StayInStableSt	6439628	79012	0	0
gen_high_event_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	953	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3248	0	0
T3	0	18	0	0
T4	7201	16	0	0
T5	409	0	0	0
T10	0	52	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	12	0	0
T46	0	54	0	0
T47	0	16	0	0
T48	506	0	0	0
T62	0	50	0	0
T63	0	46	0	0
T64	0	38	0	0
T65	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	102919	0	0
T3	0	639	0	0
T4	7201	481	0	0
T5	409	0	0	0
T10	0	3297	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	312	0	0
T46	0	1350	0	0
T47	0	608	0	0
T48	506	0	0	0
T62	0	2000	0	0
T63	0	1449	0	0
T64	0	475	0	0
T65	0	754	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5750280	0	0
T1	9484	5420	0	0
T4	7201	6784	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	367	0	0
T4	7201	1	0	0
T5	409	0	0	0
T10	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T48	506	0	0	0
T71	0	5	0	0
T78	0	10	0	0
T79	0	4	0	0
T85	0	11	0	0
T86	0	15	0	0
T87	0	28	0	0
T299	0	7	0	0
T313	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	80170	0	0
T3	0	279	0	0
T4	7201	365	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	692	0	0
T46	0	1733	0	0
T47	0	1285	0	0
T48	506	0	0	0
T62	0	2374	0	0
T63	0	1606	0	0
T64	0	434	0	0
T65	0	1632	0	0
T304	0	1054	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1059	0	0
T3	0	9	0	0
T4	7201	5	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	6	0	0
T46	0	27	0	0
T47	0	8	0	0
T48	506	0	0	0
T62	0	25	0	0
T63	0	23	0	0
T64	0	19	0	0
T65	0	26	0	0
T304	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5307207	0	0
T1	9484	5420	0	0
T4	7201	5863	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5309506	0	0
T1	9484	5431	0	0
T4	7201	5864	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1635	0	0
T3	0	9	0	0
T4	7201	9	0	0
T5	409	0	0	0
T10	0	26	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	6	0	0
T46	0	27	0	0
T47	0	8	0	0
T48	506	0	0	0
T62	0	25	0	0
T63	0	23	0	0
T64	0	19	0	0
T65	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1613	0	0
T3	0	9	0	0
T4	7201	7	0	0
T5	409	0	0	0
T10	0	26	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	6	0	0
T46	0	27	0	0
T47	0	8	0	0
T48	506	0	0	0
T62	0	25	0	0
T63	0	23	0	0
T64	0	19	0	0
T65	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1059	0	0
T3	0	9	0	0
T4	7201	5	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	6	0	0
T46	0	27	0	0
T47	0	8	0	0
T48	506	0	0	0
T62	0	25	0	0
T63	0	23	0	0
T64	0	19	0	0
T65	0	26	0	0
T304	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1059	0	0
T3	0	9	0	0
T4	7201	5	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	6	0	0
T46	0	27	0	0
T47	0	8	0	0
T48	506	0	0	0
T62	0	25	0	0
T63	0	23	0	0
T64	0	19	0	0
T65	0	26	0	0
T304	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	79012	0	0
T3	0	269	0	0
T4	7201	360	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	683	0	0
T46	0	1703	0	0
T47	0	1271	0	0
T48	506	0	0	0
T62	0	2344	0	0
T63	0	1583	0	0
T64	0	415	0	0
T65	0	1604	0	0
T304	0	1048	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	953	0	0
T3	0	8	0	0
T4	7201	5	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T46	0	24	0	0
T47	0	2	0	0
T48	506	0	0	0
T62	0	20	0	0
T63	0	23	0	0
T64	0	19	0	0
T65	0	24	0	0
T304	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T4,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T11,T312,T314
1	0	Covered	T4,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T6,T7
1	0	Covered	T4

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T6
1	-	Covered	T1,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T6
DetectSt	168	Covered	T1,T4,T6
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T4,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T6
DebounceSt->IdleSt	163	Covered	T4,T7,T44
DetectSt->IdleSt	186	Covered	T4,T11,T312
DetectSt->StableSt	191	Covered	T1,T4,T6
IdleSt->DebounceSt	148	Covered	T1,T4,T6
StableSt->IdleSt	206	Covered	T1,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T6
0	1	Covered	T1,T4,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T44,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T6
DetectSt	-	-	-	-	1	-	-	Covered	T4,T11,T312
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	929	0	0
CntIncr_A	6439628	52979	0	0
CntNoWrap_A	6439628	5752599	0	0
DetectStDropOut_A	6439628	43	0	0
DetectedOut_A	6439628	16228	0	0
DetectedPulseOut_A	6439628	393	0	0
DisabledIdleSt_A	6439628	5358615	0	0
DisabledNoDetection_A	6439628	5360390	0	0
EnterDebounceSt_A	6439628	489	0	0
EnterDetectSt_A	6439628	440	0	0
EnterStableSt_A	6439628	393	0	0
PulseIsPulse_A	6439628	393	0	0
StayInStableSt	6439628	15811	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	367	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	929	0	0
T1	9484	2	0	0
T4	7201	8	0	0
T5	409	0	0	0
T6	0	4	0	0
T7	0	17	0	0
T8	0	8	0	0
T11	0	6	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	6	0	0
T44	0	14	0	0
T46	0	6	0	0
T47	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	52979	0	0
T1	9484	108	0	0
T4	7201	233	0	0
T5	409	0	0	0
T6	0	215	0	0
T7	0	1413	0	0
T8	0	280	0	0
T11	0	696	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	126	0	0
T44	0	1028	0	0
T46	0	219	0	0
T47	0	405	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5752599	0	0
T1	9484	5418	0	0
T4	7201	6792	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	43	0	0
T11	22316	3	0	0
T12	1082	0	0	0
T23	7334	0	0	0
T30	16291	0	0	0
T31	9645	0	0	0
T74	661	0	0	0
T83	0	1	0	0
T96	446	0	0	0
T172	0	3	0	0
T180	91079	0	0	0
T184	0	10	0	0
T312	0	1	0	0
T314	0	3	0	0
T315	0	1	0	0
T316	0	5	0	0
T317	0	2	0	0
T318	0	6	0	0
T319	422	0	0	0
T320	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	16228	0	0
T1	9484	5	0	0
T4	7201	65	0	0
T5	409	0	0	0
T6	0	179	0	0
T7	0	70	0	0
T8	0	40	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	261	0	0
T44	0	52	0	0
T46	0	159	0	0
T47	0	362	0	0
T111	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	393	0	0
T1	9484	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	8	0	0
T8	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T44	0	6	0	0
T46	0	3	0	0
T47	0	5	0	0
T111	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5358615	0	0
T1	9484	4372	0	0
T4	7201	6433	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5360390	0	0
T1	9484	4382	0	0
T4	7201	6434	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	489	0	0
T1	9484	1	0	0
T4	7201	5	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	9	0	0
T8	0	4	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T44	0	8	0	0
T46	0	3	0	0
T47	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	440	0	0
T1	9484	1	0	0
T4	7201	3	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	8	0	0
T8	0	4	0	0
T11	0	3	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T44	0	6	0	0
T46	0	3	0	0
T47	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	393	0	0
T1	9484	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	8	0	0
T8	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T44	0	6	0	0
T46	0	3	0	0
T47	0	5	0	0
T111	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	393	0	0
T1	9484	1	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	8	0	0
T8	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T44	0	6	0	0
T46	0	3	0	0
T47	0	5	0	0
T111	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	15811	0	0
T1	9484	4	0	0
T4	7201	64	0	0
T5	409	0	0	0
T6	0	177	0	0
T7	0	62	0	0
T8	0	36	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	258	0	0
T44	0	46	0	0
T46	0	153	0	0
T47	0	354	0	0
T111	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	367	0	0
T1	9484	1	0	0
T4	7201	0	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	8	0	0
T8	0	4	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	3	0	0
T32	0	3	0	0
T44	0	6	0	0
T47	0	2	0	0
T62	0	2	0	0
T111	0	13	0	0