Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T3,T10
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T3,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T10
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T3,T10
0	1	Covered	T4,T3,T46
1	0	Covered	T4,T3,T46

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T30
0	1	Covered	T4,T10,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T10,T30
1	-	Covered	T4,T10,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T3,T10
DetectSt	168	Covered	T4,T3,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T10,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T3,T10
DebounceSt->IdleSt	163	Covered	T4,T293,T98
DetectSt->IdleSt	186	Covered	T4,T3,T46
DetectSt->StableSt	191	Covered	T4,T10,T30
IdleSt->DebounceSt	148	Covered	T4,T3,T10
StableSt->IdleSt	206	Covered	T4,T10,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T3,T10
0	1	Covered	T4,T3,T10
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T3,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T3,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T3,T10
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T3,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T293,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T3,T10
DetectSt	-	-	-	-	1	-	-	Covered	T4,T3,T46
DetectSt	-	-	-	-	0	1	-	Covered	T4,T10,T30
DetectSt	-	-	-	-	0	0	-	Covered	T4,T3,T10
StableSt	-	-	-	-	-	-	1	Covered	T4,T10,T30
StableSt	-	-	-	-	-	-	0	Covered	T4,T10,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	3084	0	0
CntIncr_A	6439628	100624	0	0
CntNoWrap_A	6439628	5750444	0	0
DetectStDropOut_A	6439628	390	0	0
DetectedOut_A	6439628	64793	0	0
DetectedPulseOut_A	6439628	856	0	0
DisabledIdleSt_A	6439628	5314066	0	0
DisabledNoDetection_A	6439628	5316353	0	0
EnterDebounceSt_A	6439628	1555	0	0
EnterDetectSt_A	6439628	1529	0	0
EnterStableSt_A	6439628	856	0	0
PulseIsPulse_A	6439628	856	0	0
StayInStableSt	6439628	63823	0	0
gen_high_event_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	742	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	3084	0	0
T3	0	36	0	0
T4	7201	17	0	0
T5	409	0	0	0
T10	0	30	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	16	0	0
T46	0	40	0	0
T47	0	40	0	0
T48	506	0	0	0
T62	0	36	0	0
T63	0	38	0	0
T64	0	64	0	0
T65	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	100624	0	0
T3	0	1487	0	0
T4	7201	560	0	0
T5	409	0	0	0
T10	0	1260	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	552	0	0
T46	0	1076	0	0
T47	0	1300	0	0
T48	506	0	0	0
T62	0	1512	0	0
T63	0	1286	0	0
T64	0	736	0	0
T65	0	324	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5750444	0	0
T1	9484	5420	0	0
T4	7201	6783	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	390	0	0
T3	0	4	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T46	0	7	0	0
T48	506	0	0	0
T63	0	7	0	0
T79	0	24	0	0
T80	0	2	0	0
T85	0	22	0	0
T86	0	25	0	0
T305	0	5	0	0
T313	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	64793	0	0
T4	7201	366	0	0
T5	409	0	0	0
T10	0	2082	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	998	0	0
T47	0	4367	0	0
T48	506	0	0	0
T62	0	1556	0	0
T64	0	1953	0	0
T78	0	330	0	0
T293	0	36	0	0
T298	0	578	0	0
T304	0	583	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	856	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	15	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T47	0	20	0	0
T48	506	0	0	0
T62	0	18	0	0
T64	0	32	0	0
T78	0	2	0	0
T293	0	1	0	0
T298	0	13	0	0
T304	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5314066	0	0
T1	9484	5420	0	0
T4	7201	5786	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5316353	0	0
T1	9484	5431	0	0
T4	7201	5787	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1555	0	0
T3	0	18	0	0
T4	7201	10	0	0
T5	409	0	0	0
T10	0	15	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	506	0	0	0
T62	0	18	0	0
T63	0	19	0	0
T64	0	32	0	0
T65	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	1529	0	0
T3	0	18	0	0
T4	7201	7	0	0
T5	409	0	0	0
T10	0	15	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T46	0	20	0	0
T47	0	20	0	0
T48	506	0	0	0
T62	0	18	0	0
T63	0	19	0	0
T64	0	32	0	0
T65	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	856	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	15	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T47	0	20	0	0
T48	506	0	0	0
T62	0	18	0	0
T64	0	32	0	0
T78	0	2	0	0
T293	0	1	0	0
T298	0	13	0	0
T304	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	856	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	15	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T47	0	20	0	0
T48	506	0	0	0
T62	0	18	0	0
T64	0	32	0	0
T78	0	2	0	0
T293	0	1	0	0
T298	0	13	0	0
T304	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	63823	0	0
T4	7201	361	0	0
T5	409	0	0	0
T10	0	2059	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	986	0	0
T47	0	4329	0	0
T48	506	0	0	0
T62	0	1535	0	0
T64	0	1920	0	0
T78	0	327	0	0
T293	0	35	0	0
T298	0	565	0	0
T304	0	580	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	742	0	0
T4	7201	5	0	0
T5	409	0	0	0
T10	0	7	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T47	0	2	0	0
T48	506	0	0	0
T62	0	15	0	0
T64	0	31	0	0
T78	0	1	0	0
T293	0	1	0	0
T298	0	13	0	0
T304	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T4,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T3
1	1	Covered	T4,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T4,T111,T76
1	0	Covered	T4,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T6,T7,T8
1	0	Covered	T4

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T6,T7
1	-	Covered	T6,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T6,T7
DetectSt	168	Covered	T4,T6,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T4,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T6,T7
DebounceSt->IdleSt	163	Covered	T4,T7,T11
DetectSt->IdleSt	186	Covered	T4,T111,T76
DetectSt->StableSt	191	Covered	T4,T6,T7
IdleSt->DebounceSt	148	Covered	T4,T6,T7
StableSt->IdleSt	206	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T6,T7
0	1	Covered	T4,T6,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T4,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T11,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T4,T111,T76
DetectSt	-	-	-	-	0	1	-	Covered	T4,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T4,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T4,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6439628	903	0	0
CntIncr_A	6439628	49064	0	0
CntNoWrap_A	6439628	5752625	0	0
DetectStDropOut_A	6439628	52	0	0
DetectedOut_A	6439628	16120	0	0
DetectedPulseOut_A	6439628	372	0	0
DisabledIdleSt_A	6439628	5379121	0	0
DisabledNoDetection_A	6439628	5380886	0	0
EnterDebounceSt_A	6439628	476	0	0
EnterDetectSt_A	6439628	428	0	0
EnterStableSt_A	6439628	372	0	0
PulseIsPulse_A	6439628	372	0	0
StayInStableSt	6439628	15722	0	0
gen_high_level_sva.HighLevelEvent_A	6439628	5756019	0	0
gen_not_sticky_sva.StableStDropOut_A	6439628	344	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	903	0	0
T4	7201	8	0	0
T5	409	0	0	0
T6	0	4	0	0
T7	0	10	0	0
T8	0	6	0	0
T10	0	12	0	0
T11	0	13	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	8	0	0
T36	0	1	0	0
T44	0	5	0	0
T48	506	0	0	0
T75	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	49064	0	0
T4	7201	232	0	0
T5	409	0	0	0
T6	0	370	0	0
T7	0	674	0	0
T8	0	219	0	0
T10	0	498	0	0
T11	0	1312	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	300	0	0
T36	0	92	0	0
T44	0	374	0	0
T48	506	0	0	0
T75	0	303	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5752625	0	0
T1	9484	5420	0	0
T4	7201	6792	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	52	0	0
T4	7201	1	0	0
T5	409	0	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T48	506	0	0	0
T53	0	4	0	0
T76	0	4	0	0
T83	0	6	0	0
T111	0	2	0	0
T215	0	1	0	0
T308	0	3	0	0
T314	0	6	0	0
T321	0	3	0	0
T322	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	16120	0	0
T4	7201	64	0	0
T5	409	0	0	0
T6	0	26	0	0
T7	0	205	0	0
T8	0	21	0	0
T10	0	159	0	0
T11	0	222	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	214	0	0
T44	0	19	0	0
T47	0	1064	0	0
T48	506	0	0	0
T75	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	372	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	6	0	0
T11	0	6	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T44	0	2	0	0
T47	0	15	0	0
T48	506	0	0	0
T75	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5379121	0	0
T1	9484	4372	0	0
T4	7201	6432	0	0
T5	409	8	0	0
T13	527	126	0	0
T14	729	328	0	0
T15	502	101	0	0
T16	405	4	0	0
T17	436	35	0	0
T18	435	34	0	0
T19	633	232	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5380886	0	0
T1	9484	4382	0	0
T4	7201	6433	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	476	0	0
T4	7201	5	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	6	0	0
T8	0	3	0	0
T10	0	6	0	0
T11	0	7	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T36	0	1	0	0
T44	0	3	0	0
T48	506	0	0	0
T75	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	428	0	0
T4	7201	3	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	6	0	0
T11	0	6	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T44	0	2	0	0
T47	0	15	0	0
T48	506	0	0	0
T75	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	372	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	6	0	0
T11	0	6	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T44	0	2	0	0
T47	0	15	0	0
T48	506	0	0	0
T75	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	372	0	0
T4	7201	1	0	0
T5	409	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	6	0	0
T11	0	6	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	4	0	0
T44	0	2	0	0
T47	0	15	0	0
T48	506	0	0	0
T75	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	15722	0	0
T4	7201	63	0	0
T5	409	0	0	0
T6	0	24	0	0
T7	0	201	0	0
T8	0	18	0	0
T10	0	153	0	0
T11	0	216	0	0
T13	527	0	0	0
T14	729	0	0	0
T15	502	0	0	0
T16	405	0	0	0
T17	436	0	0	0
T18	435	0	0	0
T19	633	0	0	0
T30	0	209	0	0
T44	0	17	0	0
T47	0	1049	0	0
T48	506	0	0	0
T75	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	5756019	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6439628	344	0	0
T6	14520	2	0	0
T7	295293	4	0	0
T8	24750	3	0	0
T9	2888	0	0	0
T10	0	6	0	0
T11	0	6	0	0
T24	498	0	0	0
T25	502	0	0	0
T30	0	3	0	0
T43	40809	0	0	0
T44	0	2	0	0
T47	0	15	0	0
T60	502	0	0	0
T61	2200	0	0	0
T75	0	3	0	0
T145	426	0	0	0
T312	0	5	0	0