Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1368930239	9627	0	0
auto_block_debounce_ctl_rd_A	1368930239	1934	0	0
auto_block_out_ctl_rd_A	1368930239	2483	0	0
com_det_ctl_0_rd_A	1368930239	3971	0	0
com_det_ctl_1_rd_A	1368930239	4041	0	0
com_det_ctl_2_rd_A	1368930239	4104	0	0
com_det_ctl_3_rd_A	1368930239	3951	0	0
com_out_ctl_0_rd_A	1368930239	4479	0	0
com_out_ctl_1_rd_A	1368930239	4465	0	0
com_out_ctl_2_rd_A	1368930239	4561	0	0
com_out_ctl_3_rd_A	1368930239	4527	0	0
com_pre_det_ctl_0_rd_A	1368930239	1394	0	0
com_pre_det_ctl_1_rd_A	1368930239	1606	0	0
com_pre_det_ctl_2_rd_A	1368930239	1517	0	0
com_pre_det_ctl_3_rd_A	1368930239	1568	0	0
com_pre_sel_ctl_0_rd_A	1368930239	4787	0	0
com_pre_sel_ctl_1_rd_A	1368930239	4554	0	0
com_pre_sel_ctl_2_rd_A	1368930239	4694	0	0
com_pre_sel_ctl_3_rd_A	1368930239	4943	0	0
com_sel_ctl_0_rd_A	1368930239	4822	0	0
com_sel_ctl_1_rd_A	1368930239	4603	0	0
com_sel_ctl_2_rd_A	1368930239	4849	0	0
com_sel_ctl_3_rd_A	1368930239	4850	0	0
ec_rst_ctl_rd_A	1368930239	2835	0	0
intr_enable_rd_A	1368930239	2035	0	0
key_intr_ctl_rd_A	1368930239	3412	0	0
key_intr_debounce_ctl_rd_A	1368930239	1476	0	0
key_invert_ctl_rd_A	1368930239	4706	0	0
pin_allowed_ctl_rd_A	1368930239	5607	0	0
pin_out_ctl_rd_A	1368930239	4940	0	0
pin_out_value_rd_A	1368930239	4782	0	0
regwen_rd_A	1368930239	1627	0	0
ulp_ac_debounce_ctl_rd_A	1368930239	1638	0	0
ulp_ctl_rd_A	1368930239	1721	0	0
ulp_lid_debounce_ctl_rd_A	1368930239	1729	0	0
ulp_pwrb_debounce_ctl_rd_A	1368930239	1761	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	9627	0	0
T1	464754	10	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	23	0	0
T7	0	7	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	2	0	0
T31	0	11	0	0
T33	0	9	0	0
T36	0	7	0	0
T134	0	10	0	0
T196	0	13	0	0
T258	0	10	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1934	0	0
T2	211385	0	0	0
T3	179032	0	0	0
T6	364681	0	0	0
T7	0	2	0	0
T23	0	22	0	0
T36	0	36	0	0
T39	280332	5	0	0
T40	320003	0	0	0
T41	290130	3	0	0
T42	314633	2	0	0
T43	0	11	0	0
T59	33164	0	0	0
T110	210539	0	0	0
T206	50612	0	0	0
T255	0	7	0	0
T257	0	16	0	0
T344	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2483	0	0
T2	211385	0	0	0
T3	179032	0	0	0
T6	364681	0	0	0
T23	0	2	0	0
T36	0	13	0	0
T39	280332	5	0	0
T40	320003	0	0	0
T41	290130	6	0	0
T42	314633	5	0	0
T43	0	1	0	0
T59	33164	0	0	0
T74	0	13	0	0
T110	210539	0	0	0
T206	50612	0	0	0
T255	0	3	0	0
T257	0	11	0	0
T344	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	3971	0	0
T7	281409	41	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	6	0	0
T35	0	21	0	0
T36	0	25	0	0
T46	0	42	0	0
T50	274850	0	0	0
T53	0	23	0	0
T62	0	97	0	0
T75	0	63	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	29	0	0
T312	0	71	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4041	0	0
T7	281409	60	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	9	0	0
T35	0	10	0	0
T36	0	17	0	0
T46	0	54	0	0
T50	274850	0	0	0
T53	0	45	0	0
T62	0	79	0	0
T75	0	60	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	55	0	0
T312	0	73	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4104	0	0
T7	281409	61	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	10	0	0
T35	0	10	0	0
T36	0	25	0	0
T46	0	65	0	0
T50	274850	0	0	0
T53	0	40	0	0
T62	0	88	0	0
T75	0	61	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	41	0	0
T312	0	73	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	3951	0	0
T7	281409	72	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	14	0	0
T35	0	13	0	0
T36	0	40	0	0
T46	0	74	0	0
T50	274850	0	0	0
T53	0	29	0	0
T62	0	79	0	0
T75	0	63	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	27	0	0
T312	0	53	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4479	0	0
T7	281409	33	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	20	0	0
T35	0	2	0	0
T36	0	26	0	0
T46	0	53	0	0
T50	274850	0	0	0
T53	0	57	0	0
T62	0	76	0	0
T75	0	55	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	44	0	0
T312	0	75	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4465	0	0
T7	281409	36	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	15	0	0
T35	0	6	0	0
T36	0	42	0	0
T46	0	61	0	0
T50	274850	0	0	0
T53	0	45	0	0
T62	0	88	0	0
T75	0	79	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	57	0	0
T312	0	64	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4561	0	0
T7	281409	46	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	8	0	0
T35	0	3	0	0
T36	0	37	0	0
T46	0	65	0	0
T50	274850	0	0	0
T53	0	37	0	0
T62	0	86	0	0
T75	0	43	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	51	0	0
T312	0	71	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4527	0	0
T7	281409	36	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	9	0	0
T35	0	8	0	0
T36	0	29	0	0
T46	0	40	0	0
T50	274850	0	0	0
T53	0	45	0	0
T62	0	63	0	0
T75	0	66	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	64	0	0
T312	0	65	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1394	0	0
T7	281409	3	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	5	0	0
T35	0	13	0	0
T36	0	24	0	0
T50	274850	0	0	0
T91	0	24	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T229	0	36	0	0
T282	0	31	0	0
T348	0	10	0	0
T349	0	13	0	0
T350	0	16	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1606	0	0
T7	281409	12	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	28	0	0
T35	0	7	0	0
T36	0	23	0	0
T50	274850	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T124	0	2	0	0
T229	0	10	0	0
T282	0	23	0	0
T348	0	7	0	0
T349	0	14	0	0
T350	0	9	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1517	0	0
T7	281409	4	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	15	0	0
T35	0	10	0	0
T36	0	16	0	0
T50	274850	0	0	0
T91	0	27	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T229	0	25	0	0
T282	0	31	0	0
T348	0	4	0	0
T349	0	5	0	0
T350	0	22	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1568	0	0
T7	281409	3	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	10	0	0
T35	0	7	0	0
T36	0	16	0	0
T50	274850	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T124	0	5	0	0
T229	0	35	0	0
T282	0	20	0	0
T348	0	11	0	0
T349	0	10	0	0
T350	0	10	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4787	0	0
T7	281409	56	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	9	0	0
T35	0	3	0	0
T36	0	10	0	0
T46	0	57	0	0
T50	274850	0	0	0
T53	0	47	0	0
T62	0	86	0	0
T75	0	52	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	45	0	0
T312	0	83	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4554	0	0
T7	281409	62	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	7	0	0
T35	0	13	0	0
T36	0	19	0	0
T46	0	40	0	0
T50	274850	0	0	0
T53	0	43	0	0
T62	0	85	0	0
T75	0	72	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	52	0	0
T312	0	58	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4694	0	0
T7	281409	50	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	3	0	0
T35	0	10	0	0
T36	0	38	0	0
T46	0	65	0	0
T50	274850	0	0	0
T53	0	36	0	0
T62	0	65	0	0
T75	0	74	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	44	0	0
T312	0	74	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4943	0	0
T7	281409	59	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	12	0	0
T35	0	1	0	0
T36	0	30	0	0
T46	0	41	0	0
T50	274850	0	0	0
T53	0	41	0	0
T62	0	74	0	0
T75	0	67	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	35	0	0
T312	0	62	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4822	0	0
T7	281409	57	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	10	0	0
T35	0	9	0	0
T36	0	26	0	0
T46	0	49	0	0
T50	274850	0	0	0
T53	0	13	0	0
T62	0	92	0	0
T75	0	91	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	43	0	0
T312	0	99	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4603	0	0
T7	281409	63	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	15	0	0
T35	0	16	0	0
T36	0	21	0	0
T46	0	51	0	0
T50	274850	0	0	0
T53	0	28	0	0
T62	0	86	0	0
T75	0	75	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	47	0	0
T312	0	64	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4849	0	0
T7	281409	57	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	12	0	0
T35	0	3	0	0
T36	0	28	0	0
T46	0	58	0	0
T50	274850	0	0	0
T53	0	32	0	0
T62	0	93	0	0
T75	0	82	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	54	0	0
T312	0	89	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4850	0	0
T7	281409	71	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	10	0	0
T35	0	3	0	0
T36	0	23	0	0
T46	0	52	0	0
T50	274850	0	0	0
T53	0	17	0	0
T62	0	79	0	0
T75	0	66	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T298	0	50	0	0
T312	0	56	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2835	0	0
T7	281409	30	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	32	0	0
T36	0	36	0	0
T46	0	8	0	0
T50	274850	0	0	0
T53	0	27	0	0
T62	0	39	0	0
T75	0	22	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T108	0	5	0	0
T312	0	60	0	0
T351	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2035	0	0
T7	281409	13	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	19	0	0
T35	0	21	0	0
T36	0	53	0	0
T50	274850	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T229	0	36	0	0
T240	0	2	0	0
T257	0	6	0	0
T282	0	67	0	0
T348	0	40	0	0
T352	0	3	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	3412	0	0
T2	211385	6	0	0
T3	179032	0	0	0
T6	364681	0	0	0
T7	0	4	0	0
T23	0	7	0	0
T35	0	20	0	0
T36	0	42	0	0
T41	290130	0	0	0
T42	314633	0	0	0
T43	204048	0	0	0
T59	33164	0	0	0
T60	125592	0	0	0
T68	0	2	0	0
T110	210539	0	0	0
T144	0	8	0	0
T151	0	3	0	0
T166	0	1	0	0
T201	0	1	0	0
T206	50612	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1476	0	0
T7	281409	1	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	10	0	0
T35	0	8	0	0
T36	0	38	0	0
T50	274850	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T124	0	1	0	0
T229	0	30	0	0
T282	0	35	0	0
T348	0	11	0	0
T349	0	17	0	0
T350	0	19	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4706	0	0
T7	281409	104	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	57	0	0
T35	0	66	0	0
T36	0	322	0	0
T50	274850	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T150	0	50	0	0
T185	0	48	0	0
T192	0	36	0	0
T200	0	54	0	0
T301	0	35	0	0
T353	0	48	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	5607	0	0
T7	281409	4	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T23	0	59	0	0
T24	54853	0	0	0
T25	243456	51	0	0
T36	0	160	0	0
T50	274850	0	0	0
T61	241987	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T132	0	73	0	0
T145	36242	0	0	0
T191	0	64	0	0
T257	0	65	0	0
T354	0	45	0	0
T355	0	41	0	0
T356	0	68	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4940	0	0
T7	281409	15	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T23	0	70	0	0
T24	54853	0	0	0
T25	243456	67	0	0
T36	0	185	0	0
T50	274850	0	0	0
T61	241987	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T132	0	67	0	0
T145	36242	0	0	0
T191	0	78	0	0
T257	0	78	0	0
T354	0	60	0	0
T355	0	54	0	0
T356	0	63	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	4782	0	0
T7	281409	5	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T23	0	94	0	0
T24	54853	0	0	0
T25	243456	75	0	0
T36	0	138	0	0
T50	274850	0	0	0
T61	241987	0	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T132	0	79	0	0
T145	36242	0	0	0
T191	0	73	0	0
T257	0	87	0	0
T354	0	48	0	0
T355	0	39	0	0
T356	0	85	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1627	0	0
T7	281409	5	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	9	0	0
T35	0	4	0	0
T36	0	20	0	0
T50	274850	0	0	0
T91	0	29	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T229	0	30	0	0
T282	0	31	0	0
T348	0	4	0	0
T349	0	10	0	0
T350	0	16	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1638	0	0
T7	281409	24	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	19	0	0
T35	0	6	0	0
T36	0	35	0	0
T50	274850	0	0	0
T52	0	8	0	0
T53	0	10	0	0
T54	0	5	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T114	0	18	0	0
T348	0	17	0	0
T357	0	16	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1721	0	0
T23	337601	21	0	0
T35	0	11	0	0
T36	0	25	0	0
T44	897002	0	0	0
T52	0	8	0	0
T53	0	11	0	0
T55	27763	0	0	0
T56	247960	0	0	0
T57	120110	0	0	0
T106	44613	0	0	0
T107	96973	0	0	0
T108	260230	0	0	0
T109	101019	0	0	0
T114	0	14	0	0
T150	0	2	0	0
T269	0	3	0	0
T310	210881	0	0	0
T348	0	14	0	0
T357	0	18	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1729	0	0
T7	281409	8	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	22	0	0
T35	0	22	0	0
T36	0	28	0	0
T50	274850	0	0	0
T52	0	15	0	0
T53	0	6	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T114	0	10	0	0
T269	0	3	0	0
T348	0	4	0	0
T357	0	15	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1761	0	0
T7	281409	43	0	0
T8	118800	0	0	0
T9	105840	0	0	0
T10	159801	0	0	0
T11	557924	0	0	0
T23	0	6	0	0
T35	0	22	0	0
T36	0	39	0	0
T50	274850	0	0	0
T52	0	23	0	0
T53	0	12	0	0
T54	0	2	0	0
T93	248091	0	0	0
T94	210700	0	0	0
T95	120791	0	0	0
T96	11153	0	0	0
T114	0	5	0	0
T348	0	14	0	0
T357	0	7	0	0