Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T23
1	-	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T19
0	0	1	Covered	T1,T4,T19
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T19
0	0	1	Covered	T1,T4,T19
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	118556857	0	0
DstReqKnown_A	227701026	197997334	0	0
SrcAckBusyChk_A	2147483647	120654	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118556857	0	0
T1	9759834	21951	0	0
T3	0	13270	0	0
T4	12175774	143817	0	0
T5	6688106	0	0	0
T6	0	29111	0	0
T7	0	13596	0	0
T8	0	156019	0	0
T9	0	15949	0	0
T10	0	186045	0	0
T11	0	4880	0	0
T13	1704760	0	0	0
T14	3099406	3739	0	0
T15	8367026	0	0	0
T16	2344776	0	0	0
T17	1483896	0	0	0
T18	3705218	0	0	0
T19	10231178	0	0	0
T30	0	17767	0	0
T31	0	2360	0	0
T39	0	11229	0	0
T40	0	11991	0	0
T41	0	12921	0	0
T42	0	11585	0	0
T43	0	934	0	0
T44	0	68448	0	0
T45	0	1497	0	0
T46	0	1631	0	0
T47	0	44342	0	0
T48	790348	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227701026	197997334	0	0
T1	322456	184654	0	0
T4	244834	231234	0	0
T5	13906	306	0	0
T13	17918	4318	0	0
T14	24786	11186	0	0
T15	17068	3468	0	0
T16	13770	170	0	0
T17	14824	1224	0	0
T18	14790	1190	0	0
T19	21522	7922	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120654	0	0
T1	9759834	15	0	0
T3	0	36	0	0
T4	12175774	84	0	0
T5	6688106	0	0	0
T6	0	32	0	0
T7	0	42	0	0
T8	0	88	0	0
T9	0	9	0	0
T10	0	108	0	0
T11	0	64	0	0
T13	1704760	0	0	0
T14	3099406	8	0	0
T15	8367026	0	0	0
T16	2344776	0	0	0
T17	1483896	0	0	0
T18	3705218	0	0	0
T19	10231178	0	0	0
T30	0	45	0	0
T31	0	6	0	0
T39	0	8	0	0
T40	0	7	0	0
T41	0	7	0	0
T42	0	7	0	0
T43	0	6	0	0
T44	0	42	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	26	0	0
T48	790348	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	15801636	15790246	0	0
T4	12175774	12175536	0	0
T5	6688106	6685488	0	0
T13	1704760	1701972	0	0
T14	3099406	3096686	0	0
T15	8367026	8363898	0	0
T16	2344776	2342192	0	0
T17	1483896	1481924	0	0
T18	3705218	3701988	0	0
T19	10231178	10228322	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T26,T28,T49
1	-	Covered	T1,T3,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T3,T6
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T3,T6
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	983761	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1067	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	983761	0	0
T1	464754	1450	0	0
T3	0	936	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	1814	0	0
T7	0	1394	0	0
T8	0	10930	0	0
T10	0	18961	0	0
T11	0	627	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1400	0	0
T30	0	2852	0	0
T44	0	9577	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1067	0	0
T1	464754	1	0	0
T3	0	2	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	6	0	0
T10	0	11	0	0
T11	0	7	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1	0	0
T30	0	7	0	0
T44	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T19

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T4,T19

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T19

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T4,T19

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T19
0	0	1	Covered	T1,T4,T19
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T19
0	0	1	Covered	T1,T4,T19
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	2082094	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	2119	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2082094	0	0
T1	464754	2834	0	0
T3	0	1582	0	0
T4	358111	1500	0	0
T5	196709	0	0	0
T6	0	4620	0	0
T7	0	3342	0	0
T8	0	19126	0	0
T10	0	20429	0	0
T11	0	738	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	1895	0	0
T50	0	715	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2119	0	0
T1	464754	2	0	0
T3	0	4	0	0
T4	358111	1	0	0
T5	196709	0	0	0
T6	0	5	0	0
T7	0	10	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	1	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T9
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T9
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1130224	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1063	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1130224	0	0
T4	358111	1500	0	0
T5	196709	0	0	0
T7	0	2230	0	0
T9	0	1927	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1426	0	0
T29	0	777	0	0
T36	0	469	0	0
T48	60796	0	0	0
T51	0	679	0	0
T52	0	4761	0	0
T53	0	1280	0	0
T54	0	1731	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1063	0	0
T4	358111	1	0	0
T5	196709	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T36	0	1	0	0
T48	60796	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T9
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T9
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1129059	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1069	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1129059	0	0
T4	358111	1498	0	0
T5	196709	0	0	0
T7	0	2167	0	0
T9	0	1923	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1423	0	0
T29	0	775	0	0
T36	0	456	0	0
T48	60796	0	0	0
T51	0	677	0	0
T52	0	4732	0	0
T53	0	1251	0	0
T54	0	1723	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1069	0	0
T4	358111	1	0	0
T5	196709	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T36	0	1	0	0
T48	60796	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T7,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T9
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T9
0	0	1	Covered	T4,T7,T9
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1130670	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1062	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1130670	0	0
T4	358111	1496	0	0
T5	196709	0	0	0
T7	0	2119	0	0
T9	0	1921	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1421	0	0
T29	0	773	0	0
T36	0	446	0	0
T48	60796	0	0	0
T51	0	673	0	0
T52	0	4697	0	0
T53	0	1228	0	0
T54	0	1712	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1062	0	0
T4	358111	1	0	0
T5	196709	0	0	0
T7	0	6	0	0
T9	0	1	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T36	0	1	0	0
T48	60796	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T24,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T24,T7
1	1	Covered	T1,T24,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T24,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T24,T7
1	1	Covered	T1,T24,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T24,T7
0	0	1	Covered	T1,T24,T7
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T24,T7
0	0	1	Covered	T1,T24,T7
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	2726151	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	3023	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2726151	0	0
T1	464754	34189	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T7	0	13387	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	33496	0	0
T24	0	7816	0	0
T31	0	16444	0	0
T36	0	41614	0	0
T55	0	3715	0	0
T56	0	37006	0	0
T57	0	16663	0	0
T58	0	21739	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	3023	0	0
T1	464754	20	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T7	0	40	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	20	0	0
T24	0	20	0	0
T31	0	40	0	0
T36	0	100	0	0
T55	0	20	0	0
T56	0	20	0	0
T57	0	20	0	0
T58	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T13,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T13,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T13,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T13,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T13,T15
0	0	1	Covered	T1,T13,T15
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T13,T15
0	0	1	Covered	T1,T13,T15
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	6053140	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	6902	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	6053140	0	0
T1	464754	36378	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	53865	0	0
T13	50140	6576	0	0
T14	91159	0	0	0
T15	246089	33912	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T24	0	327	0	0
T25	0	33475	0	0
T48	0	8689	0	0
T59	0	4476	0	0
T60	0	16645	0	0
T61	0	7740	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	6902	0	0
T1	464754	21	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	60	0	0
T13	50140	20	0	0
T14	91159	0	0	0
T15	246089	20	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T24	0	1	0	0
T25	0	20	0	0
T48	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T13

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T13

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T13

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T13

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T13
0	0	1	Covered	T1,T4,T13
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T13
0	0	1	Covered	T1,T4,T13
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7272961	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	8151	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7272961	0	0
T1	464754	42055	0	0
T3	0	1590	0	0
T4	358111	1496	0	0
T5	196709	0	0	0
T6	0	60333	0	0
T13	50140	6656	0	0
T14	91159	0	0	0
T15	246089	34200	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	1897	0	0
T48	0	8769	0	0
T59	0	4556	0	0
T60	0	16923	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	8151	0	0
T1	464754	24	0	0
T3	0	4	0	0
T4	358111	1	0	0
T5	196709	0	0	0
T6	0	67	0	0
T13	50140	20	0	0
T14	91159	0	0	0
T15	246089	20	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	1	0	0
T48	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T13,T15

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T13,T15

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T13,T15

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T13,T15
1	1	Covered	T1,T13,T15

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T13,T15
0	0	1	Covered	T1,T13,T15
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T13,T15
0	0	1	Covered	T1,T13,T15
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	6009910	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	6809	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	6009910	0	0
T1	464754	34080	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	53985	0	0
T7	0	26441	0	0
T13	50140	6616	0	0
T14	91159	0	0	0
T15	246089	34045	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T25	0	33673	0	0
T48	0	8729	0	0
T59	0	4516	0	0
T60	0	16789	0	0
T61	0	7780	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	6809	0	0
T1	464754	20	0	0
T4	358111	0	0	0
T5	196709	0	0	0
T6	0	60	0	0
T7	0	80	0	0
T13	50140	20	0	0
T14	91159	0	0	0
T15	246089	20	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T25	0	20	0	0
T48	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T2,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T2,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T2,T6
0	0	1	Covered	T4,T2,T6
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T2,T6
0	0	1	Covered	T4,T2,T6
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1214773	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1075	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1214773	0	0
T2	0	1898	0	0
T4	358111	46453	0	0
T5	196709	0	0	0
T6	0	1037	0	0
T7	0	1086	0	0
T9	0	1935	0	0
T12	0	1438	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T31	0	833	0	0
T32	0	1496	0	0
T36	0	1417	0	0
T37	0	1466	0	0
T48	60796	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1075	0	0
T2	0	1	0	0
T4	358111	28	0	0
T5	196709	0	0	0
T6	0	1	0	0
T7	0	3	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T48	60796	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	2074374	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	2094	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2074374	0	0
T1	464754	1371	0	0
T2	0	1881	0	0
T3	0	1559	0	0
T4	358111	3489	0	0
T5	196709	0	0	0
T6	0	3573	0	0
T7	0	3943	0	0
T8	0	19055	0	0
T9	0	1933	0	0
T10	0	20405	0	0
T11	0	722	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2094	0	0
T1	464754	1	0	0
T2	0	1	0	0
T3	0	4	0	0
T4	358111	2	0	0
T5	196709	0	0	0
T6	0	4	0	0
T7	0	12	0	0
T8	0	11	0	0
T9	0	1	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T14
0	0	1	Covered	T1,T4,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T14
0	0	1	Covered	T1,T4,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1416616	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1339	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1416616	0	0
T1	464754	6346	0	0
T4	358111	3501	0	0
T5	196709	0	0	0
T6	0	7269	0	0
T9	0	10640	0	0
T13	50140	0	0	0
T14	91159	2373	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T39	0	6992	0	0
T40	0	8496	0	0
T41	0	7477	0	0
T42	0	6774	0	0
T43	0	482	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1339	0	0
T1	464754	4	0	0
T4	358111	2	0	0
T5	196709	0	0	0
T6	0	8	0	0
T9	0	6	0	0
T13	50140	0	0	0
T14	91159	5	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T39	0	5	0	0
T40	0	5	0	0
T41	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T14
0	0	1	Covered	T1,T4,T14
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T14
0	0	1	Covered	T1,T4,T14
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1275083	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1192	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1275083	0	0
T1	464754	4368	0	0
T4	358111	1500	0	0
T5	196709	0	0	0
T6	0	5444	0	0
T9	0	5309	0	0
T13	50140	0	0	0
T14	91159	1366	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T39	0	4237	0	0
T40	0	3495	0	0
T41	0	5444	0	0
T42	0	4811	0	0
T43	0	452	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1192	0	0
T1	464754	3	0	0
T4	358111	1	0	0
T5	196709	0	0	0
T6	0	6	0	0
T9	0	3	0	0
T13	50140	0	0	0
T14	91159	3	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T39	0	3	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7483767	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	7419	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7483767	0	0
T3	0	26469	0	0
T4	358111	18987	0	0
T5	196709	0	0	0
T10	0	121872	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	24322	0	0
T45	0	1499	0	0
T46	0	28299	0	0
T47	0	160971	0	0
T48	60796	0	0	0
T62	0	39777	0	0
T63	0	106056	0	0
T64	0	8652	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7419	0	0
T3	0	64	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T10	0	73	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	59	0	0
T45	0	1	0	0
T46	0	89	0	0
T47	0	93	0	0
T48	60796	0	0	0
T62	0	97	0	0
T63	0	67	0	0
T64	0	87	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7326114	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	7324	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7326114	0	0
T3	0	27340	0	0
T4	358111	18981	0	0
T5	196709	0	0	0
T10	0	134340	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	27610	0	0
T46	0	21211	0	0
T47	0	177257	0	0
T48	60796	0	0	0
T62	0	29855	0	0
T63	0	99558	0	0
T64	0	8292	0	0
T65	0	127561	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7324	0	0
T3	0	68	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T10	0	81	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	68	0	0
T46	0	72	0	0
T47	0	104	0	0
T48	60796	0	0	0
T62	0	79	0	0
T63	0	63	0	0
T64	0	87	0	0
T65	0	75	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7234938	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	7307	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7234938	0	0
T3	0	32104	0	0
T4	358111	18981	0	0
T5	196709	0	0	0
T10	0	142020	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	24702	0	0
T46	0	17896	0	0
T47	0	162236	0	0
T48	60796	0	0	0
T62	0	29387	0	0
T63	0	99300	0	0
T64	0	6276	0	0
T65	0	95437	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7307	0	0
T3	0	83	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T10	0	86	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	62	0	0
T46	0	62	0	0
T47	0	96	0	0
T48	60796	0	0	0
T62	0	80	0	0
T63	0	63	0	0
T64	0	68	0	0
T65	0	57	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7391130	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	7494	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7391130	0	0
T3	0	35166	0	0
T4	358111	18981	0	0
T5	196709	0	0	0
T10	0	117546	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	23994	0	0
T46	0	24235	0	0
T47	0	140994	0	0
T48	60796	0	0	0
T62	0	32051	0	0
T63	0	136393	0	0
T64	0	4995	0	0
T65	0	140205	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7494	0	0
T3	0	92	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T10	0	71	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	60	0	0
T46	0	89	0	0
T47	0	84	0	0
T48	60796	0	0	0
T62	0	87	0	0
T63	0	86	0	0
T64	0	55	0	0
T65	0	83	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1441281	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1315	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1441281	0	0
T3	0	1625	0	0
T4	358111	15468	0	0
T5	196709	0	0	0
T10	0	20885	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	2063	0	0
T45	0	1497	0	0
T46	0	1631	0	0
T47	0	44342	0	0
T48	60796	0	0	0
T62	0	4860	0	0
T63	0	1799	0	0
T64	0	238	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1315	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T10	0	12	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	26	0	0
T48	60796	0	0	0
T62	0	12	0	0
T63	0	1	0	0
T64	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1447238	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1351	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1447238	0	0
T3	0	1486	0	0
T4	358111	15462	0	0
T5	196709	0	0	0
T10	0	20765	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	2013	0	0
T46	0	1358	0	0
T47	0	43380	0	0
T48	60796	0	0	0
T62	0	4218	0	0
T63	0	1789	0	0
T64	0	218	0	0
T65	0	5301	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1351	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T10	0	12	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T46	0	5	0	0
T47	0	26	0	0
T48	60796	0	0	0
T62	0	12	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1459943	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1348	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1459943	0	0
T3	0	1344	0	0
T4	358111	15462	0	0
T5	196709	0	0	0
T10	0	20645	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1963	0	0
T46	0	1578	0	0
T47	0	42412	0	0
T48	60796	0	0	0
T62	0	4564	0	0
T63	0	1779	0	0
T64	0	198	0	0
T65	0	5271	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1348	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T10	0	12	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T46	0	5	0	0
T47	0	26	0	0
T48	60796	0	0	0
T62	0	12	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T3,T10
1	1	Covered	T4,T3,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T3,T10
0	0	1	Covered	T4,T3,T10
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1420539	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1321	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1420539	0	0
T3	0	1351	0	0
T4	358111	15462	0	0
T5	196709	0	0	0
T10	0	20525	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1913	0	0
T46	0	1342	0	0
T47	0	41467	0	0
T48	60796	0	0	0
T62	0	4438	0	0
T63	0	1769	0	0
T64	0	238	0	0
T65	0	5241	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1321	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T10	0	12	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T46	0	5	0	0
T47	0	26	0	0
T48	60796	0	0	0
T62	0	12	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	8137339	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	8100	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	8137339	0	0
T1	464754	1461	0	0
T3	0	26834	0	0
T4	358111	18951	0	0
T5	196709	0	0	0
T6	0	2859	0	0
T7	0	3259	0	0
T8	0	20115	0	0
T10	0	121946	0	0
T11	0	730	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	24410	0	0
T31	0	1189	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	8100	0	0
T1	464754	1	0	0
T3	0	64	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T6	0	3	0	0
T7	0	9	0	0
T8	0	11	0	0
T10	0	73	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	59	0	0
T31	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7946835	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	7968	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7946835	0	0
T1	464754	1452	0	0
T3	0	27737	0	0
T4	358111	18945	0	0
T5	196709	0	0	0
T6	0	1817	0	0
T7	0	1459	0	0
T8	0	20044	0	0
T10	0	134430	0	0
T11	0	714	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	27716	0	0
T44	0	11506	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7968	0	0
T1	464754	1	0	0
T3	0	68	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	81	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	68	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7834168	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	7926	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7834168	0	0
T1	464754	1449	0	0
T3	0	32579	0	0
T4	358111	18945	0	0
T5	196709	0	0	0
T6	0	1813	0	0
T7	0	1423	0	0
T8	0	19969	0	0
T10	0	142120	0	0
T11	0	698	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	24796	0	0
T44	0	11492	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7926	0	0
T1	464754	1	0	0
T3	0	83	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	86	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	62	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	7986717	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	8151	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	7986717	0	0
T1	464754	1440	0	0
T3	0	35844	0	0
T4	358111	18945	0	0
T5	196709	0	0	0
T6	0	1809	0	0
T7	0	1378	0	0
T8	0	19884	0	0
T10	0	117616	0	0
T11	0	682	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	24084	0	0
T44	0	11478	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	8151	0	0
T1	464754	1	0	0
T3	0	92	0	0
T4	358111	11	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	71	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	60	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	2051452	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	2010	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2051452	0	0
T1	464754	1428	0	0
T3	0	1568	0	0
T4	358111	15432	0	0
T5	196709	0	0	0
T6	0	2841	0	0
T7	0	3046	0	0
T8	0	19794	0	0
T10	0	20837	0	0
T11	0	666	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	2043	0	0
T31	0	1183	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2010	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	3	0	0
T7	0	9	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T31	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1960629	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1914	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1960629	0	0
T1	464754	1425	0	0
T3	0	1425	0	0
T4	358111	15426	0	0
T5	196709	0	0	0
T6	0	1801	0	0
T7	0	1292	0	0
T8	0	19716	0	0
T10	0	20717	0	0
T11	0	650	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1993	0	0
T44	0	11450	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1914	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1974135	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1942	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1974135	0	0
T1	464754	1415	0	0
T3	0	1293	0	0
T4	358111	15426	0	0
T5	196709	0	0	0
T6	0	1797	0	0
T7	0	1252	0	0
T8	0	19633	0	0
T10	0	20597	0	0
T11	0	634	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1943	0	0
T44	0	11436	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1942	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1938647	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1920	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1938647	0	0
T1	464754	1405	0	0
T3	0	1529	0	0
T4	358111	15426	0	0
T5	196709	0	0	0
T6	0	1793	0	0
T7	0	1217	0	0
T8	0	19545	0	0
T10	0	20477	0	0
T11	0	618	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1893	0	0
T44	0	11422	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1920	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	2043823	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	2022	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2043823	0	0
T1	464754	1401	0	0
T3	0	1541	0	0
T4	358111	15414	0	0
T5	196709	0	0	0
T6	0	2823	0	0
T7	0	2877	0	0
T8	0	19468	0	0
T10	0	20813	0	0
T11	0	602	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	2033	0	0
T31	0	1177	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	2022	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	3	0	0
T7	0	9	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T31	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1981880	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1959	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1981880	0	0
T1	464754	1394	0	0
T3	0	1408	0	0
T4	358111	15408	0	0
T5	196709	0	0	0
T6	0	1785	0	0
T7	0	1243	0	0
T8	0	19374	0	0
T10	0	20693	0	0
T11	0	586	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1983	0	0
T44	0	11394	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1959	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1954524	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1943	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1954524	0	0
T1	464754	1386	0	0
T3	0	1275	0	0
T4	358111	15408	0	0
T5	196709	0	0	0
T6	0	1781	0	0
T7	0	1206	0	0
T8	0	19291	0	0
T10	0	20573	0	0
T11	0	570	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1933	0	0
T44	0	11380	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1943	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T1,T4,T3
0	0	1	Covered	T1,T4,T3
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1922679	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1916	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1922679	0	0
T1	464754	1383	0	0
T3	0	1606	0	0
T4	358111	15408	0	0
T5	196709	0	0	0
T6	0	1777	0	0
T7	0	1463	0	0
T8	0	19198	0	0
T10	0	20453	0	0
T11	0	554	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	1883	0	0
T44	0	11366	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1916	0	0
T1	464754	1	0	0
T3	0	4	0	0
T4	358111	9	0	0
T5	196709	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T10	0	12	0	0
T11	0	8	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T30	0	5	0	0
T44	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T7,T23
1	1	Covered	T4,T7,T23

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T23
1	-	Covered	T4,T7,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Unreachable
1	0	Covered	T4,T7,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T23
1	1	Covered	T4,T7,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T23
0	0	1	Covered	T4,T7,T23
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T5
0	1	-	Covered	T4,T7,T23
0	0	1	Covered	T4,T7,T23
0	0	0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1368930239	1120263	0	0
DstReqKnown_A	6697089	5823451	0	0
SrcAckBusyChk_A	1368930239	1039	0	0
SrcBusyKnown_A	1368930239	1368458163	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1120263	0	0
T4	358111	6492	0	0
T5	196709	0	0	0
T7	0	1138	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	2849	0	0
T29	0	1553	0	0
T36	0	927	0	0
T48	60796	0	0	0
T51	0	1585	0	0
T52	0	3314	0	0
T53	0	1471	0	0
T54	0	3015	0	0
T66	0	6990	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6697089	5823451	0	0
T1	9484	5431	0	0
T4	7201	6801	0	0
T5	409	9	0	0
T13	527	127	0	0
T14	729	329	0	0
T15	502	102	0	0
T16	405	5	0	0
T17	436	36	0	0
T18	435	35	0	0
T19	633	233	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1039	0	0
T4	358111	4	0	0
T5	196709	0	0	0
T7	0	3	0	0
T13	50140	0	0	0
T14	91159	0	0	0
T15	246089	0	0	0
T16	68964	0	0	0
T17	43644	0	0	0
T18	108977	0	0	0
T19	300917	0	0	0
T23	0	2	0	0
T29	0	2	0	0
T36	0	2	0	0
T48	60796	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	4	0	0
T54	0	2	0	0
T66	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1368930239	1368458163	0	0
T1	464754	464419	0	0
T4	358111	358104	0	0
T5	196709	196632	0	0
T13	50140	50058	0	0
T14	91159	91079	0	0
T15	246089	245997	0	0
T16	68964	68888	0	0
T17	43644	43586	0	0
T18	108977	108882	0	0
T19	300917	300833	0	0