Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1858

1

T5

3

T1

8

T3

10

auto[1]

581

1

T5

1

T1

4

T3

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T5

3

T1

12

T3

10

auto[1]

555

1

T5

1

T3

2

T4

14

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1785

1

T5

4

T1

9

T3

10

auto[1]

654

1

T1

3

T3

2

T4

42

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1811

1

T5

3

T1

8

T3

12

auto[1]

628

1

T5

1

T1

4

T4

27

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2235

1

T5

4

T1

12

T3

12

auto[1]

204

1

T4

14

T43

4

T32

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2219

1

T5

4

T1

8

T3

12

auto[1]

220

1

T1

4

T4

13

T8

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2277

1

T5

3

T1

10

T3

10

auto[1]

162

1

T5

1

T1

2

T3

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2236

1

T5

4

T1

11

T3

10

auto[1]

203

1

T1

1

T3

2

T4

15

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2112

1

T5

3

T1

10

T3

10

auto[1]

327

1

T5

1

T1

2

T3

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1963

1

T5

4

T1

11

T3

10

auto[1]

476

1

T1

1

T3

2

T8

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	763	1			T16	10		T12	11		T33	18
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	64	1			T4	14		T43	2		T295	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	73	1			T72	3		T295	4		T307	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	17	1			T43	2		T245	2		T268	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	63	1			T32	10		T245	5		T169	10
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	39	1			T1	1		T3	2		T4	15
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	10	1			T353	4		T361	1		T362	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	43	1			T3	2		T348	9		T349	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	29	1			T295	4		T331	2		T281	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	8	1			T5	1		T245	2		T363	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T364	3		T365	3		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	9	1			T280	1		T296	1		T366	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T353	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T362	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	55	1			T1	2		T8	1		T169	11
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	30	1			T32	4		T331	2		T362	11
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	57	1			T4	13		T43	1		T295	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T360	5		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	9	1			T307	4		T367	2		T368	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T369	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	9	1			T307	4		T268	2		T370	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	10	1			T1	1		T32	3		T371	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	5	1			T279	4		T241	1		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T1	1		T360	2		T372	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T353	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

105

1

T32

1

T169

11

T280

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

95

1

T169

10

T258

9

T113

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T3

2

T12

5

T283

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

112

1

T1

1

T43

1

T32

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T16

6

T33

12

T214

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T295

4

T373

2

T268

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T1

1

T8

1

T118

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

110

1

T72

3

T32

4

T66

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

93

1

T1

1

T4

15

T33

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T311

1

T374

5

T351

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T258

3

T307

4

T375

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

74

1

T258

6

T295

2

T296

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T1

2

T4

13

T113

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

22

1

T66

1

T282

1

T281

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T187

4

T351

2

T376

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

89

1

T55

1

T245

5

T282

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T33

4

T245

2

T280

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T32

10

T66

5

T99

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T296

1

T324

1

T377

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T43

4

T182

2

T353

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T5

1

T347

2

T302

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T172

3

T117

3

T178

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T111

1

T300

2

T378

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

69

1

T3

2

T12

4

T172

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T107

2

T118

2

T121

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T16

3

T12

2

T374

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T117

2

T119

3

T376

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T4

14

T245

2

T100

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T100

1

T303

1

T354

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T16

1

T284

2

T307

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T324

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded