Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T7

9

T24

12

T70

11

auto[1]

1024

1

T7

11

T24

8

T70

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

481

1

T7

4

T24

6

T70

6

from_0to1

489

1

T7

4

T24

6

T70

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T7

9

T24

9

T70

9

auto[1]

1026

1

T7

11

T24

11

T70

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T7

11

T24

10

T70

14

auto[1]

1024

1

T7

9

T24

10

T70

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T24

1

T70

1

T53

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T24

1

T22

1

T40

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T24

1

T70

2

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T7

1

T24

1

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T24

1

T70

2

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T7

2

T24

1

T22

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T53

1

T71

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T24

2

T70

2

T53

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T7

1

T24

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T7

1

T40

1

T127

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T7

1

T24

1

T22

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T70

2

T40

2

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T70

1

T53

1

T40

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T7

1

T22

1

T197

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T7

1

T70

2

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T24

2

T53

1

T40

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T7

7

T24

11

T70

8

auto[1]

991

1

T7

13

T24

9

T70

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T7

5

T24

5

T70

3

from_0to1

496

1

T7

4

T24

5

T70

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T7

11

T24

11

T70

11

auto[1]

1003

1

T7

9

T24

9

T70

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T7

9

T24

10

T70

12

auto[1]

1019

1

T7

11

T24

10

T70

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T7

1

T24

2

T22

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T24

1

T53

1

T40

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T24

1

T70

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T7

1

T22

1

T197

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T53

1

T40

2

T20

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T7

1

T24

1

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T7

2

T40

2

T197

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T22

1

T71

2

T40

2

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T24

1

T71

2

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T7

1

T70

1

T40

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T7

1

T70

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T7

1

T53

1

T127

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T24

1

T22

1

T40

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T70

1

T53

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T7

1

T24

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T24

2

T53

2

T40

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T7

13

T24

10

T70

8

auto[1]

1054

1

T7

7

T24

10

T70

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

488

1

T7

4

T24

6

T70

4

from_0to1

482

1

T7

5

T24

5

T70

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T7

11

T24

9

T70

7

auto[1]

1055

1

T7

9

T24

11

T70

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1016

1

T7

12

T24

7

T70

11

auto[1]

1022

1

T7

8

T24

13

T70

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T7

1

T24

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T24

1

T127

1

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T7

1

T70

1

T71

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T70

1

T53

1

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T22

1

T71

1

T197

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T70

2

T53

2

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T7

1

T70

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T7

2

T24

2

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T53

2

T40

1

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T7

1

T24

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T7

1

T70

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T24

3

T70

1

T22

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T7

1

T24

1

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T24

1

T53

1

T127

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T7

1

T24

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T71

1

T40

3

T197

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T7

12

T24

15

T70

9

auto[1]

993

1

T7

8

T24

5

T70

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T7

6

T24

5

T70

4

from_0to1

502

1

T7

6

T24

4

T70

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T7

8

T24

12

T70

10

auto[1]

1000

1

T7

12

T24

8

T70

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T7

9

T24

11

T70

11

auto[1]

1053

1

T7

11

T24

9

T70

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T24

1

T70

1

T53

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T7

1

T24

2

T53

2

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T7

1

T70

1

T40

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T7

2

T24

2

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T7

1

T24

2

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T22

2

T71

1

T40

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T7

1

T70

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T24

1

T22

1

T71

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T22

1

T71

1

T127

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T70

1

T22

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T7

1

T70

1

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T7

1

T127

1

T197

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T40

1

T127

1

T197

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T7

1

T53

3

T197

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T7

1

T70

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T7

2

T24

1

T70

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T7

10

T24

7

T70

9

auto[1]

1047

1

T7

10

T24

13

T70

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

483

1

T7

4

T24

6

T70

4

from_0to1

484

1

T7

5

T24

6

T70

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

992

1

T7

7

T24

14

T70

10

auto[1]

1046

1

T7

13

T24

6

T70

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T7

15

T24

11

T70

7

auto[1]

988

1

T7

5

T24

9

T70

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T24

1

T22

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T24

1

T70

1

T40

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T7

2

T53

1

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T7

1

T22

1

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T7

1

T53

1

T127

3

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T22

1

T197

1

T198

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T24

1

T70

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T7

1

T24

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T24

2

T70

2

T53

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T7

1

T24

1

T127

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T24

1

T71

1

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T70

1

T53

2

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T7

1

T24

1

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T70

2

T53

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T24

3

T53

1

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T7

2

T70

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T7

10

T24

7

T70

11

auto[1]

972

1

T7

10

T24

13

T70

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

474

1

T7

7

T24

4

T70

3

from_0to1

477

1

T7

8

T24

4

T70

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T7

8

T24

9

T70

9

auto[1]

981

1

T7

12

T24

11

T70

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T7

9

T24

8

T70

6

auto[1]

1007

1

T7

11

T24

12

T70

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T7

2

T71

1

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T7

1

T24

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T7

1

T70

1

T53

3

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T7

1

T24

1

T22

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T7

1

T53

1

T22

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T7

1

T70

1

T22

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T24

1

T40

2

T127

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T7

2

T70

2

T40

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T71

1

T40

1

T127

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T24

1

T70

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T24

1

T71

2

T40

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T7

2

T53

1

T40

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T7

1

T70

1

T53

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T24

1

T53

2

T71

2

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T24

1

T22

1

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T7

3

T24

1

T53

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T7

12

T24

10

T70

9

auto[1]

976

1

T7

8

T24

10

T70

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

476

1

T7

8

T24

6

T70

6

from_0to1

483

1

T7

9

T24

5

T70

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T7

7

T24

11

T70

11

auto[1]

1045

1

T7

13

T24

9

T70

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1012

1

T7

9

T24

9

T70

13

auto[1]

1026

1

T7

11

T24

11

T70

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T7

1

T24

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T7

3

T24

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T24

1

T70

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T7

1

T24

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T53

1

T22

2

T71

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T7

2

T24

2

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T7

1

T22

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T7

1

T24

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T70

2

T71

1

T127

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T24

1

T70

1

T53

2

auto[1]

from_1to0

auto[1]

auto[0]

45

1

T7

1

T24

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T7

2

T22

1

T40

3

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T7

1

T70

1

T53

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T24

1

T70

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T7

2

T24

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T7

2

T40

3

T127

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T7

8

T24

9

T70

6

auto[1]

977

1

T7

12

T24

11

T70

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

482

1

T7

5

T24

4

T70

5

from_0to1

484

1

T7

6

T24

4

T70

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T7

8

T24

9

T70

10

auto[1]

1013

1

T7

12

T24

11

T70

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T7

9

T24

12

T70

12

auto[1]

998

1

T7

11

T24

8

T70

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T7

1

T127

2

T197

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T53

2

T40

2

T127

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T24

2

T70

1

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T22

1

T71

1

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T22

1

T71

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T24

1

T70

2

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T24

1

T53

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T53

1

T22

1

T127

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T70

1

T22

2

T40

4

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T7

1

T70

3

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T7

1

T24

1

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T7

2

T24

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T7

2

T40

2

T45

3

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T7

1

T24

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T7

1

T24

1

T70

2

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T7

2

T53

1

T40

1