Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117121

1

T5

266

T6

108

T7

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139627	1			T5	213		T6	3		T7	62
values[0x0]	65163	1			T5	271		T6	214		T7	23
values[0x1]	66076	1			T5	283		T6	210		T7	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124777	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146089

1

T5

339

T6

152

T7

61

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2719	1			T5	5		T6	19		T1	5
valid_sources[0x01]	905	1			T5	2		T6	3		T7	1
valid_sources[0x02]	1886	1			T5	3		T8	1		T16	1
valid_sources[0x03]	1304	1			T5	3		T8	6		T12	1
valid_sources[0x04]	912	1			T5	3		T8	2		T16	6
valid_sources[0x05]	859	1			T5	2		T1	5		T8	3
valid_sources[0x06]	888	1			T5	5		T1	1		T16	1
valid_sources[0x07]	1537	1			T5	1		T8	1		T16	1
valid_sources[0x08]	1007	1			T5	8		T6	23		T1	15
valid_sources[0x09]	738	1			T7	1		T1	5		T8	2
valid_sources[0x0a]	1133	1			T5	2		T7	4		T1	1
valid_sources[0x0b]	876	1			T5	4		T1	1		T8	3
valid_sources[0x0c]	860	1			T5	6		T1	9		T8	2
valid_sources[0x0d]	769	1			T5	2		T1	1		T2	20
valid_sources[0x0e]	1030	1			T5	4		T1	3		T8	20
valid_sources[0x0f]	896	1			T5	1		T8	10		T16	1
valid_sources[0x10]	1054	1			T5	3		T2	76		T8	3
valid_sources[0x11]	798	1			T5	6		T6	15		T1	3
valid_sources[0x12]	971	1			T5	4		T68	1		T33	2
valid_sources[0x13]	906	1			T5	3		T7	2		T1	5
valid_sources[0x14]	1059	1			T5	3		T1	11		T8	3
valid_sources[0x15]	787	1			T5	3		T1	1		T8	5
valid_sources[0x16]	791	1			T5	7		T6	13		T1	1
valid_sources[0x17]	865	1			T6	1		T1	6		T8	4
valid_sources[0x18]	911	1			T5	2		T7	2		T8	8
valid_sources[0x19]	1194	1			T5	3		T8	2		T16	2
valid_sources[0x1a]	1714	1			T5	1		T2	1		T12	1
valid_sources[0x1b]	943	1			T7	2		T1	3		T16	5
valid_sources[0x1c]	1665	1			T5	4		T1	1		T8	2
valid_sources[0x1d]	1146	1			T5	1		T7	1		T1	1
valid_sources[0x1e]	1615	1			T5	4		T1	1		T8	1
valid_sources[0x1f]	930	1			T5	4		T1	12		T8	8
valid_sources[0x20]	818	1			T6	4		T1	8		T8	3
valid_sources[0x21]	971	1			T5	3		T8	5		T16	5
valid_sources[0x22]	969	1			T5	4		T8	3		T16	2
valid_sources[0x23]	1156	1			T5	6		T1	5		T8	3
valid_sources[0x24]	812	1			T5	1		T8	4		T16	1
valid_sources[0x25]	2172	1			T5	6		T8	6		T16	7
valid_sources[0x26]	1035	1			T5	3		T6	5		T1	2
valid_sources[0x27]	842	1			T5	2		T6	23		T1	1
valid_sources[0x28]	952	1			T5	5		T7	2		T8	3
valid_sources[0x29]	910	1			T5	2		T6	17		T1	9
valid_sources[0x2a]	913	1			T7	1		T1	16		T8	1
valid_sources[0x2b]	1217	1			T5	6		T1	2		T8	2
valid_sources[0x2c]	1154	1			T5	4		T6	12		T7	1
valid_sources[0x2d]	809	1			T5	3		T7	1		T1	2
valid_sources[0x2e]	1048	1			T5	4		T1	8		T8	2
valid_sources[0x2f]	1025	1			T5	9		T1	4		T14	1
valid_sources[0x30]	893	1			T5	3		T7	1		T1	9
valid_sources[0x31]	1155	1			T5	2		T7	3		T1	1
valid_sources[0x32]	968	1			T5	1		T8	3		T16	3
valid_sources[0x33]	1113	1			T5	4		T1	1		T8	3
valid_sources[0x34]	1475	1			T5	2		T1	11		T8	1
valid_sources[0x35]	990	1			T5	5		T7	1		T1	10
valid_sources[0x36]	880	1			T5	3		T6	29		T7	2
valid_sources[0x37]	822	1			T5	5		T7	1		T1	1
valid_sources[0x38]	988	1			T5	1		T1	13		T33	8
valid_sources[0x39]	1069	1			T5	4		T1	10		T14	1
valid_sources[0x3a]	948	1			T5	4		T1	5		T8	4
valid_sources[0x3b]	859	1			T5	9		T1	5		T8	4
valid_sources[0x3c]	986	1			T5	1		T1	3		T8	1
valid_sources[0x3d]	796	1			T5	5		T7	3		T1	7
valid_sources[0x3e]	818	1			T5	2		T6	21		T1	17
valid_sources[0x3f]	1071	1			T5	4		T7	1		T1	4
valid_sources[0x40]	804	1			T5	2		T1	1		T8	5
valid_sources[0x41]	947	1			T5	2		T6	7		T1	12
valid_sources[0x42]	949	1			T5	1		T1	1		T8	1
valid_sources[0x43]	788	1			T5	3		T7	3		T1	6
valid_sources[0x44]	833	1			T5	2		T1	10		T8	6
valid_sources[0x45]	849	1			T5	7		T7	1		T1	6
valid_sources[0x46]	843	1			T5	4		T1	2		T8	3
valid_sources[0x47]	839	1			T5	3		T1	12		T8	9
valid_sources[0x48]	711	1			T5	3		T1	4		T8	6
valid_sources[0x49]	1027	1			T5	2		T1	2		T8	1
valid_sources[0x4a]	1682	1			T5	2		T1	5		T2	20
valid_sources[0x4b]	1346	1			T5	5		T1	5		T8	1
valid_sources[0x4c]	1161	1			T5	1		T1	4		T8	3
valid_sources[0x4d]	1430	1			T5	2		T7	3		T1	1
valid_sources[0x4e]	1123	1			T5	4		T7	2		T1	9
valid_sources[0x4f]	2134	1			T5	3		T1	12		T16	3
valid_sources[0x50]	805	1			T5	1		T6	2		T1	11
valid_sources[0x51]	1220	1			T5	1		T7	1		T1	4
valid_sources[0x52]	930	1			T5	1		T1	5		T8	4
valid_sources[0x53]	943	1			T5	4		T7	1		T8	4
valid_sources[0x54]	873	1			T5	1		T1	2		T9	1
valid_sources[0x55]	837	1			T5	4		T1	3		T8	1
valid_sources[0x56]	1408	1			T5	3		T6	3		T1	4
valid_sources[0x57]	864	1			T5	2		T2	20		T8	1
valid_sources[0x58]	952	1			T5	1		T7	1		T1	1
valid_sources[0x59]	788	1			T1	3		T8	1		T16	3
valid_sources[0x5a]	1117	1			T5	1		T1	3		T8	8
valid_sources[0x5b]	976	1			T5	4		T8	2		T12	1
valid_sources[0x5c]	1381	1			T5	2		T6	4		T7	2
valid_sources[0x5d]	1173	1			T5	3		T7	1		T16	6
valid_sources[0x5e]	887	1			T5	7		T7	2		T1	4
valid_sources[0x5f]	875	1			T5	3		T1	7		T2	20
valid_sources[0x60]	1978	1			T5	4		T1	1		T8	5
valid_sources[0x61]	1509	1			T5	4		T6	11		T1	10
valid_sources[0x62]	1674	1			T5	3		T6	6		T1	3
valid_sources[0x63]	727	1			T7	6		T1	3		T8	5
valid_sources[0x64]	858	1			T5	4		T1	9		T8	1
valid_sources[0x65]	800	1			T5	1		T7	1		T1	4
valid_sources[0x66]	847	1			T5	2		T8	3		T12	1
valid_sources[0x67]	1674	1			T5	1		T8	4		T16	2
valid_sources[0x68]	825	1			T5	2		T7	4		T1	5
valid_sources[0x69]	1129	1			T5	4		T1	7		T8	3
valid_sources[0x6a]	903	1			T5	1		T1	3		T8	5
valid_sources[0x6b]	1553	1			T5	2		T8	4		T16	1
valid_sources[0x6c]	1179	1			T5	1		T1	2		T8	2
valid_sources[0x6d]	907	1			T1	4		T8	1		T16	2
valid_sources[0x6e]	756	1			T5	2		T1	4		T8	4
valid_sources[0x6f]	1017	1			T5	6		T1	6		T8	3
valid_sources[0x70]	884	1			T5	4		T7	1		T1	1
valid_sources[0x71]	1100	1			T5	3		T1	3		T8	4
valid_sources[0x72]	910	1			T5	2		T7	1		T1	3
valid_sources[0x73]	891	1			T5	7		T1	8		T8	3
valid_sources[0x74]	840	1			T5	6		T1	1		T8	3
valid_sources[0x75]	946	1			T5	5		T1	13		T2	1
valid_sources[0x76]	1203	1			T5	1		T1	1		T16	4
valid_sources[0x77]	2020	1			T1	4		T8	4		T12	5
valid_sources[0x78]	1050	1			T5	1		T6	22		T1	1
valid_sources[0x79]	1124	1			T5	4		T7	1		T1	5
valid_sources[0x7a]	846	1			T5	4		T1	6		T2	20
valid_sources[0x7b]	953	1			T5	4		T1	1		T8	13
valid_sources[0x7c]	1062	1			T5	3		T1	9		T2	20
valid_sources[0x7d]	700	1			T5	4		T1	4		T8	5
valid_sources[0x7e]	1137	1			T5	1		T1	4		T16	2
valid_sources[0x7f]	1150	1			T14	2		T12	3		T13	2
valid_sources[0x80]	892	1			T5	3		T2	2		T16	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63390

1

T5

112

T7

30

T1

177

values[0x0]

all_enables

biggest_size

31510

1

T5

97

T6

72

T7

8

values[0x1]

all_enables

biggest_size

22221

1

T5

57

T6

36

T7

8