Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T25,T26,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T25,T26,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T25,T26,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T22
1	0	Covered	T5,T6,T7
1	1	Covered	T25,T26,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T22
0	1	Covered	T120,T125
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T22
0	1	Covered	T25,T26,T22
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T26,T22
1	-	Covered	T25,T26,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T22
DetectSt	168	Covered	T25,T26,T22
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T25,T26,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T22
DebounceSt->IdleSt	163	Covered	T46,T139,T140
DetectSt->IdleSt	186	Covered	T120,T125
DetectSt->StableSt	191	Covered	T25,T26,T22
IdleSt->DebounceSt	148	Covered	T25,T26,T22
StableSt->IdleSt	206	Covered	T25,T26,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T22
0	1	Covered	T25,T26,T22
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T22
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T22
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T139,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T22
DetectSt	-	-	-	-	1	-	-	Covered	T120,T125
DetectSt	-	-	-	-	0	1	-	Covered	T25,T26,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T26,T22
StableSt	-	-	-	-	-	-	0	Covered	T25,T26,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	306	0	0
CntIncr_A	7644258	259747	0	0
CntNoWrap_A	7644258	6941512	0	0
DetectStDropOut_A	7644258	2	0	0
DetectedOut_A	7644258	926	0	0
DetectedPulseOut_A	7644258	139	0	0
DisabledIdleSt_A	7644258	6674899	0	0
DisabledNoDetection_A	7644258	6677255	0	0
EnterDebounceSt_A	7644258	169	0	0
EnterDetectSt_A	7644258	141	0	0
EnterStableSt_A	7644258	139	0	0
PulseIsPulse_A	7644258	139	0	0
StayInStableSt	7644258	787	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	7150	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	138	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	306	0	0
T21	489	0	0	0
T22	0	4	0	0
T25	827	4	0	0
T26	598	4	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	259747	0	0
T21	489	0	0	0
T22	0	161	0	0
T25	827	192	0	0
T26	598	73	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	52	0	0
T41	0	134	0	0
T44	0	75	0	0
T45	0	78	0	0
T46	0	117	0	0
T47	0	97	0	0
T48	0	42	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941512	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2	0	0
T80	8418	0	0	0
T120	768	1	0	0
T121	10511	0	0	0
T125	0	1	0	0
T130	843	0	0	0
T131	1503	0	0	0
T132	491	0	0	0
T133	4402	0	0	0
T134	491	0	0	0
T135	29298	0	0	0
T136	15634	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	926	0	0
T21	489	0	0	0
T22	0	13	0	0
T25	827	10	0	0
T26	598	6	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	2	0	0
T41	0	11	0	0
T44	0	6	0	0
T45	0	8	0	0
T46	0	6	0	0
T47	0	13	0	0
T48	0	12	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	139	0	0
T21	489	0	0	0
T22	0	2	0	0
T25	827	2	0	0
T26	598	2	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6674899	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6677255	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	169	0	0
T21	489	0	0	0
T22	0	2	0	0
T25	827	2	0	0
T26	598	2	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	141	0	0
T21	489	0	0	0
T22	0	2	0	0
T25	827	2	0	0
T26	598	2	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	139	0	0
T21	489	0	0	0
T22	0	2	0	0
T25	827	2	0	0
T26	598	2	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	139	0	0
T21	489	0	0	0
T22	0	2	0	0
T25	827	2	0	0
T26	598	2	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	787	0	0
T21	489	0	0	0
T22	0	11	0	0
T25	827	8	0	0
T26	598	4	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	9	0	0
T44	0	5	0	0
T45	0	7	0	0
T46	0	5	0	0
T47	0	11	0	0
T48	0	11	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	7150	0	0
T1	13845	27	0	0
T2	5524	7	0	0
T3	10725	37	0	0
T4	32180	33	0	0
T5	8381	31	0	0
T6	5169	32	0	0
T7	502	6	0	0
T8	11331	28	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	0	3	0	0
T16	0	13	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	138	0	0
T21	489	0	0	0
T22	0	2	0	0
T25	827	2	0	0
T26	598	2	0	0
T32	28843	0	0	0
T36	669	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	459	0	0	0
T50	426	0	0	0
T51	4402	0	0	0
T52	10643	0	0	0
T53	163311	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T10,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T10,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T10,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T10,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T20
0	1	Covered	T75,T106,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T20
0	1	Unreachable
1	0	Covered	T2,T10,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T20
DetectSt	168	Covered	T2,T10,T20
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T10,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T20
DebounceSt->IdleSt	163	Covered	T45,T73,T75
DetectSt->IdleSt	186	Covered	T75,T106,T107
DetectSt->StableSt	191	Covered	T2,T10,T20
IdleSt->DebounceSt	148	Covered	T2,T10,T20
StableSt->IdleSt	206	Covered	T2,T10,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T20
0	1	Covered	T2,T10,T20
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T20
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T20
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T73,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T20
DetectSt	-	-	-	-	1	-	-	Covered	T75,T106,T107
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T20
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	172	0	0
CntIncr_A	7644258	203660	0	0
CntNoWrap_A	7644258	6941646	0	0
DetectStDropOut_A	7644258	16	0	0
DetectedOut_A	7644258	32331	0	0
DetectedPulseOut_A	7644258	54	0	0
DisabledIdleSt_A	7644258	5706409	0	0
DisabledNoDetection_A	7644258	5708826	0	0
EnterDebounceSt_A	7644258	102	0	0
EnterDetectSt_A	7644258	70	0	0
EnterStableSt_A	7644258	54	0	0
PulseIsPulse_A	7644258	54	0	0
StayInStableSt	7644258	32277	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	7150	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_sticky_sva.StableStDropOut_A	7644258	737890	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	172	0	0
T2	5524	2	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T35	0	4	0	0
T41	0	2	0	0
T45	0	3	0	0
T58	0	2	0	0
T59	423	0	0	0
T73	0	6	0	0
T74	0	2	0	0
T75	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	203660	0	0
T2	5524	77	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	86	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	24	0	0
T35	0	134	0	0
T41	0	18	0	0
T45	0	21832	0	0
T58	0	36	0	0
T59	423	0	0	0
T73	0	264	0	0
T74	0	92	0	0
T75	0	152	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941646	0	0
T1	13845	13438	0	0
T2	5524	605	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	16	0	0
T75	13558	1	0	0
T106	0	3	0	0
T107	0	1	0	0
T125	0	1	0	0
T141	0	2	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	904	0	0	0
T148	495	0	0	0
T149	753	0	0	0
T150	496	0	0	0
T151	522	0	0	0
T152	486	0	0	0
T153	422	0	0	0
T154	404	0	0	0
T155	537	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	32331	0	0
T2	5524	37	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	429	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	59	0	0
T35	0	789	0	0
T41	0	58	0	0
T45	0	176	0	0
T58	0	10	0	0
T59	423	0	0	0
T74	0	379	0	0
T75	0	281	0	0
T137	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	54	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5706409	0	0
T1	13845	13438	0	0
T2	5524	452	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5708826	0	0
T1	13845	13442	0	0
T2	5524	465	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	102	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T73	0	6	0	0
T74	0	1	0	0
T75	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	70	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	3	0	0
T137	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	54	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	54	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	32277	0	0
T2	5524	36	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	427	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	58	0	0
T35	0	787	0	0
T41	0	57	0	0
T45	0	175	0	0
T58	0	9	0	0
T59	423	0	0	0
T74	0	378	0	0
T75	0	279	0	0
T137	0	97	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	7150	0	0
T1	13845	27	0	0
T2	5524	7	0	0
T3	10725	37	0	0
T4	32180	33	0	0
T5	8381	31	0	0
T6	5169	32	0	0
T7	502	6	0	0
T8	11331	28	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	0	3	0	0
T16	0	13	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	737890	0	0
T2	5524	26	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	442	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	139	0	0
T35	0	310	0	0
T41	0	300	0	0
T45	0	67	0	0
T58	0	26	0	0
T59	423	0	0	0
T74	0	53	0	0
T75	0	707	0	0
T137	0	730	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T2,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T2,T15
1	1	Covered	T7,T2,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T10,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T10,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T10,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T20
1	0	Covered	T7,T2,T15
1	1	Covered	T2,T10,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T45
0	1	Covered	T2,T20,T35
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T45
0	1	Unreachable
1	0	Covered	T10,T41,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T20
DetectSt	168	Covered	T2,T10,T20
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T41,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T20
DebounceSt->IdleSt	163	Covered	T75,T156,T157
DetectSt->IdleSt	186	Covered	T2,T20,T35
DetectSt->StableSt	191	Covered	T10,T41,T45
IdleSt->DebounceSt	148	Covered	T2,T10,T20
StableSt->IdleSt	206	Covered	T10,T41,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T20
0	1	Covered	T2,T10,T20
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T20
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T20
IdleSt	0	-	-	-	-	-	-	Covered	T7,T2,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T156,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T20
DetectSt	-	-	-	-	1	-	-	Covered	T2,T20,T35
DetectSt	-	-	-	-	0	1	-	Covered	T10,T41,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T45
StableSt	-	-	-	-	-	-	0	Covered	T10,T41,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	174	0	0
CntIncr_A	7644258	6426	0	0
CntNoWrap_A	7644258	6941644	0	0
DetectStDropOut_A	7644258	16	0	0
DetectedOut_A	7644258	8267	0	0
DetectedPulseOut_A	7644258	47	0	0
DisabledIdleSt_A	7644258	5706409	0	0
DisabledNoDetection_A	7644258	5708826	0	0
EnterDebounceSt_A	7644258	111	0	0
EnterDetectSt_A	7644258	63	0	0
EnterStableSt_A	7644258	47	0	0
PulseIsPulse_A	7644258	47	0	0
StayInStableSt	7644258	8220	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_sticky_sva.StableStDropOut_A	7644258	829387	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	174	0	0
T2	5524	2	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	4	0	0
T35	0	10	0	0
T41	0	2	0	0
T45	0	4	0	0
T58	0	2	0	0
T59	423	0	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6426	0	0
T2	5524	50	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	110	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	164	0	0
T35	0	272	0	0
T41	0	52	0	0
T45	0	94	0	0
T58	0	33	0	0
T59	423	0	0	0
T73	0	106	0	0
T74	0	15	0	0
T75	0	460	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941644	0	0
T1	13845	13438	0	0
T2	5524	605	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	16	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T35	0	3	0	0
T59	423	0	0	0
T125	0	1	0	0
T143	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	8267	0	0
T10	1440	520	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T24	502	0	0	0
T33	23744	0	0	0
T35	0	239	0	0
T41	0	250	0	0
T45	0	126	0	0
T58	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T73	0	503	0	0
T74	0	56	0	0
T75	0	398	0	0
T79	8487	0	0	0
T137	0	535	0	0
T138	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47	0	0
T10	1440	2	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T24	502	0	0	0
T33	23744	0	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T79	8487	0	0	0
T137	0	2	0	0
T138	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5706409	0	0
T1	13845	13438	0	0
T2	5524	452	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5708826	0	0
T1	13845	13442	0	0
T2	5524	465	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	111	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T35	0	5	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	63	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T35	0	5	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47	0	0
T10	1440	2	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T24	502	0	0	0
T33	23744	0	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T79	8487	0	0	0
T137	0	2	0	0
T138	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47	0	0
T10	1440	2	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T24	502	0	0	0
T33	23744	0	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T79	8487	0	0	0
T137	0	2	0	0
T138	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	8220	0	0
T10	1440	518	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T24	502	0	0	0
T33	23744	0	0	0
T35	0	237	0	0
T41	0	249	0	0
T45	0	124	0	0
T59	423	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T73	0	501	0	0
T74	0	55	0	0
T75	0	397	0	0
T79	8487	0	0	0
T104	0	202	0	0
T137	0	533	0	0
T138	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	829387	0	0
T10	1440	329	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T24	502	0	0	0
T33	23744	0	0	0
T35	0	423	0	0
T41	0	80	0	0
T45	0	58737	0	0
T58	0	51	0	0
T59	423	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T73	0	342	0	0
T74	0	450	0	0
T75	0	58	0	0
T79	8487	0	0	0
T137	0	145	0	0
T138	0	172	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T10,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T10,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T20,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T10,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T41
0	1	Covered	T45,T73,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T20,T41
0	1	Unreachable
1	0	Covered	T2,T20,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T20
DetectSt	168	Covered	T2,T20,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T20,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T20,T41
DebounceSt->IdleSt	163	Covered	T10,T73,T104
DetectSt->IdleSt	186	Covered	T45,T73,T104
DetectSt->StableSt	191	Covered	T2,T20,T41
IdleSt->DebounceSt	148	Covered	T2,T10,T20
StableSt->IdleSt	206	Covered	T2,T20,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T20
0	1	Covered	T2,T10,T20
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T20
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T20,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T73,T104
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T20
DetectSt	-	-	-	-	1	-	-	Covered	T45,T73,T104
DetectSt	-	-	-	-	0	1	-	Covered	T2,T20,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T20,T41
StableSt	-	-	-	-	-	-	0	Covered	T2,T20,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	176	0	0
CntIncr_A	7644258	477896	0	0
CntNoWrap_A	7644258	6941642	0	0
DetectStDropOut_A	7644258	17	0	0
DetectedOut_A	7644258	543532	0	0
DetectedPulseOut_A	7644258	46	0	0
DisabledIdleSt_A	7644258	5706409	0	0
DisabledNoDetection_A	7644258	5708826	0	0
EnterDebounceSt_A	7644258	113	0	0
EnterDetectSt_A	7644258	63	0	0
EnterStableSt_A	7644258	46	0	0
PulseIsPulse_A	7644258	46	0	0
StayInStableSt	7644258	543486	0	0
gen_high_event_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_sticky_sva.StableStDropOut_A	7644258	209284	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	176	0	0
T2	5524	2	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	7	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T35	0	4	0	0
T41	0	2	0	0
T45	0	4	0	0
T58	0	2	0	0
T59	423	0	0	0
T73	0	10	0	0
T74	0	2	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	477896	0	0
T2	5524	56	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	588	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	27	0	0
T35	0	172	0	0
T41	0	22	0	0
T45	0	58684	0	0
T58	0	32	0	0
T59	423	0	0	0
T73	0	558	0	0
T74	0	31	0	0
T75	0	158	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941642	0	0
T1	13845	13438	0	0
T2	5524	605	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	17	0	0
T45	70285	1	0	0
T46	656	0	0	0
T47	7927	0	0	0
T58	525	0	0	0
T73	0	4	0	0
T100	11940	0	0	0
T101	4615	0	0	0
T104	0	3	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	34059	0	0	0
T170	523	0	0	0
T171	528	0	0	0
T172	25186	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	543532	0	0
T2	5524	32	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	59	0	0
T35	0	884	0	0
T41	0	106	0	0
T45	0	170	0	0
T58	0	29	0	0
T59	423	0	0	0
T74	0	70	0	0
T75	0	872	0	0
T137	0	357	0	0
T138	0	96	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	46	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5706409	0	0
T1	13845	13438	0	0
T2	5524	452	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5708826	0	0
T1	13845	13442	0	0
T2	5524	465	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	113	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	7	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T73	0	6	0	0
T74	0	1	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	63	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T58	0	1	0	0
T59	423	0	0	0
T73	0	4	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	46	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	46	0	0
T2	5524	1	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T35	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T59	423	0	0	0
T74	0	1	0	0
T75	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	543486	0	0
T2	5524	31	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	58	0	0
T35	0	882	0	0
T41	0	105	0	0
T45	0	169	0	0
T58	0	28	0	0
T59	423	0	0	0
T74	0	69	0	0
T75	0	870	0	0
T137	0	355	0	0
T138	0	94	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	209284	0	0
T2	5524	61	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	145	0	0
T35	0	198	0	0
T41	0	257	0	0
T45	0	84	0	0
T58	0	26	0	0
T59	423	0	0	0
T74	0	425	0	0
T75	0	607	0	0
T137	0	416	0	0
T138	0	53	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T36,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T11,T36,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T36,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T36,T22
1	0	Covered	T5,T6,T7
1	1	Covered	T11,T36,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T40
0	1	Covered	T45
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T40
0	1	Covered	T40,T41,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T36,T40
1	-	Covered	T40,T41,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T36,T40
DetectSt	168	Covered	T11,T36,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T36,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T36,T40
DebounceSt->IdleSt	163	Covered	T102,T165,T173
DetectSt->IdleSt	186	Covered	T45,T54
DetectSt->StableSt	191	Covered	T11,T36,T40
IdleSt->DebounceSt	148	Covered	T11,T36,T40
StableSt->IdleSt	206	Covered	T40,T41,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T36,T40
0	1	Covered	T11,T36,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T36,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T36,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T36,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T173
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T36,T40
DetectSt	-	-	-	-	1	-	-	Covered	T45,T54
DetectSt	-	-	-	-	0	1	-	Covered	T11,T36,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T41,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T36,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	98	0	0
CntIncr_A	7644258	63685	0	0
CntNoWrap_A	7644258	6941720	0	0
DetectStDropOut_A	7644258	1	0	0
DetectedOut_A	7644258	3182	0	0
DetectedPulseOut_A	7644258	46	0	0
DisabledIdleSt_A	7644258	6594536	0	0
DisabledNoDetection_A	7644258	6596887	0	0
EnterDebounceSt_A	7644258	51	0	0
EnterDetectSt_A	7644258	48	0	0
EnterStableSt_A	7644258	46	0	0
PulseIsPulse_A	7644258	46	0	0
StayInStableSt	7644258	3114	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	98	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T43	11907	0	0	0
T45	0	6	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	2	0	0
T174	0	2	0	0
T175	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	63685	0	0
T11	545	12	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	82	0	0
T36	0	32	0	0
T38	0	38783	0	0
T40	0	80	0	0
T41	0	108	0	0
T43	11907	0	0	0
T45	0	202	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	77	0	0
T174	0	71	0	0
T175	0	130	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941720	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1	0	0
T45	70285	1	0	0
T46	656	0	0	0
T47	7927	0	0	0
T58	525	0	0	0
T100	11940	0	0	0
T101	4615	0	0	0
T169	34059	0	0	0
T170	523	0	0	0
T171	528	0	0	0
T172	25186	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3182	0	0
T11	545	40	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	111	0	0
T36	0	41	0	0
T38	0	42	0	0
T40	0	15	0	0
T41	0	83	0	0
T43	11907	0	0	0
T45	0	118	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	44	0	0
T174	0	39	0	0
T175	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	46	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T174	0	1	0	0
T175	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6594536	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6596887	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	51	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	11907	0	0	0
T45	0	3	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T174	0	1	0	0
T175	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	48	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	11907	0	0	0
T45	0	3	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T174	0	1	0	0
T175	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	46	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T174	0	1	0	0
T175	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	46	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T174	0	1	0	0
T175	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3114	0	0
T11	545	38	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	110	0	0
T36	0	39	0	0
T38	0	40	0	0
T40	0	14	0	0
T41	0	80	0	0
T43	11907	0	0	0
T45	0	116	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	42	0	0
T174	0	38	0	0
T175	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	24	0	0
T35	0	1	0	0
T37	999	0	0	0
T38	161391	0	0	0
T40	3782	1	0	0
T41	0	1	0	0
T44	720	0	0	0
T45	0	2	0	0
T90	416	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T129	424	0	0	0
T163	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T179	422	0	0	0
T180	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T22,T38,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T22,T38,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T22,T38,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T38,T37
1	0	Covered	T5,T7,T1
1	1	Covered	T22,T38,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T38,T37
0	1	Covered	T103,T181,T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T38,T37
0	1	Covered	T38,T37,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T38,T37
1	-	Covered	T38,T37,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T38,T37
DetectSt	168	Covered	T22,T38,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T22,T38,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T38,T37
DebounceSt->IdleSt	163	Covered	T41,T45,T182
DetectSt->IdleSt	186	Covered	T103,T181,T161
DetectSt->StableSt	191	Covered	T22,T38,T37
IdleSt->DebounceSt	148	Covered	T22,T38,T37
StableSt->IdleSt	206	Covered	T22,T38,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T38,T37
0	1	Covered	T22,T38,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T38,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T38,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T38,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T107,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T38,T37
DetectSt	-	-	-	-	1	-	-	Covered	T103,T181,T161
DetectSt	-	-	-	-	0	1	-	Covered	T22,T38,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T37,T41
StableSt	-	-	-	-	-	-	0	Covered	T22,T38,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	156	0	0
CntIncr_A	7644258	88585	0	0
CntNoWrap_A	7644258	6941662	0	0
DetectStDropOut_A	7644258	5	0	0
DetectedOut_A	7644258	93400	0	0
DetectedPulseOut_A	7644258	70	0	0
DisabledIdleSt_A	7644258	6593377	0	0
DisabledNoDetection_A	7644258	6595731	0	0
EnterDebounceSt_A	7644258	83	0	0
EnterDetectSt_A	7644258	75	0	0
EnterStableSt_A	7644258	70	0	0
PulseIsPulse_A	7644258	70	0	0
StayInStableSt	7644258	93300	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	2794	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	156	0	0
T22	19852	4	0	0
T23	495	0	0	0
T35	0	4	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	3782	0	0	0
T41	0	3	0	0
T45	0	4	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	4	0	0
T99	26116	0	0	0
T103	0	2	0	0
T105	0	2	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	88585	0	0
T22	19852	112	0	0
T23	495	0	0	0
T35	0	164	0	0
T37	0	60	0	0
T38	0	38783	0	0
T40	3782	0	0	0
T41	0	108	0	0
T45	0	150	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	143	0	0
T99	26116	0	0	0
T103	0	77	0	0
T105	0	93	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941662	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5	0	0
T103	609	1	0	0
T161	0	1	0	0
T181	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	403	0	0	0
T187	25959	0	0	0
T188	423	0	0	0
T189	8021	0	0	0
T190	504	0	0	0
T191	426	0	0	0
T192	412	0	0	0
T193	3285	0	0	0
T194	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	93400	0	0
T22	19852	379	0	0
T23	495	0	0	0
T35	0	71	0	0
T37	0	214	0	0
T38	0	32184	0	0
T40	3782	0	0	0
T41	0	33	0	0
T45	0	180	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	184	0	0
T99	26116	0	0	0
T105	0	266	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	617	0	0
T187	0	156	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	70	0	0
T22	19852	2	0	0
T23	495	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3782	0	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	2	0	0
T99	26116	0	0	0
T105	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6593377	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6595731	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	83	0	0
T22	19852	2	0	0
T23	495	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3782	0	0	0
T41	0	2	0	0
T45	0	3	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	2	0	0
T99	26116	0	0	0
T103	0	1	0	0
T105	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	75	0	0
T22	19852	2	0	0
T23	495	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3782	0	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	2	0	0
T99	26116	0	0	0
T103	0	1	0	0
T105	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	70	0	0
T22	19852	2	0	0
T23	495	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3782	0	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	2	0	0
T99	26116	0	0	0
T105	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	70	0	0
T22	19852	2	0	0
T23	495	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	3782	0	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	2	0	0
T99	26116	0	0	0
T105	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	93300	0	0
T22	19852	375	0	0
T23	495	0	0	0
T35	0	68	0	0
T37	0	213	0	0
T38	0	32183	0	0
T40	3782	0	0	0
T41	0	32	0	0
T45	0	178	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	180	0	0
T99	26116	0	0	0
T105	0	264	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T183	0	615	0	0
T187	0	154	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2794	0	0
T1	13845	0	0	0
T2	5524	7	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T7	502	7	0	0
T8	11331	0	0	0
T9	573	1	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	403	0	0	0
T15	427	3	0	0
T16	13925	0	0	0
T24	0	5	0	0
T68	0	4	0	0
T69	0	4	0	0
T86	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	40	0	0
T20	4585	0	0	0
T35	0	1	0	0
T37	999	1	0	0
T38	161391	1	0	0
T41	0	1	0	0
T44	720	0	0	0
T45	0	2	0	0
T90	416	0	0	0
T106	0	1	0	0
T163	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0
T179	422	0	0	0
T180	522	0	0	0
T195	0	1	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0