Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T11,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T42
1	0	Covered	T5,T6,T7
1	1	Covered	T9,T11,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T42
0	1	Covered	T161
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T42
0	1	Covered	T11,T37,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T42
1	-	Covered	T11,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T42
DetectSt	168	Covered	T9,T11,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T11,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T42
DebounceSt->IdleSt	163	Covered	T102,T199,T200
DetectSt->IdleSt	186	Covered	T161,T54
DetectSt->StableSt	191	Covered	T9,T11,T42
IdleSt->DebounceSt	148	Covered	T9,T11,T42
StableSt->IdleSt	206	Covered	T11,T40,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T42
0	1	Covered	T9,T11,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T199,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T42
DetectSt	-	-	-	-	1	-	-	Covered	T161,T54
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	91	0	0
CntIncr_A	7644258	41410	0	0
CntNoWrap_A	7644258	6941727	0	0
DetectStDropOut_A	7644258	1	0	0
DetectedOut_A	7644258	35347	0	0
DetectedPulseOut_A	7644258	42	0	0
DisabledIdleSt_A	7644258	6759850	0	0
DisabledNoDetection_A	7644258	6762202	0	0
EnterDebounceSt_A	7644258	47	0	0
EnterDetectSt_A	7644258	44	0	0
EnterStableSt_A	7644258	42	0	0
PulseIsPulse_A	7644258	42	0	0
StayInStableSt	7644258	35282	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	91	0	0
T9	573	2	0	0
T10	1440	0	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	41410	0	0
T9	573	86	0	0
T10	1440	0	0	0
T11	545	12	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	19	0	0
T36	0	32	0	0
T37	0	120	0	0
T38	0	38783	0	0
T40	0	80	0	0
T42	0	100	0	0
T45	0	64	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941727	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	170	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1	0	0
T161	11675	1	0	0
T201	525	0	0	0
T202	422	0	0	0
T203	26409	0	0	0
T204	504	0	0	0
T205	403	0	0	0
T206	1027	0	0	0
T207	13626	0	0	0
T208	3426	0	0	0
T209	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	35347	0	0
T9	573	41	0	0
T10	1440	0	0	0
T11	545	43	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	43	0	0
T36	0	178	0	0
T37	0	46	0	0
T38	0	32187	0	0
T40	0	43	0	0
T42	0	42	0	0
T45	0	188	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6759850	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	3	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6762202	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	3	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	44	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	35282	0	0
T9	573	39	0	0
T10	1440	0	0	0
T11	545	42	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	42	0	0
T36	0	176	0	0
T37	0	43	0	0
T38	0	32185	0	0
T40	0	41	0	0
T42	0	40	0	0
T45	0	186	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	19	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T144	0	1	0	0
T158	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T195	0	1	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T11,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T11,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T13,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T13
1	0	Covered	T5,T7,T1
1	1	Covered	T9,T11,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T42
0	1	Covered	T34,T75,T211
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T42
0	1	Covered	T11,T13,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T13,T42
1	-	Covered	T11,T13,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T13
DetectSt	168	Covered	T11,T13,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T13,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T13,T42
DebounceSt->IdleSt	163	Covered	T9,T183,T212
DetectSt->IdleSt	186	Covered	T34,T75,T211
DetectSt->StableSt	191	Covered	T11,T13,T42
IdleSt->DebounceSt	148	Covered	T9,T11,T13
StableSt->IdleSt	206	Covered	T11,T13,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T13
0	1	Covered	T9,T11,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T13,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T183,T212
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T13
DetectSt	-	-	-	-	1	-	-	Covered	T34,T75,T211
DetectSt	-	-	-	-	0	1	-	Covered	T11,T13,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T13,T42
StableSt	-	-	-	-	-	-	0	Covered	T11,T13,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	144	0	0
CntIncr_A	7644258	74880	0	0
CntNoWrap_A	7644258	6941674	0	0
DetectStDropOut_A	7644258	4	0	0
DetectedOut_A	7644258	160388	0	0
DetectedPulseOut_A	7644258	64	0	0
DisabledIdleSt_A	7644258	6666190	0	0
DisabledNoDetection_A	7644258	6668552	0	0
EnterDebounceSt_A	7644258	77	0	0
EnterDetectSt_A	7644258	69	0	0
EnterStableSt_A	7644258	64	0	0
PulseIsPulse_A	7644258	64	0	0
StayInStableSt	7644258	160296	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	3159	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	144	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	4	0	0
T12	21029	0	0	0
T13	793	4	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	4	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	74880	0	0
T9	573	86	0	0
T10	1440	0	0	0
T11	545	24	0	0
T12	21029	0	0	0
T13	793	140	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	38	0	0
T36	0	32	0	0
T37	0	120	0	0
T39	0	36	0	0
T40	0	37	0	0
T42	0	100	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941674	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	171	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	4	0	0
T34	679	1	0	0
T75	0	1	0	0
T140	2103	0	0	0
T211	0	1	0	0
T213	0	1	0	0
T214	19474	0	0	0
T215	44319	0	0	0
T216	495	0	0	0
T217	406	0	0	0
T218	55026	0	0	0
T219	649	0	0	0
T220	491	0	0	0
T221	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	160388	0	0
T11	545	54	0	0
T12	21029	0	0	0
T13	793	56	0	0
T33	23744	0	0	0
T34	0	74	0	0
T36	0	17	0	0
T37	0	301	0	0
T39	0	109	0	0
T40	0	185	0	0
T42	0	55	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	149	0	0
T183	0	235	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	64	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	2	0	0
T33	23744	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T183	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6666190	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	3	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6668552	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	3	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	77	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T24	502	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	69	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	2	0	0
T33	23744	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T183	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	64	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	2	0	0
T33	23744	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T183	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	64	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	2	0	0
T33	23744	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T183	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	160296	0	0
T11	545	51	0	0
T12	21029	0	0	0
T13	793	53	0	0
T33	23744	0	0	0
T34	0	72	0	0
T36	0	16	0	0
T37	0	299	0	0
T39	0	107	0	0
T40	0	184	0	0
T42	0	54	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	146	0	0
T183	0	232	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3159	0	0
T1	13845	0	0	0
T2	5524	10	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T7	502	7	0	0
T8	11331	0	0	0
T9	573	1	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	403	0	0	0
T15	427	1	0	0
T16	13925	0	0	0
T24	0	7	0	0
T59	0	1	0	0
T68	0	7	0	0
T69	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	36	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	1	0	0
T33	23744	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T177	0	1	0	0
T183	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T22,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T11,T22,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T22,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T22,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T11,T22,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T22,T40
0	1	Covered	T75,T105,T222
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T22,T40
0	1	Covered	T11,T40,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T22,T40
1	-	Covered	T11,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T22,T40
DetectSt	168	Covered	T11,T22,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T22,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T22,T40
DebounceSt->IdleSt	163	Covered	T102,T144,T223
DetectSt->IdleSt	186	Covered	T75,T105,T222
DetectSt->StableSt	191	Covered	T11,T22,T40
IdleSt->DebounceSt	148	Covered	T11,T22,T40
StableSt->IdleSt	206	Covered	T11,T22,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T22,T40
0	1	Covered	T11,T22,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T22,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T22,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T22,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T224
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T22,T40
DetectSt	-	-	-	-	1	-	-	Covered	T75,T105,T222
DetectSt	-	-	-	-	0	1	-	Covered	T11,T22,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T22,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	161	0	0
CntIncr_A	7644258	50067	0	0
CntNoWrap_A	7644258	6941657	0	0
DetectStDropOut_A	7644258	5	0	0
DetectedOut_A	7644258	81916	0	0
DetectedPulseOut_A	7644258	73	0	0
DisabledIdleSt_A	7644258	6753507	0	0
DisabledNoDetection_A	7644258	6755866	0	0
EnterDebounceSt_A	7644258	83	0	0
EnterDetectSt_A	7644258	79	0	0
EnterStableSt_A	7644258	73	0	0
PulseIsPulse_A	7644258	73	0	0
StayInStableSt	7644258	81818	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	48	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	161	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	2	0	0
T22	0	2	0	0
T33	23744	0	0	0
T35	0	4	0	0
T40	0	6	0	0
T43	11907	0	0	0
T45	0	8	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	2	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	4	0	0
T175	0	4	0	0
T183	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	50067	0	0
T11	545	12	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	71	0	0
T22	0	72	0	0
T33	23744	0	0	0
T35	0	164	0	0
T40	0	154	0	0
T43	11907	0	0	0
T45	0	276	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	54	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	186	0	0
T175	0	130	0	0
T183	0	243	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941657	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	5	0	0
T75	13558	1	0	0
T105	0	1	0	0
T125	0	1	0	0
T147	904	0	0	0
T148	495	0	0	0
T149	753	0	0	0
T150	496	0	0	0
T151	522	0	0	0
T152	486	0	0	0
T153	422	0	0	0
T154	404	0	0	0
T155	537	0	0	0
T222	0	1	0	0
T225	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	81916	0	0
T11	545	56	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	285	0	0
T22	0	234	0	0
T33	23744	0	0	0
T35	0	302	0	0
T40	0	123	0	0
T43	11907	0	0	0
T45	0	165	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	18	0	0
T175	0	161	0	0
T183	0	120	0	0
T195	0	165	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	73	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T33	23744	0	0	0
T35	0	2	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T175	0	2	0	0
T183	0	3	0	0
T195	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6753507	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6755866	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	83	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T33	23744	0	0	0
T35	0	2	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T175	0	2	0	0
T183	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	79	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T33	23744	0	0	0
T35	0	2	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T175	0	2	0	0
T183	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	73	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T33	23744	0	0	0
T35	0	2	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T175	0	2	0	0
T183	0	3	0	0
T195	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	73	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T33	23744	0	0	0
T35	0	2	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T175	0	2	0	0
T183	0	3	0	0
T195	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	81818	0	0
T11	545	55	0	0
T12	21029	0	0	0
T13	793	0	0	0
T20	0	283	0	0
T22	0	232	0	0
T33	23744	0	0	0
T35	0	299	0	0
T40	0	120	0	0
T43	11907	0	0	0
T45	0	161	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	17	0	0
T175	0	159	0	0
T183	0	116	0	0
T195	0	163	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	48	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	1	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T163	0	1	0	0
T175	0	2	0	0
T183	0	2	0	0
T195	0	2	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T11,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T22
1	0	Covered	T5,T6,T7
1	1	Covered	T11,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T41
0	1	Covered	T45,T34,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T40,T41
1	-	Covered	T45,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T40,T41
DetectSt	168	Covered	T11,T40,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T40,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T40,T41
DebounceSt->IdleSt	163	Covered	T106,T226,T102
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T40,T41
IdleSt->DebounceSt	148	Covered	T11,T40,T41
StableSt->IdleSt	206	Covered	T40,T41,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T40,T41
0	1	Covered	T11,T40,T41
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T40,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T40,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T106,T199,T227
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T40,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T11,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	89	0	0
CntIncr_A	7644258	47753	0	0
CntNoWrap_A	7644258	6941729	0	0
DetectStDropOut_A	7644258	0	0	0
DetectedOut_A	7644258	3075	0	0
DetectedPulseOut_A	7644258	42	0	0
DisabledIdleSt_A	7644258	6755318	0	0
DisabledNoDetection_A	7644258	6757672	0	0
EnterDebounceSt_A	7644258	48	0	0
EnterDetectSt_A	7644258	42	0	0
EnterStableSt_A	7644258	42	0	0
PulseIsPulse_A	7644258	42	0	0
StayInStableSt	7644258	3011	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	6818	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	89	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	11907	0	0	0
T45	0	4	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	2	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	4	0	0
T106	0	1	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47753	0	0
T11	545	12	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	19	0	0
T35	0	82	0	0
T40	0	80	0	0
T41	0	54	0	0
T43	11907	0	0	0
T45	0	148	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	54	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	186	0	0
T106	0	45	0	0
T177	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941729	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3075	0	0
T11	545	41	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	30	0	0
T40	0	262	0	0
T41	0	41	0	0
T43	11907	0	0	0
T45	0	82	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	68	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	78	0	0
T177	0	4	0	0
T178	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T177	0	1	0	0
T178	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6755318	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	3	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6757672	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	3	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	48	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T106	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T177	0	1	0	0
T178	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T177	0	1	0	0
T178	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T177	0	1	0	0
T178	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3011	0	0
T11	545	39	0	0
T12	21029	0	0	0
T13	793	0	0	0
T33	23744	0	0	0
T35	0	29	0	0
T40	0	260	0	0
T41	0	39	0	0
T43	11907	0	0	0
T45	0	79	0	0
T68	524	0	0	0
T69	525	0	0	0
T75	0	66	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	75	0	0
T177	0	3	0	0
T178	0	75	0	0
T222	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6818	0	0
T1	13845	38	0	0
T2	5524	5	0	0
T3	10725	26	0	0
T4	32180	28	0	0
T5	8381	28	0	0
T6	5169	31	0	0
T7	502	4	0	0
T8	11331	26	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	0	1	0	0
T16	0	10	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	20	0	0
T34	0	1	0	0
T35	0	1	0	0
T45	70285	1	0	0
T46	656	0	0	0
T47	7927	0	0	0
T58	525	0	0	0
T100	11940	0	0	0
T101	4615	0	0	0
T105	0	1	0	0
T144	0	1	0	0
T169	34059	0	0	0
T170	523	0	0	0
T171	528	0	0	0
T172	25186	0	0	0
T177	0	1	0	0
T178	0	2	0	0
T222	0	1	0	0
T225	0	2	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T22,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T22,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T22,T40,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T9,T22,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T40,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T40,T37
0	1	Covered	T40,T37,T41
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T40,T37
1	-	Covered	T40,T37,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T22,T40
DetectSt	168	Covered	T22,T40,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T22,T40,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T40,T37
DebounceSt->IdleSt	163	Covered	T9,T35,T210
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T22,T40,T37
IdleSt->DebounceSt	148	Covered	T9,T22,T40
StableSt->IdleSt	206	Covered	T22,T40,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T22,T40
0	1	Covered	T9,T22,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T40,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T22,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T40,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T35,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T22,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T22,T40,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T37,T41
StableSt	-	-	-	-	-	-	0	Covered	T22,T40,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	171	0	0
CntIncr_A	7644258	69750	0	0
CntNoWrap_A	7644258	6941647	0	0
DetectStDropOut_A	7644258	0	0	0
DetectedOut_A	7644258	21979	0	0
DetectedPulseOut_A	7644258	82	0	0
DisabledIdleSt_A	7644258	6668939	0	0
DisabledNoDetection_A	7644258	6671287	0	0
EnterDebounceSt_A	7644258	90	0	0
EnterDetectSt_A	7644258	82	0	0
EnterStableSt_A	7644258	82	0	0
PulseIsPulse_A	7644258	82	0	0
StayInStableSt	7644258	21864	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	48	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	171	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T22	0	2	0	0
T24	502	0	0	0
T34	0	6	0	0
T35	0	5	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	4	0	0
T59	423	0	0	0
T68	524	0	0	0
T172	0	2	0	0
T183	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	69750	0	0
T9	573	86	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T22	0	40	0	0
T24	502	0	0	0
T34	0	57	0	0
T35	0	246	0	0
T37	0	60	0	0
T40	0	80	0	0
T41	0	54	0	0
T45	0	138	0	0
T59	423	0	0	0
T68	524	0	0	0
T172	0	38	0	0
T183	0	131	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941647	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	171	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	21979	0	0
T22	19852	47	0	0
T23	495	0	0	0
T34	0	95	0	0
T35	0	142	0	0
T37	0	109	0	0
T40	3782	15	0	0
T41	0	132	0	0
T45	0	350	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	0	0	0
T103	0	122	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T172	0	38	0	0
T183	0	371	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	82	0	0
T22	19852	1	0	0
T23	495	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T40	3782	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	0	0	0
T103	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T172	0	1	0	0
T183	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6668939	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	3	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6671287	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	3	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	90	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T22	0	1	0	0
T24	502	0	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T59	423	0	0	0
T68	524	0	0	0
T172	0	1	0	0
T183	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	82	0	0
T22	19852	1	0	0
T23	495	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T40	3782	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	0	0	0
T103	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T172	0	1	0	0
T183	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	82	0	0
T22	19852	1	0	0
T23	495	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T40	3782	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	0	0	0
T103	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T172	0	1	0	0
T183	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	82	0	0
T22	19852	1	0	0
T23	495	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T40	3782	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	0	0	0
T103	0	1	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T172	0	1	0	0
T183	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	21864	0	0
T22	19852	45	0	0
T23	495	0	0	0
T34	0	91	0	0
T35	0	139	0	0
T37	0	108	0	0
T40	3782	14	0	0
T41	0	131	0	0
T45	0	348	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	0	0	0
T103	0	120	0	0
T108	5416	0	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T172	0	36	0	0
T183	0	367	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	48	0	0
T34	0	2	0	0
T35	0	1	0	0
T37	999	1	0	0
T38	161391	0	0	0
T40	3782	1	0	0
T41	0	1	0	0
T44	720	0	0	0
T45	0	2	0	0
T90	416	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T129	424	0	0	0
T175	0	2	0	0
T179	422	0	0	0
T180	522	0	0	0
T189	0	1	0	0
T212	0	1	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T13,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T13,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T13,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T42
1	0	Covered	T5,T6,T7
1	1	Covered	T9,T13,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T40
0	1	Covered	T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T40
0	1	Covered	T20,T35,T105
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T40
1	-	Covered	T20,T35,T105

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T13,T40
DetectSt	168	Covered	T9,T13,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T13,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T40
DebounceSt->IdleSt	163	Covered	T38,T102,T230
DetectSt->IdleSt	186	Covered	T213
DetectSt->StableSt	191	Covered	T9,T13,T40
IdleSt->DebounceSt	148	Covered	T9,T13,T40
StableSt->IdleSt	206	Covered	T40,T20,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T13,T40
0	1	Covered	T9,T13,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T13,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T230,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T13,T40
DetectSt	-	-	-	-	1	-	-	Covered	T213
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T35,T105
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	88	0	0
CntIncr_A	7644258	66300	0	0
CntNoWrap_A	7644258	6941730	0	0
DetectStDropOut_A	7644258	1	0	0
DetectedOut_A	7644258	28491	0	0
DetectedPulseOut_A	7644258	40	0	0
DisabledIdleSt_A	7644258	6672632	0	0
DisabledNoDetection_A	7644258	6674987	0	0
EnterDebounceSt_A	7644258	47	0	0
EnterDetectSt_A	7644258	41	0	0
EnterStableSt_A	7644258	40	0	0
PulseIsPulse_A	7644258	40	0	0
StayInStableSt	7644258	28428	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	6543	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	88	0	0
T9	573	2	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T24	502	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	2	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	2	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	66300	0	0
T9	573	86	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	70	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	71	0	0
T24	502	0	0	0
T35	0	164	0	0
T38	0	38783	0	0
T40	0	80	0	0
T41	0	54	0	0
T45	0	74	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	54	0	0
T232	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941730	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	170	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1	0	0
T213	770	1	0	0
T233	414	0	0	0
T234	528	0	0	0
T235	523	0	0	0
T236	422	0	0	0
T237	6100	0	0	0
T238	15921	0	0	0
T239	11185	0	0	0
T240	694	0	0	0
T241	8772	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	28491	0	0
T9	573	42	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	110	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	53	0	0
T24	502	0	0	0
T35	0	84	0	0
T40	0	43	0	0
T41	0	74	0	0
T45	0	175	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	67	0	0
T105	0	77	0	0
T232	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	40	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	1	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T24	502	0	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0
T105	0	2	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6672632	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	3	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6674987	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	3	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	1	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T24	502	0	0	0
T35	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	41	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	1	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T24	502	0	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0
T105	0	2	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	40	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	1	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T24	502	0	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0
T105	0	2	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	40	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	1	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	1	0	0
T24	502	0	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	1	0	0
T105	0	2	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	28428	0	0
T9	573	40	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	108	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	52	0	0
T24	502	0	0	0
T35	0	82	0	0
T40	0	41	0	0
T41	0	72	0	0
T45	0	173	0	0
T59	423	0	0	0
T68	524	0	0	0
T75	0	65	0	0
T105	0	74	0	0
T232	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6543	0	0
T1	13845	24	0	0
T2	5524	5	0	0
T3	10725	26	0	0
T4	32180	31	0	0
T5	8381	29	0	0
T6	5169	27	0	0
T7	502	5	0	0
T8	11331	27	0	0
T9	573	1	0	0
T14	403	0	0	0
T15	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	17	0	0
T20	4585	1	0	0
T35	0	2	0	0
T41	3079	0	0	0
T45	70285	0	0	0
T46	656	0	0	0
T58	525	0	0	0
T105	0	1	0	0
T169	34059	0	0	0
T198	507	0	0	0
T206	0	1	0	0
T210	0	1	0	0
T213	0	1	0	0
T228	0	2	0	0
T242	0	1	0	0
T243	0	3	0	0
T244	0	1	0	0
T245	20702	0	0	0
T246	426	0	0	0
T247	407	0	0	0