Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T13,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T13,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T13,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T42
1	0	Covered	T5,T6,T7
1	1	Covered	T9,T13,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T42
0	1	Covered	T158,T144,T248
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T42
0	1	Covered	T13,T22,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T42
1	-	Covered	T13,T22,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T13,T42
DetectSt	168	Covered	T9,T13,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T13,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T42
DebounceSt->IdleSt	163	Covered	T45,T182,T163
DetectSt->IdleSt	186	Covered	T158,T144,T248
DetectSt->StableSt	191	Covered	T9,T13,T42
IdleSt->DebounceSt	148	Covered	T9,T13,T42
StableSt->IdleSt	206	Covered	T13,T22,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T13,T42
0	1	Covered	T9,T13,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T13,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T158,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T13,T42
DetectSt	-	-	-	-	1	-	-	Covered	T158,T144,T248
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T22,T20
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	139	0	0
CntIncr_A	7644258	99874	0	0
CntNoWrap_A	7644258	6941679	0	0
DetectStDropOut_A	7644258	4	0	0
DetectedOut_A	7644258	26040	0	0
DetectedPulseOut_A	7644258	62	0	0
DisabledIdleSt_A	7644258	6668595	0	0
DisabledNoDetection_A	7644258	6670961	0	0
EnterDebounceSt_A	7644258	74	0	0
EnterDetectSt_A	7644258	67	0	0
EnterStableSt_A	7644258	62	0	0
PulseIsPulse_A	7644258	62	0	0
StayInStableSt	7644258	25951	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	139	0	0
T9	573	2	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	4	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	4	0	0
T22	0	2	0	0
T24	502	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	99874	0	0
T9	573	86	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	140	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	142	0	0
T22	0	40	0	0
T24	502	0	0	0
T34	0	38	0	0
T35	0	164	0	0
T41	0	54	0	0
T42	0	100	0	0
T45	0	87	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941679	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	170	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	4	0	0
T144	0	1	0	0
T158	13745	1	0	0
T159	1288	0	0	0
T165	5400	0	0	0
T222	674	0	0	0
T223	0	1	0	0
T248	0	1	0	0
T249	404	0	0	0
T250	650	0	0	0
T251	882	0	0	0
T252	686	0	0	0
T253	976	0	0	0
T254	514	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	26040	0	0
T9	573	77	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	82	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	207	0	0
T22	0	8	0	0
T24	502	0	0	0
T34	0	195	0	0
T35	0	218	0	0
T41	0	261	0	0
T42	0	42	0	0
T45	0	205	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	62	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6668595	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	3	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6670961	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	3	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	74	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	67	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	62	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	62	0	0
T9	573	1	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	2	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	25951	0	0
T9	573	75	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	0	0	0
T13	793	79	0	0
T15	427	0	0	0
T16	13925	0	0	0
T20	0	204	0	0
T22	0	7	0	0
T24	502	0	0	0
T34	0	192	0	0
T35	0	215	0	0
T41	0	259	0	0
T42	0	40	0	0
T45	0	204	0	0
T59	423	0	0	0
T68	524	0	0	0
T183	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	35	0	0
T13	793	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T43	11907	0	0	0
T45	0	1	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T174	0	2	0	0
T183	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T38,T39,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T38,T39,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T38,T39,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T42,T38
1	0	Covered	T5,T6,T7
1	1	Covered	T38,T39,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T34
0	1	Covered	T161,T145
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T34
0	1	Covered	T34,T35,T183
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T34
1	-	Covered	T34,T35,T183

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T34
DetectSt	168	Covered	T38,T39,T34
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T38,T39,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T34
DebounceSt->IdleSt	163	Covered	T183,T102,T231
DetectSt->IdleSt	186	Covered	T161,T145
DetectSt->StableSt	191	Covered	T38,T39,T34
IdleSt->DebounceSt	148	Covered	T38,T39,T34
StableSt->IdleSt	206	Covered	T34,T35,T183

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T34
0	1	Covered	T38,T39,T34
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T34
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T34
DetectSt	-	-	-	-	1	-	-	Covered	T161,T145
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T183
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	84	0	0
CntIncr_A	7644258	80298	0	0
CntNoWrap_A	7644258	6941734	0	0
DetectStDropOut_A	7644258	3	0	0
DetectedOut_A	7644258	43792	0	0
DetectedPulseOut_A	7644258	37	0	0
DisabledIdleSt_A	7644258	6604401	0	0
DisabledNoDetection_A	7644258	6606761	0	0
EnterDebounceSt_A	7644258	44	0	0
EnterDetectSt_A	7644258	40	0	0
EnterStableSt_A	7644258	37	0	0
PulseIsPulse_A	7644258	37	0	0
StayInStableSt	7644258	43737	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	6452	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	84	0	0
T20	4585	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	999	0	0	0
T38	161391	2	0	0
T39	0	2	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	2	0	0
T163	0	6	0	0
T176	0	2	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	5	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	2	0	0
T229	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	80298	0	0
T20	4585	0	0	0
T34	0	19	0	0
T35	0	82	0	0
T37	999	0	0	0
T38	161391	38783	0	0
T39	0	36	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	45	0	0
T163	0	92	0	0
T176	0	42	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	243	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	90	0	0
T229	0	39565	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941734	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3	0	0
T145	0	1	0	0
T161	11675	2	0	0
T201	525	0	0	0
T202	422	0	0	0
T203	26409	0	0	0
T204	504	0	0	0
T205	403	0	0	0
T206	1027	0	0	0
T207	13626	0	0	0
T208	3426	0	0	0
T209	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	43792	0	0
T20	4585	0	0	0
T34	0	15	0	0
T35	0	113	0	0
T37	999	0	0	0
T38	161391	41	0	0
T39	0	43	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	80	0	0
T163	0	201	0	0
T176	0	177	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	237	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	43	0	0
T229	0	41422	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	37	0	0
T20	4585	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	999	0	0	0
T38	161391	1	0	0
T39	0	1	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	1	0	0
T163	0	3	0	0
T176	0	1	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	2	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	1	0	0
T229	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6604401	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6606761	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	44	0	0
T20	4585	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	999	0	0	0
T38	161391	1	0	0
T39	0	1	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	1	0	0
T163	0	3	0	0
T176	0	1	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	3	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	1	0	0
T229	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	40	0	0
T20	4585	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	999	0	0	0
T38	161391	1	0	0
T39	0	1	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	1	0	0
T163	0	3	0	0
T176	0	1	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	2	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	1	0	0
T229	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	37	0	0
T20	4585	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	999	0	0	0
T38	161391	1	0	0
T39	0	1	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	1	0	0
T163	0	3	0	0
T176	0	1	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	2	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	1	0	0
T229	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	37	0	0
T20	4585	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	999	0	0	0
T38	161391	1	0	0
T39	0	1	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	1	0	0
T163	0	3	0	0
T176	0	1	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	2	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	1	0	0
T229	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	43737	0	0
T20	4585	0	0	0
T34	0	14	0	0
T35	0	112	0	0
T37	999	0	0	0
T38	161391	39	0	0
T39	0	41	0	0
T44	720	0	0	0
T90	416	0	0	0
T106	0	78	0	0
T163	0	197	0	0
T176	0	175	0	0
T179	422	0	0	0
T180	522	0	0	0
T183	0	234	0	0
T196	644	0	0	0
T197	505	0	0	0
T198	507	0	0	0
T212	0	42	0	0
T229	0	41421	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6452	0	0
T1	13845	29	0	0
T2	5524	4	0	0
T3	10725	32	0	0
T4	32180	35	0	0
T5	8381	31	0	0
T6	5169	25	0	0
T7	502	5	0	0
T8	11331	29	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	0	6	0	0
T16	0	12	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	19	0	0
T34	679	1	0	0
T35	0	1	0	0
T130	0	1	0	0
T140	2103	0	0	0
T158	0	1	0	0
T163	0	2	0	0
T183	0	1	0	0
T212	0	1	0	0
T214	19474	0	0	0
T215	44319	0	0	0
T216	495	0	0	0
T217	406	0	0	0
T218	55026	0	0	0
T219	649	0	0	0
T220	491	0	0	0
T221	406	0	0	0
T229	0	1	0	0
T243	0	1	0	0
T255	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T13,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T11,T13,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T11,T13,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T42
1	0	Covered	T5,T6,T7
1	1	Covered	T11,T13,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T42
0	1	Covered	T158,T248
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T42
0	1	Covered	T11,T13,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T13,T42
1	-	Covered	T11,T13,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T13,T42
DetectSt	168	Covered	T11,T13,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T11,T13,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T13,T42
DebounceSt->IdleSt	163	Covered	T38,T102,T256
DetectSt->IdleSt	186	Covered	T158,T248,T54
DetectSt->StableSt	191	Covered	T11,T13,T42
IdleSt->DebounceSt	148	Covered	T11,T13,T42
StableSt->IdleSt	206	Covered	T11,T13,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T13,T42
0	1	Covered	T11,T13,T42
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T13,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T13,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T256,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T13,T42
DetectSt	-	-	-	-	1	-	-	Covered	T158,T248,T54
DetectSt	-	-	-	-	0	1	-	Covered	T11,T13,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T13,T42
StableSt	-	-	-	-	-	-	0	Covered	T11,T13,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	155	0	0
CntIncr_A	7644258	149863	0	0
CntNoWrap_A	7644258	6941663	0	0
DetectStDropOut_A	7644258	2	0	0
DetectedOut_A	7644258	71691	0	0
DetectedPulseOut_A	7644258	71	0	0
DisabledIdleSt_A	7644258	6594555	0	0
DisabledNoDetection_A	7644258	6596907	0	0
EnterDebounceSt_A	7644258	81	0	0
EnterDetectSt_A	7644258	74	0	0
EnterStableSt_A	7644258	71	0	0
PulseIsPulse_A	7644258	71	0	0
StayInStableSt	7644258	71591	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	155	0	0
T11	545	2	0	0
T12	21029	0	0	0
T13	793	4	0	0
T20	0	4	0	0
T22	0	4	0	0
T33	23744	0	0	0
T38	0	3	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	149863	0	0
T11	545	12	0	0
T12	21029	0	0	0
T13	793	140	0	0
T20	0	142	0	0
T22	0	112	0	0
T33	23744	0	0	0
T38	0	77566	0	0
T40	0	37	0	0
T41	0	54	0	0
T42	0	100	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	77	0	0
T183	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941663	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2	0	0
T158	13745	1	0	0
T159	1288	0	0	0
T165	5400	0	0	0
T222	674	0	0	0
T248	0	1	0	0
T249	404	0	0	0
T250	650	0	0	0
T251	882	0	0	0
T252	686	0	0	0
T253	976	0	0	0
T254	514	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	71691	0	0
T11	545	43	0	0
T12	21029	0	0	0
T13	793	128	0	0
T20	0	81	0	0
T22	0	261	0	0
T33	23744	0	0	0
T38	0	12403	0	0
T40	0	170	0	0
T41	0	260	0	0
T42	0	55	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	44	0	0
T183	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	71	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	2	0	0
T20	0	2	0	0
T22	0	2	0	0
T33	23744	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6594555	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6596907	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	81	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	2	0	0
T20	0	2	0	0
T22	0	2	0	0
T33	23744	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	74	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	2	0	0
T20	0	2	0	0
T22	0	2	0	0
T33	23744	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	71	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	2	0	0
T20	0	2	0	0
T22	0	2	0	0
T33	23744	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	71	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	2	0	0
T20	0	2	0	0
T22	0	2	0	0
T33	23744	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	71591	0	0
T11	545	42	0	0
T12	21029	0	0	0
T13	793	125	0	0
T20	0	78	0	0
T22	0	258	0	0
T33	23744	0	0	0
T38	0	12402	0	0
T40	0	169	0	0
T41	0	258	0	0
T42	0	54	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T103	0	42	0	0
T183	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	42	0	0
T11	545	1	0	0
T12	21029	0	0	0
T13	793	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T33	23744	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	11907	0	0	0
T68	524	0	0	0
T69	525	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T183	0	1	0	0
T189	0	1	0	0
T195	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T36,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T13,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T36,T37
0	1	Covered	T13,T45,T34
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T36,T37
1	-	Covered	T13,T45,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T36,T37
DetectSt	168	Covered	T13,T36,T37
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T36,T37
DebounceSt->IdleSt	163	Covered	T102,T213
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T36,T37
IdleSt->DebounceSt	148	Covered	T13,T36,T37
StableSt->IdleSt	206	Covered	T13,T45,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T36,T37
0	1	Covered	T13,T36,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T36,T37
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T213
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T45,T34
StableSt	-	-	-	-	-	-	0	Covered	T13,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	92	0	0
CntIncr_A	7644258	48002	0	0
CntNoWrap_A	7644258	6941726	0	0
DetectStDropOut_A	7644258	0	0	0
DetectedOut_A	7644258	4224	0	0
DetectedPulseOut_A	7644258	45	0	0
DisabledIdleSt_A	7644258	6755193	0	0
DisabledNoDetection_A	7644258	6757554	0	0
EnterDebounceSt_A	7644258	47	0	0
EnterDetectSt_A	7644258	45	0	0
EnterStableSt_A	7644258	45	0	0
PulseIsPulse_A	7644258	45	0	0
StayInStableSt	7644258	4153	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	6426	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	92	0	0
T13	793	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T43	11907	0	0	0
T45	0	4	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	2	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T183	0	4	0	0
T258	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	48002	0	0
T13	793	70	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	19	0	0
T35	0	164	0	0
T36	0	32	0	0
T37	0	60	0	0
T43	11907	0	0	0
T45	0	138	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	54	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	93	0	0
T183	0	131	0	0
T258	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941726	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	4224	0	0
T13	793	44	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	42	0	0
T35	0	142	0	0
T36	0	41	0	0
T37	0	150	0	0
T43	11907	0	0	0
T45	0	283	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	68	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	133	0	0
T183	0	264	0	0
T258	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	45	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T183	0	2	0	0
T258	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6755193	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6757554	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	47	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T183	0	2	0	0
T258	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	45	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T183	0	2	0	0
T258	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	45	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T183	0	2	0	0
T258	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	45	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T183	0	2	0	0
T258	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	4153	0	0
T13	793	43	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	41	0	0
T35	0	139	0	0
T36	0	39	0	0
T37	0	148	0	0
T43	11907	0	0	0
T45	0	280	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	66	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	131	0	0
T183	0	261	0	0
T258	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6426	0	0
T1	13845	30	0	0
T2	5524	6	0	0
T3	10725	28	0	0
T4	32180	34	0	0
T5	8381	29	0	0
T6	5169	25	0	0
T7	502	4	0	0
T8	11331	23	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	0	2	0	0
T16	0	11	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	18	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T43	11907	0	0	0
T45	0	1	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T175	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T212	0	1	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T36,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T36,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T36,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T42,T36
1	0	Covered	T5,T6,T7
1	1	Covered	T13,T36,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T36,T22
0	1	Covered	T255,T213,T227
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T36,T22
0	1	Covered	T13,T22,T40
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T36,T22
1	-	Covered	T13,T22,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T36,T22
DetectSt	168	Covered	T13,T36,T22
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T36,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T36,T22
DebounceSt->IdleSt	163	Covered	T35,T102,T243
DetectSt->IdleSt	186	Covered	T255,T213,T227
DetectSt->StableSt	191	Covered	T13,T36,T22
IdleSt->DebounceSt	148	Covered	T13,T36,T22
StableSt->IdleSt	206	Covered	T13,T22,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T36,T22
0	1	Covered	T13,T36,T22
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T36,T22
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T36,T22
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T36,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T243,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T36,T22
DetectSt	-	-	-	-	1	-	-	Covered	T255,T213,T227
DetectSt	-	-	-	-	0	1	-	Covered	T13,T36,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T22,T40
StableSt	-	-	-	-	-	-	0	Covered	T13,T36,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	161	0	0
CntIncr_A	7644258	89597	0	0
CntNoWrap_A	7644258	6941657	0	0
DetectStDropOut_A	7644258	3	0	0
DetectedOut_A	7644258	15324	0	0
DetectedPulseOut_A	7644258	74	0	0
DisabledIdleSt_A	7644258	6594074	0	0
DisabledNoDetection_A	7644258	6596427	0	0
EnterDebounceSt_A	7644258	84	0	0
EnterDetectSt_A	7644258	77	0	0
EnterStableSt_A	7644258	74	0	0
PulseIsPulse_A	7644258	74	0	0
StayInStableSt	7644258	15214	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	161	0	0
T13	793	2	0	0
T20	0	4	0	0
T22	0	4	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T40	0	6	0	0
T43	11907	0	0	0
T45	0	4	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	89597	0	0
T13	793	70	0	0
T20	0	142	0	0
T22	0	144	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	38	0	0
T35	0	82	0	0
T36	0	32	0	0
T39	0	36	0	0
T40	0	154	0	0
T43	11907	0	0	0
T45	0	128	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941657	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3	0	0
T123	18588	0	0	0
T213	0	1	0	0
T227	0	1	0	0
T255	16837	1	0	0
T259	527	0	0	0
T260	525	0	0	0
T261	2233	0	0	0
T262	645	0	0	0
T263	521	0	0	0
T264	8047	0	0	0
T265	21043	0	0	0
T266	2457	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	15324	0	0
T13	793	43	0	0
T20	0	81	0	0
T22	0	135	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	116	0	0
T36	0	41	0	0
T39	0	108	0	0
T40	0	511	0	0
T43	11907	0	0	0
T45	0	169	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	123	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	74	0	0
T13	793	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6594074	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6596427	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	84	0	0
T13	793	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	77	0	0
T13	793	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	74	0	0
T13	793	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	74	0	0
T13	793	1	0	0
T20	0	2	0	0
T22	0	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	3	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	15214	0	0
T13	793	42	0	0
T20	0	78	0	0
T22	0	132	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	114	0	0
T36	0	39	0	0
T39	0	106	0	0
T40	0	506	0	0
T43	11907	0	0	0
T45	0	167	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	121	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T258	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	37	0	0
T13	793	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T40	0	1	0	0
T43	11907	0	0	0
T45	0	2	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T183	0	2	0	0
T232	0	1	0	0
T258	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T42,T36
1	0	Covered	T5,T6,T7
1	1	Covered	T13,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T34,T35
0	1	Covered	T34,T255
1	0	Covered	T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T34,T35
0	1	Covered	T175,T195,T176
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T34,T35
1	-	Covered	T175,T195,T176

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T34,T35
DetectSt	168	Covered	T13,T34,T35
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T34,T35
DebounceSt->IdleSt	163	Covered	T102,T223
DetectSt->IdleSt	186	Covered	T34,T255,T54
DetectSt->StableSt	191	Covered	T13,T34,T35
IdleSt->DebounceSt	148	Covered	T13,T34,T35
StableSt->IdleSt	206	Covered	T35,T75,T183

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T34,T35
0	1	Covered	T13,T34,T35
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T34,T35
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T34,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T34,T255,T54
DetectSt	-	-	-	-	0	1	-	Covered	T13,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T175,T195,T176
StableSt	-	-	-	-	-	-	0	Covered	T13,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	77	0	0
CntIncr_A	7644258	2230	0	0
CntNoWrap_A	7644258	6941741	0	0
DetectStDropOut_A	7644258	2	0	0
DetectedOut_A	7644258	2331	0	0
DetectedPulseOut_A	7644258	35	0	0
DisabledIdleSt_A	7644258	6922396	0	0
DisabledNoDetection_A	7644258	6924758	0	0
EnterDebounceSt_A	7644258	40	0	0
EnterDetectSt_A	7644258	38	0	0
EnterStableSt_A	7644258	35	0	0
PulseIsPulse_A	7644258	35	0	0
StayInStableSt	7644258	2278	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7644258	7150	0	0
gen_low_level_sva.LowLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	77	0	0
T13	793	2	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	2	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	2	0	0
T106	0	2	0	0
T175	0	4	0	0
T183	0	2	0	0
T195	0	2	0	0
T232	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2230	0	0
T13	793	70	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	38	0	0
T35	0	82	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	89	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	93	0	0
T106	0	45	0	0
T175	0	130	0	0
T183	0	81	0	0
T195	0	72	0	0
T232	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941741	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2	0	0
T34	679	1	0	0
T140	2103	0	0	0
T214	19474	0	0	0
T215	44319	0	0	0
T216	495	0	0	0
T217	406	0	0	0
T218	55026	0	0	0
T219	649	0	0	0
T220	491	0	0	0
T221	406	0	0	0
T255	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2331	0	0
T13	793	110	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	75	0	0
T35	0	41	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	62	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	132	0	0
T106	0	81	0	0
T175	0	79	0	0
T183	0	323	0	0
T195	0	40	0	0
T232	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	35	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T175	0	2	0	0
T183	0	1	0	0
T195	0	1	0	0
T232	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6922396	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6924758	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	40	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T175	0	2	0	0
T183	0	1	0	0
T195	0	1	0	0
T232	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	38	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T175	0	2	0	0
T183	0	1	0	0
T195	0	1	0	0
T232	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	35	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T175	0	2	0	0
T183	0	1	0	0
T195	0	1	0	0
T232	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	35	0	0
T13	793	1	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	1	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	1	0	0
T106	0	1	0	0
T175	0	2	0	0
T183	0	1	0	0
T195	0	1	0	0
T232	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2278	0	0
T13	793	108	0	0
T31	502	0	0	0
T33	23744	0	0	0
T34	0	73	0	0
T35	0	39	0	0
T43	11907	0	0	0
T69	525	0	0	0
T70	506	0	0	0
T72	13148	0	0	0
T75	0	60	0	0
T79	8487	0	0	0
T86	450	0	0	0
T89	421	0	0	0
T105	0	130	0	0
T106	0	79	0	0
T175	0	76	0	0
T183	0	321	0	0
T195	0	39	0	0
T232	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	7150	0	0
T1	13845	27	0	0
T2	5524	7	0	0
T3	10725	37	0	0
T4	32180	33	0	0
T5	8381	31	0	0
T6	5169	32	0	0
T7	502	6	0	0
T8	11331	28	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	0	3	0	0
T16	0	13	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	17	0	0
T175	4939	1	0	0
T176	0	1	0	0
T178	0	2	0	0
T181	0	2	0	0
T195	2479	1	0	0
T206	0	1	0	0
T223	0	1	0	0
T230	0	1	0	0
T242	0	1	0	0
T243	0	3	0	0
T267	717	0	0	0
T268	24821	0	0	0
T269	141226	0	0	0
T270	508	0	0	0
T271	422	0	0	0
T272	26546	0	0	0
T273	454	0	0	0
T274	645	0	0	0