Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T6,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T6,T108,T109
1	0	Covered	T169,T275,T214

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T3
1	-	Covered	T5,T1,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T1
DetectSt	168	Covered	T5,T6,T1
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T5,T1,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T1
DebounceSt->IdleSt	163	Covered	T102,T276,T277
DetectSt->IdleSt	186	Covered	T6,T108,T169
DetectSt->StableSt	191	Covered	T5,T1,T3
IdleSt->DebounceSt	148	Covered	T5,T6,T1
StableSt->IdleSt	206	Covered	T5,T1,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T1
0	1	Covered	T5,T6,T1
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T1
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T276,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T108,T169
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T1
StableSt	-	-	-	-	-	-	1	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	3004	0	0
CntIncr_A	7644258	114999	0	0
CntNoWrap_A	7644258	6938814	0	0
DetectStDropOut_A	7644258	279	0	0
DetectedOut_A	7644258	78122	0	0
DetectedPulseOut_A	7644258	953	0	0
DisabledIdleSt_A	7644258	6439519	0	0
DisabledNoDetection_A	7644258	6441739	0	0
EnterDebounceSt_A	7644258	1540	0	0
EnterDetectSt_A	7644258	1465	0	0
EnterStableSt_A	7644258	953	0	0
PulseIsPulse_A	7644258	953	0	0
StayInStableSt	7644258	77065	0	0
gen_high_event_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	848	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3004	0	0
T1	13845	30	0	0
T2	5524	0	0	0
T3	10725	58	0	0
T4	32180	44	0	0
T5	8381	36	0	0
T6	5169	16	0	0
T7	502	0	0	0
T8	11331	46	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	2	0	0
T43	0	52	0	0
T55	0	22	0	0
T72	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	114999	0	0
T1	13845	840	0	0
T2	5524	0	0	0
T3	10725	928	0	0
T4	32180	1474	0	0
T5	8381	828	0	0
T6	5169	403	0	0
T7	502	0	0	0
T8	11331	2047	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	21	0	0
T43	0	1170	0	0
T55	0	627	0	0
T72	0	407	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6938814	0	0
T1	13845	13408	0	0
T2	5524	607	0	0
T3	10725	10262	0	0
T4	32180	31713	0	0
T5	8381	7942	0	0
T6	5169	4752	0	0
T7	502	101	0	0
T8	11331	10882	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	279	0	0
T1	13845	0	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T6	5169	8	0	0
T7	502	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T108	0	4	0	0
T109	0	24	0	0
T110	0	24	0	0
T112	0	11	0	0
T114	0	5	0	0
T115	0	9	0	0
T116	0	13	0	0
T118	0	13	0	0
T278	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	78122	0	0
T1	13845	1288	0	0
T2	5524	0	0	0
T3	10725	1301	0	0
T4	32180	2252	0	0
T5	8381	1430	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1967	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	77	0	0
T43	0	1448	0	0
T49	0	34	0	0
T55	0	323	0	0
T72	0	478	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	953	0	0
T1	13845	15	0	0
T2	5524	0	0	0
T3	10725	29	0	0
T4	32180	22	0	0
T5	8381	18	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	23	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	1	0	0
T43	0	26	0	0
T49	0	1	0	0
T55	0	11	0	0
T72	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6439519	0	0
T1	13845	8585	0	0
T2	5524	607	0	0
T3	10725	6708	0	0
T4	32180	25247	0	0
T5	8381	4030	0	0
T6	5169	2014	0	0
T7	502	101	0	0
T8	11331	4053	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6441739	0	0
T1	13845	8587	0	0
T2	5524	620	0	0
T3	10725	6709	0	0
T4	32180	25250	0	0
T5	8381	4030	0	0
T6	5169	2014	0	0
T7	502	102	0	0
T8	11331	4053	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1540	0	0
T1	13845	15	0	0
T2	5524	0	0	0
T3	10725	29	0	0
T4	32180	22	0	0
T5	8381	18	0	0
T6	5169	8	0	0
T7	502	0	0	0
T8	11331	23	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	1	0	0
T43	0	26	0	0
T55	0	11	0	0
T72	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1465	0	0
T1	13845	15	0	0
T2	5524	0	0	0
T3	10725	29	0	0
T4	32180	22	0	0
T5	8381	18	0	0
T6	5169	8	0	0
T7	502	0	0	0
T8	11331	23	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	1	0	0
T43	0	26	0	0
T55	0	11	0	0
T72	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	953	0	0
T1	13845	15	0	0
T2	5524	0	0	0
T3	10725	29	0	0
T4	32180	22	0	0
T5	8381	18	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	23	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	1	0	0
T43	0	26	0	0
T49	0	1	0	0
T55	0	11	0	0
T72	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	953	0	0
T1	13845	15	0	0
T2	5524	0	0	0
T3	10725	29	0	0
T4	32180	22	0	0
T5	8381	18	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	23	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	1	0	0
T43	0	26	0	0
T49	0	1	0	0
T55	0	11	0	0
T72	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	77065	0	0
T1	13845	1272	0	0
T2	5524	0	0	0
T3	10725	1271	0	0
T4	32180	2222	0	0
T5	8381	1411	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1943	0	0
T9	573	0	0	0
T14	403	0	0	0
T31	0	75	0	0
T43	0	1421	0	0
T49	0	32	0	0
T55	0	311	0	0
T72	0	467	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	848	0	0
T1	13845	14	0	0
T2	5524	0	0	0
T3	10725	28	0	0
T4	32180	14	0	0
T5	8381	17	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	22	0	0
T9	573	0	0	0
T14	403	0	0	0
T32	0	18	0	0
T43	0	25	0	0
T52	0	8	0	0
T55	0	10	0	0
T72	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T5,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T99,T101,T111
1	0	Covered	T102,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T3,T4,T8
1	0	Covered	T102,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T3
1	-	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T2
DetectSt	168	Covered	T5,T1,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T5,T1,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T3
DebounceSt->IdleSt	163	Covered	T2,T12,T33
DetectSt->IdleSt	186	Covered	T99,T101,T111
DetectSt->StableSt	191	Covered	T5,T1,T3
IdleSt->DebounceSt	148	Covered	T5,T1,T2
StableSt->IdleSt	206	Covered	T5,T1,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T12,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T99,T101,T111
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	1072	0	0
CntIncr_A	7644258	51253	0	0
CntNoWrap_A	7644258	6940746	0	0
DetectStDropOut_A	7644258	54	0	0
DetectedOut_A	7644258	15744	0	0
DetectedPulseOut_A	7644258	427	0	0
DisabledIdleSt_A	7644258	6605479	0	0
DisabledNoDetection_A	7644258	6607213	0	0
EnterDebounceSt_A	7644258	591	0	0
EnterDetectSt_A	7644258	485	0	0
EnterStableSt_A	7644258	427	0	0
PulseIsPulse_A	7644258	427	0	0
StayInStableSt	7644258	15277	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	384	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1072	0	0
T1	13845	2	0	0
T2	5524	1	0	0
T3	10725	2	0	0
T4	32180	16	0	0
T5	8381	2	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	2	0	0
T9	573	0	0	0
T12	0	11	0	0
T14	403	0	0	0
T16	0	6	0	0
T33	0	9	0	0
T43	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	51253	0	0
T1	13845	46	0	0
T2	5524	20	0	0
T3	10725	33	0	0
T4	32180	320	0	0
T5	8381	48	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	55	0	0
T9	573	0	0	0
T12	0	521	0	0
T14	403	0	0	0
T16	0	399	0	0
T33	0	811	0	0
T43	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6940746	0	0
T1	13845	13436	0	0
T2	5524	606	0	0
T3	10725	10318	0	0
T4	32180	31741	0	0
T5	8381	7976	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10926	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	54	0	0
T23	495	0	0	0
T40	3782	0	0	0
T57	1821	0	0	0
T71	503	0	0	0
T99	26116	3	0	0
T101	0	1	0	0
T108	5416	0	0	0
T111	0	1	0	0
T113	0	4	0	0
T117	0	3	0	0
T119	0	2	0	0
T121	0	4	0	0
T122	0	12	0	0
T123	0	9	0	0
T124	0	1	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T129	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	15744	0	0
T1	13845	63	0	0
T2	5524	0	0	0
T3	10725	67	0	0
T4	32180	664	0	0
T5	8381	74	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	97	0	0
T9	573	0	0	0
T12	0	282	0	0
T14	403	0	0	0
T16	0	267	0	0
T31	0	3	0	0
T33	0	39	0	0
T43	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	427	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	1	0	0
T4	32180	8	0	0
T5	8381	1	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1	0	0
T9	573	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T16	0	3	0	0
T31	0	1	0	0
T33	0	4	0	0
T43	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6605479	0	0
T1	13845	12151	0	0
T2	5524	565	0	0
T3	10725	9020	0	0
T4	32180	29513	0	0
T5	8381	6549	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	8962	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6607213	0	0
T1	13845	12154	0	0
T2	5524	577	0	0
T3	10725	9022	0	0
T4	32180	29517	0	0
T5	8381	6550	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	8963	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	591	0	0
T1	13845	1	0	0
T2	5524	1	0	0
T3	10725	1	0	0
T4	32180	8	0	0
T5	8381	1	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1	0	0
T9	573	0	0	0
T12	0	7	0	0
T14	403	0	0	0
T16	0	3	0	0
T33	0	5	0	0
T43	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	485	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	1	0	0
T4	32180	8	0	0
T5	8381	1	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1	0	0
T9	573	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T16	0	3	0	0
T31	0	1	0	0
T33	0	4	0	0
T43	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	427	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	1	0	0
T4	32180	8	0	0
T5	8381	1	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1	0	0
T9	573	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T16	0	3	0	0
T31	0	1	0	0
T33	0	4	0	0
T43	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	427	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	1	0	0
T4	32180	8	0	0
T5	8381	1	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	1	0	0
T9	573	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T16	0	3	0	0
T31	0	1	0	0
T33	0	4	0	0
T43	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	15277	0	0
T1	13845	61	0	0
T2	5524	0	0	0
T3	10725	66	0	0
T4	32180	651	0	0
T5	8381	72	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	96	0	0
T9	573	0	0	0
T12	0	278	0	0
T14	403	0	0	0
T16	0	264	0	0
T31	0	2	0	0
T33	0	35	0	0
T43	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	384	0	0
T3	10725	1	0	0
T4	32180	3	0	0
T8	11331	1	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	3	0	0
T24	502	0	0	0
T31	0	1	0	0
T32	0	9	0	0
T33	0	4	0	0
T55	0	1	0	0
T59	423	0	0	0
T66	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T6,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T6,T72,T108
1	0	Covered	T3,T4,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T8
0	1	Covered	T1,T8,T43
1	0	Covered	T5,T279

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T8
1	-	Covered	T1,T8,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T1
DetectSt	168	Covered	T5,T6,T1
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T5,T1,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T1
DebounceSt->IdleSt	163	Covered	T102,T276,T277
DetectSt->IdleSt	186	Covered	T6,T3,T4
DetectSt->StableSt	191	Covered	T5,T1,T8
IdleSt->DebounceSt	148	Covered	T5,T6,T1
StableSt->IdleSt	206	Covered	T5,T1,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T1
0	1	Covered	T5,T6,T1
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T1
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T276,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T1
DetectSt	-	-	-	-	1	-	-	Covered	T6,T3,T4
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T8
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T1
StableSt	-	-	-	-	-	-	1	Covered	T5,T1,T8
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	2950	0	0
CntIncr_A	7644258	114264	0	0
CntNoWrap_A	7644258	6938868	0	0
DetectStDropOut_A	7644258	295	0	0
DetectedOut_A	7644258	81415	0	0
DetectedPulseOut_A	7644258	1006	0	0
DisabledIdleSt_A	7644258	6439230	0	0
DisabledNoDetection_A	7644258	6441458	0	0
EnterDebounceSt_A	7644258	1499	0	0
EnterDetectSt_A	7644258	1451	0	0
EnterStableSt_A	7644258	1006	0	0
PulseIsPulse_A	7644258	1006	0	0
StayInStableSt	7644258	80313	0	0
gen_high_event_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	893	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2950	0	0
T1	13845	10	0	0
T2	5524	0	0	0
T3	10725	32	0	0
T4	32180	16	0	0
T5	8381	16	0	0
T6	5169	28	0	0
T7	502	0	0	0
T8	11331	26	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	14	0	0
T52	0	10	0	0
T55	0	24	0	0
T72	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	114264	0	0
T1	13845	355	0	0
T2	5524	0	0	0
T3	10725	826	0	0
T4	32180	733	0	0
T5	8381	360	0	0
T6	5169	709	0	0
T7	502	0	0	0
T8	11331	832	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	350	0	0
T52	0	375	0	0
T55	0	504	0	0
T72	0	1499	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6938868	0	0
T1	13845	13428	0	0
T2	5524	607	0	0
T3	10725	10288	0	0
T4	32180	31741	0	0
T5	8381	7962	0	0
T6	5169	4740	0	0
T7	502	101	0	0
T8	11331	10902	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	295	0	0
T1	13845	0	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T6	5169	14	0	0
T7	502	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T72	0	9	0	0
T108	0	8	0	0
T109	0	25	0	0
T110	0	11	0	0
T112	0	15	0	0
T115	0	26	0	0
T116	0	17	0	0
T280	0	13	0	0
T281	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	81415	0	0
T1	13845	248	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	14	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	475	0	0
T9	573	0	0	0
T14	403	0	0	0
T32	0	1108	0	0
T43	0	318	0	0
T52	0	289	0	0
T55	0	390	0	0
T169	0	1911	0	0
T245	0	488	0	0
T275	0	1241	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1006	0	0
T1	13845	5	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	8	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	13	0	0
T9	573	0	0	0
T14	403	0	0	0
T32	0	13	0	0
T43	0	7	0	0
T52	0	5	0	0
T55	0	12	0	0
T169	0	21	0	0
T245	0	11	0	0
T275	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6439230	0	0
T1	13845	9413	0	0
T2	5524	607	0	0
T3	10725	7482	0	0
T4	32180	26957	0	0
T5	8381	5471	0	0
T6	5169	2014	0	0
T7	502	101	0	0
T8	11331	5773	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6441458	0	0
T1	13845	9415	0	0
T2	5524	620	0	0
T3	10725	7484	0	0
T4	32180	26968	0	0
T5	8381	5472	0	0
T6	5169	2014	0	0
T7	502	102	0	0
T8	11331	5774	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1499	0	0
T1	13845	5	0	0
T2	5524	0	0	0
T3	10725	16	0	0
T4	32180	8	0	0
T5	8381	8	0	0
T6	5169	14	0	0
T7	502	0	0	0
T8	11331	13	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	7	0	0
T52	0	5	0	0
T55	0	12	0	0
T72	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1451	0	0
T1	13845	5	0	0
T2	5524	0	0	0
T3	10725	16	0	0
T4	32180	8	0	0
T5	8381	8	0	0
T6	5169	14	0	0
T7	502	0	0	0
T8	11331	13	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	7	0	0
T52	0	5	0	0
T55	0	12	0	0
T72	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1006	0	0
T1	13845	5	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	8	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	13	0	0
T9	573	0	0	0
T14	403	0	0	0
T32	0	13	0	0
T43	0	7	0	0
T52	0	5	0	0
T55	0	12	0	0
T169	0	21	0	0
T245	0	11	0	0
T275	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1006	0	0
T1	13845	5	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	8	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	13	0	0
T9	573	0	0	0
T14	403	0	0	0
T32	0	13	0	0
T43	0	7	0	0
T52	0	5	0	0
T55	0	12	0	0
T169	0	21	0	0
T245	0	11	0	0
T275	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	80313	0	0
T1	13845	242	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	6	0	0
T6	5169	0	0	0
T7	502	0	0	0
T8	11331	462	0	0
T9	573	0	0	0
T14	403	0	0	0
T32	0	1094	0	0
T43	0	310	0	0
T52	0	284	0	0
T55	0	378	0	0
T169	0	1882	0	0
T245	0	475	0	0
T275	0	1229	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	893	0	0
T1	13845	4	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	13	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	12	0	0
T43	0	6	0	0
T52	0	5	0	0
T55	0	12	0	0
T169	0	13	0	0
T214	0	8	0	0
T245	0	9	0	0
T275	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T16,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T16,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T16,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T6,T1
1	1	Covered	T1,T16,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T12
0	1	Covered	T282,T283,T284
1	0	Covered	T102,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T12
0	1	Covered	T1,T16,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T12
1	-	Covered	T1,T16,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T16,T12
DetectSt	168	Covered	T1,T16,T12
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T16,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T16,T12
DebounceSt->IdleSt	163	Covered	T12,T275,T283
DetectSt->IdleSt	186	Covered	T282,T283,T284
DetectSt->StableSt	191	Covered	T1,T16,T12
IdleSt->DebounceSt	148	Covered	T1,T16,T12
StableSt->IdleSt	206	Covered	T1,T16,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T16,T12
0	1	Covered	T1,T16,T12
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T12
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T16,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T16,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T275,T283
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T16,T12
DetectSt	-	-	-	-	1	-	-	Covered	T282,T283,T284
DetectSt	-	-	-	-	0	1	-	Covered	T1,T16,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T16,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T16,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T16,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	764	0	0
CntIncr_A	7644258	41412	0	0
CntNoWrap_A	7644258	6941054	0	0
DetectStDropOut_A	7644258	81	0	0
DetectedOut_A	7644258	11404	0	0
DetectedPulseOut_A	7644258	269	0	0
DisabledIdleSt_A	7644258	6600308	0	0
DisabledNoDetection_A	7644258	6602128	0	0
EnterDebounceSt_A	7644258	410	0	0
EnterDetectSt_A	7644258	354	0	0
EnterStableSt_A	7644258	269	0	0
PulseIsPulse_A	7644258	269	0	0
StayInStableSt	7644258	11109	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	239	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	764	0	0
T1	13845	2	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	11	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	2	0	0
T32	0	4	0	0
T33	0	12	0	0
T43	0	2	0	0
T100	0	2	0	0
T101	0	4	0	0
T169	0	14	0	0
T245	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	41412	0	0
T1	13845	54	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	625	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	218	0	0
T32	0	144	0	0
T33	0	1098	0	0
T43	0	34	0	0
T100	0	113	0	0
T101	0	96	0	0
T169	0	245	0	0
T245	0	162	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941054	0	0
T1	13845	13436	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31757	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	81	0	0
T64	491	0	0	0
T109	5316	0	0	0
T111	0	7	0	0
T178	0	2	0	0
T187	0	7	0	0
T282	6160	1	0	0
T283	37844	8	0	0
T284	0	1	0	0
T285	0	10	0	0
T286	0	1	0	0
T287	0	2	0	0
T288	0	10	0	0
T289	50119	0	0	0
T290	487	0	0	0
T291	407	0	0	0
T292	437	0	0	0
T293	501	0	0	0
T294	454	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	11404	0	0
T1	13845	58	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	178	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	4	0	0
T32	0	118	0	0
T33	0	54	0	0
T43	0	53	0	0
T100	0	31	0	0
T101	0	8	0	0
T169	0	544	0	0
T245	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	269	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T43	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T169	0	7	0	0
T245	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6600308	0	0
T1	13845	13191	0	0
T2	5524	607	0	0
T3	10725	10309	0	0
T4	32180	31757	0	0
T5	8381	7964	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10453	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6602128	0	0
T1	13845	13194	0	0
T2	5524	620	0	0
T3	10725	10312	0	0
T4	32180	31769	0	0
T5	8381	7966	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10455	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	410	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	7	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T43	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T169	0	7	0	0
T245	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	354	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T43	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T169	0	7	0	0
T245	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	269	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T43	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T169	0	7	0	0
T245	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	269	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T43	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T169	0	7	0	0
T245	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	11109	0	0
T1	13845	57	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	174	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	3	0	0
T32	0	116	0	0
T33	0	48	0	0
T43	0	51	0	0
T100	0	30	0	0
T101	0	6	0	0
T169	0	530	0	0
T245	0	130	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	239	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	4	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	1	0	0
T32	0	2	0	0
T33	0	6	0	0
T100	0	1	0	0
T101	0	2	0	0
T172	0	2	0	0
T245	0	2	0	0
T275	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T6,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T5,T6,T72
1	0	Covered	T5,T3,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T8
0	1	Covered	T1,T4,T8
1	0	Covered	T3,T72,T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T1
DetectSt	168	Covered	T5,T6,T1
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T1
DebounceSt->IdleSt	163	Covered	T102,T276,T277
DetectSt->IdleSt	186	Covered	T5,T6,T3
DetectSt->StableSt	191	Covered	T1,T3,T4
IdleSt->DebounceSt	148	Covered	T5,T6,T1
StableSt->IdleSt	206	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T1
0	1	Covered	T5,T6,T1
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T1
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T276,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T1
DetectSt	-	-	-	-	1	-	-	Covered	T5,T6,T3
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T1
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	3108	0	0
CntIncr_A	7644258	116330	0	0
CntNoWrap_A	7644258	6938710	0	0
DetectStDropOut_A	7644258	344	0	0
DetectedOut_A	7644258	81373	0	0
DetectedPulseOut_A	7644258	928	0	0
DisabledIdleSt_A	7644258	6440241	0	0
DisabledNoDetection_A	7644258	6442463	0	0
EnterDebounceSt_A	7644258	1582	0	0
EnterDetectSt_A	7644258	1526	0	0
EnterStableSt_A	7644258	928	0	0
PulseIsPulse_A	7644258	928	0	0
StayInStableSt	7644258	80343	0	0
gen_high_event_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	816	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	3108	0	0
T1	13845	50	0	0
T2	5524	0	0	0
T3	10725	38	0	0
T4	32180	36	0	0
T5	8381	50	0	0
T6	5169	28	0	0
T7	502	0	0	0
T8	11331	10	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	44	0	0
T52	0	12	0	0
T55	0	48	0	0
T72	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	116330	0	0
T1	13845	1675	0	0
T2	5524	0	0	0
T3	10725	980	0	0
T4	32180	846	0	0
T5	8381	1157	0	0
T6	5169	708	0	0
T7	502	0	0	0
T8	11331	315	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	1078	0	0
T52	0	784	0	0
T55	0	1742	0	0
T72	0	972	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6938710	0	0
T1	13845	13388	0	0
T2	5524	607	0	0
T3	10725	10282	0	0
T4	32180	31721	0	0
T5	8381	7928	0	0
T6	5169	4740	0	0
T7	502	101	0	0
T8	11331	10918	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	344	0	0
T1	13845	0	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	17	0	0
T6	5169	14	0	0
T7	502	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T14	403	0	0	0
T52	0	1	0	0
T55	0	6	0	0
T72	0	8	0	0
T108	0	13	0	0
T109	0	12	0	0
T110	0	21	0	0
T169	0	8	0	0
T275	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	81373	0	0
T1	13845	877	0	0
T2	5524	0	0	0
T3	10725	2	0	0
T4	32180	2141	0	0
T8	11331	189	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	884	0	0
T43	0	1290	0	0
T55	0	7	0	0
T72	0	1	0	0
T245	0	2629	0	0
T280	0	424	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	928	0	0
T1	13845	25	0	0
T2	5524	0	0	0
T3	10725	2	0	0
T4	32180	18	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	12	0	0
T43	0	22	0	0
T55	0	7	0	0
T72	0	1	0	0
T245	0	24	0	0
T280	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6440241	0	0
T1	13845	8879	0	0
T2	5524	607	0	0
T3	10725	7495	0	0
T4	32180	25613	0	0
T5	8381	5471	0	0
T6	5169	2014	0	0
T7	502	101	0	0
T8	11331	5804	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6442463	0	0
T1	13845	8880	0	0
T2	5524	620	0	0
T3	10725	7497	0	0
T4	32180	25619	0	0
T5	8381	5472	0	0
T6	5169	2014	0	0
T7	502	102	0	0
T8	11331	5805	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1582	0	0
T1	13845	25	0	0
T2	5524	0	0	0
T3	10725	19	0	0
T4	32180	18	0	0
T5	8381	25	0	0
T6	5169	14	0	0
T7	502	0	0	0
T8	11331	5	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	22	0	0
T52	0	6	0	0
T55	0	24	0	0
T72	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1526	0	0
T1	13845	25	0	0
T2	5524	0	0	0
T3	10725	19	0	0
T4	32180	18	0	0
T5	8381	25	0	0
T6	5169	14	0	0
T7	502	0	0	0
T8	11331	5	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	22	0	0
T52	0	6	0	0
T55	0	24	0	0
T72	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	928	0	0
T1	13845	25	0	0
T2	5524	0	0	0
T3	10725	2	0	0
T4	32180	18	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	12	0	0
T43	0	22	0	0
T55	0	7	0	0
T72	0	1	0	0
T245	0	24	0	0
T280	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	928	0	0
T1	13845	25	0	0
T2	5524	0	0	0
T3	10725	2	0	0
T4	32180	18	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	12	0	0
T43	0	22	0	0
T55	0	7	0	0
T72	0	1	0	0
T245	0	24	0	0
T280	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	80343	0	0
T1	13845	850	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	2118	0	0
T8	11331	184	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	870	0	0
T43	0	1268	0	0
T214	0	5211	0	0
T245	0	2600	0	0
T280	0	412	0	0
T295	0	2066	0	0
T296	0	221	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	816	0	0
T1	13845	23	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	13	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	10	0	0
T43	0	22	0	0
T214	0	28	0	0
T245	0	19	0	0
T280	0	10	0	0
T295	0	20	0	0
T296	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T4,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T4,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T4,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T6,T1
1	1	Covered	T1,T4,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T12
0	1	Covered	T99,T100,T101
1	0	Covered	T102,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T12
0	1	Covered	T1,T4,T12
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T12
1	-	Covered	T1,T4,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T12
DetectSt	168	Covered	T1,T4,T12
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T4,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T4,T12
DebounceSt->IdleSt	163	Covered	T12,T66,T99
DetectSt->IdleSt	186	Covered	T99,T100,T101
DetectSt->StableSt	191	Covered	T1,T4,T12
IdleSt->DebounceSt	148	Covered	T1,T4,T12
StableSt->IdleSt	206	Covered	T1,T4,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T12
0	1	Covered	T1,T4,T12
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T12
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T4,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T66,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T12
DetectSt	-	-	-	-	1	-	-	Covered	T99,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T4,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	782	0	0
CntIncr_A	7644258	38545	0	0
CntNoWrap_A	7644258	6941036	0	0
DetectStDropOut_A	7644258	55	0	0
DetectedOut_A	7644258	12984	0	0
DetectedPulseOut_A	7644258	311	0	0
DisabledIdleSt_A	7644258	6603184	0	0
DisabledNoDetection_A	7644258	6605002	0	0
EnterDebounceSt_A	7644258	414	0	0
EnterDetectSt_A	7644258	370	0	0
EnterStableSt_A	7644258	311	0	0
PulseIsPulse_A	7644258	311	0	0
StayInStableSt	7644258	12647	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	283	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	782	0	0
T1	13845	2	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	10	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	5	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	2	0	0
T33	0	12	0	0
T66	0	11	0	0
T99	0	11	0	0
T100	0	19	0	0
T101	0	11	0	0
T245	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	38545	0	0
T1	13845	59	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	285	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	269	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	82	0	0
T33	0	804	0	0
T66	0	470	0	0
T99	0	544	0	0
T100	0	1404	0	0
T101	0	281	0	0
T245	0	252	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6941036	0	0
T1	13845	13436	0	0
T2	5524	607	0	0
T3	10725	10320	0	0
T4	32180	31747	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	55	0	0
T23	495	0	0	0
T40	3782	0	0	0
T57	1821	0	0	0
T71	503	0	0	0
T75	0	1	0	0
T99	26116	5	0	0
T100	0	9	0	0
T101	0	5	0	0
T108	5416	0	0	0
T121	0	5	0	0
T126	517	0	0	0
T127	502	0	0	0
T128	434	0	0	0
T129	424	0	0	0
T256	0	4	0	0
T282	0	1	0	0
T285	0	1	0	0
T286	0	5	0	0
T297	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	12984	0	0
T1	13845	51	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	335	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	101	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	49	0	0
T33	0	348	0	0
T66	0	390	0	0
T172	0	35	0	0
T245	0	338	0	0
T280	0	90	0	0
T283	0	241	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	311	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	5	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T66	0	5	0	0
T172	0	3	0	0
T245	0	4	0	0
T280	0	1	0	0
T283	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6603184	0	0
T1	13845	12563	0	0
T2	5524	607	0	0
T3	10725	10308	0	0
T4	32180	29621	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10739	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6605002	0	0
T1	13845	12565	0	0
T2	5524	620	0	0
T3	10725	10311	0	0
T4	32180	29628	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10741	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	414	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	5	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	3	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T66	0	6	0	0
T99	0	6	0	0
T100	0	10	0	0
T101	0	6	0	0
T245	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	370	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	5	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T66	0	5	0	0
T99	0	5	0	0
T100	0	9	0	0
T101	0	5	0	0
T245	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	311	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	5	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T66	0	5	0	0
T172	0	3	0	0
T245	0	4	0	0
T280	0	1	0	0
T283	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	311	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	5	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T66	0	5	0	0
T172	0	3	0	0
T245	0	4	0	0
T280	0	1	0	0
T283	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	12647	0	0
T1	13845	50	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	330	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	99	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	48	0	0
T33	0	342	0	0
T66	0	385	0	0
T172	0	32	0	0
T245	0	334	0	0
T280	0	88	0	0
T283	0	233	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	283	0	0
T1	13845	1	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	5	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	2	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	1	0	0
T33	0	6	0	0
T66	0	5	0	0
T172	0	3	0	0
T214	0	1	0	0
T245	0	4	0	0
T283	0	8	0	0