Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T1

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T6,T1

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T5,T6,T108
1	0	Covered	T5,T245,T275

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T280,T54,T298

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T1
DetectSt	168	Covered	T5,T6,T1
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T1
DebounceSt->IdleSt	163	Covered	T102,T276,T277
DetectSt->IdleSt	186	Covered	T5,T6,T108
DetectSt->StableSt	191	Covered	T1,T3,T4
IdleSt->DebounceSt	148	Covered	T5,T6,T1
StableSt->IdleSt	206	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T1
0	1	Covered	T5,T6,T1
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T1
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T1
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T276,T277
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T1
DetectSt	-	-	-	-	1	-	-	Covered	T5,T6,T108
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T1
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	2953	0	0
CntIncr_A	7644258	108629	0	0
CntNoWrap_A	7644258	6938865	0	0
DetectStDropOut_A	7644258	301	0	0
DetectedOut_A	7644258	70043	0	0
DetectedPulseOut_A	7644258	908	0	0
DisabledIdleSt_A	7644258	6443986	0	0
DisabledNoDetection_A	7644258	6446211	0	0
EnterDebounceSt_A	7644258	1500	0	0
EnterDetectSt_A	7644258	1453	0	0
EnterStableSt_A	7644258	908	0	0
PulseIsPulse_A	7644258	908	0	0
StayInStableSt	7644258	69036	0	0
gen_high_event_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	771	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	2953	0	0
T1	13845	20	0	0
T2	5524	0	0	0
T3	10725	36	0	0
T4	32180	38	0	0
T5	8381	62	0	0
T6	5169	62	0	0
T7	502	0	0	0
T8	11331	10	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	20	0	0
T52	0	20	0	0
T55	0	50	0	0
T72	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	108629	0	0
T1	13845	440	0	0
T2	5524	0	0	0
T3	10725	648	0	0
T4	32180	874	0	0
T5	8381	1443	0	0
T6	5169	1588	0	0
T7	502	0	0	0
T8	11331	430	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	560	0	0
T52	0	950	0	0
T55	0	1450	0	0
T72	0	986	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6938865	0	0
T1	13845	13418	0	0
T2	5524	607	0	0
T3	10725	10284	0	0
T4	32180	31719	0	0
T5	8381	7916	0	0
T6	5169	4706	0	0
T7	502	101	0	0
T8	11331	10918	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	301	0	0
T1	13845	0	0	0
T2	5524	0	0	0
T3	10725	0	0	0
T4	32180	0	0	0
T5	8381	13	0	0
T6	5169	31	0	0
T7	502	0	0	0
T8	11331	0	0	0
T9	573	0	0	0
T14	403	0	0	0
T108	0	9	0	0
T109	0	10	0	0
T110	0	6	0	0
T112	0	6	0	0
T114	0	12	0	0
T115	0	11	0	0
T214	0	3	0	0
T275	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	70043	0	0
T1	13845	530	0	0
T2	5524	0	0	0
T3	10725	1067	0	0
T4	32180	2721	0	0
T8	11331	71	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	766	0	0
T43	0	449	0	0
T52	0	1850	0	0
T55	0	1652	0	0
T72	0	2252	0	0
T169	0	2142	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	908	0	0
T1	13845	10	0	0
T2	5524	0	0	0
T3	10725	18	0	0
T4	32180	19	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	10	0	0
T43	0	10	0	0
T52	0	10	0	0
T55	0	25	0	0
T72	0	29	0	0
T169	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6443986	0	0
T1	13845	9402	0	0
T2	5524	607	0	0
T3	10725	6679	0	0
T4	32180	25096	0	0
T5	8381	5471	0	0
T6	5169	2015	0	0
T7	502	101	0	0
T8	11331	5808	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6446211	0	0
T1	13845	9404	0	0
T2	5524	620	0	0
T3	10725	6679	0	0
T4	32180	25100	0	0
T5	8381	5472	0	0
T6	5169	2015	0	0
T7	502	102	0	0
T8	11331	5809	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1500	0	0
T1	13845	10	0	0
T2	5524	0	0	0
T3	10725	18	0	0
T4	32180	19	0	0
T5	8381	31	0	0
T6	5169	31	0	0
T7	502	0	0	0
T8	11331	5	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	10	0	0
T52	0	10	0	0
T55	0	25	0	0
T72	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	1453	0	0
T1	13845	10	0	0
T2	5524	0	0	0
T3	10725	18	0	0
T4	32180	19	0	0
T5	8381	31	0	0
T6	5169	31	0	0
T7	502	0	0	0
T8	11331	5	0	0
T9	573	0	0	0
T14	403	0	0	0
T43	0	10	0	0
T52	0	10	0	0
T55	0	25	0	0
T72	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	908	0	0
T1	13845	10	0	0
T2	5524	0	0	0
T3	10725	18	0	0
T4	32180	19	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	10	0	0
T43	0	10	0	0
T52	0	10	0	0
T55	0	25	0	0
T72	0	29	0	0
T169	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	908	0	0
T1	13845	10	0	0
T2	5524	0	0	0
T3	10725	18	0	0
T4	32180	19	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	10	0	0
T43	0	10	0	0
T52	0	10	0	0
T55	0	25	0	0
T72	0	29	0	0
T169	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	69036	0	0
T1	13845	519	0	0
T2	5524	0	0	0
T3	10725	1047	0	0
T4	32180	2695	0	0
T8	11331	66	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	755	0	0
T43	0	438	0	0
T52	0	1840	0	0
T55	0	1627	0	0
T72	0	2220	0	0
T169	0	2108	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	771	0	0
T1	13845	9	0	0
T2	5524	0	0	0
T3	10725	16	0	0
T4	32180	12	0	0
T8	11331	5	0	0
T9	573	0	0	0
T10	1440	0	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	0	0	0
T32	0	9	0	0
T43	0	9	0	0
T52	0	10	0	0
T55	0	25	0	0
T72	0	26	0	0
T169	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T4,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T3,T4,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T4,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T6,T1
1	1	Covered	T3,T4,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T16
0	1	Covered	T100,T283,T299
1	0	Covered	T102,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T16
0	1	Covered	T4,T16,T12
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T16
1	-	Covered	T4,T16,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T16
DetectSt	168	Covered	T3,T4,T16
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T3,T4,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T16
DebounceSt->IdleSt	163	Covered	T16,T12,T33
DetectSt->IdleSt	186	Covered	T100,T283,T299
DetectSt->StableSt	191	Covered	T3,T4,T16
IdleSt->DebounceSt	148	Covered	T3,T4,T16
StableSt->IdleSt	206	Covered	T3,T4,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T16
0	1	Covered	T3,T4,T16
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T16
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T102,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T12,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T16
DetectSt	-	-	-	-	1	-	-	Covered	T100,T283,T299
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T16
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T16
StableSt	-	-	-	-	-	-	1	Covered	T4,T16,T12
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7644258	833	0	0
CntIncr_A	7644258	43583	0	0
CntNoWrap_A	7644258	6940985	0	0
DetectStDropOut_A	7644258	101	0	0
DetectedOut_A	7644258	13409	0	0
DetectedPulseOut_A	7644258	289	0	0
DisabledIdleSt_A	7644258	6623887	0	0
DisabledNoDetection_A	7644258	6625732	0	0
EnterDebounceSt_A	7644258	439	0	0
EnterDetectSt_A	7644258	395	0	0
EnterStableSt_A	7644258	289	0	0
PulseIsPulse_A	7644258	289	0	0
StayInStableSt	7644258	13078	0	0
gen_high_level_sva.HighLevelEvent_A	7644258	6944236	0	0
gen_not_sticky_sva.StableStDropOut_A	7644258	244	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	833	0	0
T3	10725	4	0	0
T4	32180	12	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	11	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	13	0	0
T24	502	0	0	0
T32	0	4	0	0
T33	0	5	0	0
T43	0	2	0	0
T52	0	4	0	0
T59	423	0	0	0
T66	0	20	0	0
T72	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	43583	0	0
T3	10725	56	0	0
T4	32180	252	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	498	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	850	0	0
T24	502	0	0	0
T32	0	108	0	0
T33	0	421	0	0
T43	0	54	0	0
T52	0	154	0	0
T59	423	0	0	0
T66	0	1031	0	0
T72	0	198	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6940985	0	0
T1	13845	13438	0	0
T2	5524	607	0	0
T3	10725	10316	0	0
T4	32180	31745	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10928	0	0
T9	573	172	0	0
T14	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	101	0	0
T39	554	0	0	0
T47	7927	0	0	0
T48	657	0	0	0
T100	11940	3	0	0
T101	4615	0	0	0
T119	0	3	0	0
T170	523	0	0	0
T171	528	0	0	0
T172	25186	0	0	0
T178	0	5	0	0
T283	0	2	0	0
T286	0	3	0	0
T299	0	12	0	0
T300	0	5	0	0
T301	0	3	0	0
T302	0	3	0	0
T303	0	5	0	0
T304	446	0	0	0
T305	414	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	13409	0	0
T3	10725	138	0	0
T4	32180	492	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	335	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	581	0	0
T24	502	0	0	0
T32	0	157	0	0
T33	0	45	0	0
T43	0	34	0	0
T52	0	133	0	0
T59	423	0	0	0
T66	0	537	0	0
T72	0	140	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	289	0	0
T3	10725	2	0	0
T4	32180	6	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	5	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	6	0	0
T24	502	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	2	0	0
T59	423	0	0	0
T66	0	9	0	0
T72	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6623887	0	0
T1	13845	12909	0	0
T2	5524	607	0	0
T3	10725	9252	0	0
T4	32180	29043	0	0
T5	8381	7978	0	0
T6	5169	4768	0	0
T7	502	101	0	0
T8	11331	10857	0	0
T9	573	172	0	0
T14	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6625732	0	0
T1	13845	12912	0	0
T2	5524	620	0	0
T3	10725	9253	0	0
T4	32180	29048	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10859	0	0
T9	573	173	0	0
T14	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	439	0	0
T3	10725	2	0	0
T4	32180	6	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	6	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	7	0	0
T24	502	0	0	0
T32	0	2	0	0
T33	0	3	0	0
T43	0	1	0	0
T52	0	2	0	0
T59	423	0	0	0
T66	0	11	0	0
T72	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	395	0	0
T3	10725	2	0	0
T4	32180	6	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	5	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	6	0	0
T24	502	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	2	0	0
T59	423	0	0	0
T66	0	9	0	0
T72	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	289	0	0
T3	10725	2	0	0
T4	32180	6	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	5	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	6	0	0
T24	502	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	2	0	0
T59	423	0	0	0
T66	0	9	0	0
T72	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	289	0	0
T3	10725	2	0	0
T4	32180	6	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	5	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	6	0	0
T24	502	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	2	0	0
T59	423	0	0	0
T66	0	9	0	0
T72	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	13078	0	0
T3	10725	134	0	0
T4	32180	486	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T12	0	330	0	0
T14	403	0	0	0
T15	427	0	0	0
T16	13925	575	0	0
T24	502	0	0	0
T32	0	155	0	0
T33	0	43	0	0
T43	0	32	0	0
T52	0	131	0	0
T59	423	0	0	0
T66	0	528	0	0
T72	0	134	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	6944236	0	0
T1	13845	13442	0	0
T2	5524	620	0	0
T3	10725	10323	0	0
T4	32180	31769	0	0
T5	8381	7980	0	0
T6	5169	4769	0	0
T7	502	102	0	0
T8	11331	10930	0	0
T9	573	173	0	0
T14	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7644258	244	0	0
T4	32180	6	0	0
T8	11331	0	0	0
T9	573	0	0	0
T10	1440	0	0	0
T11	545	0	0	0
T12	21029	5	0	0
T15	427	0	0	0
T16	13925	6	0	0
T24	502	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T52	0	2	0	0
T59	423	0	0	0
T66	0	9	0	0
T99	0	10	0	0
T172	0	5	0	0
T282	0	1	0	0