Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1280309378	10224	0	0
auto_block_debounce_ctl_rd_A	1280309378	1925	0	0
auto_block_out_ctl_rd_A	1280309378	2746	0	0
com_det_ctl_0_rd_A	1280309378	3974	0	0
com_det_ctl_1_rd_A	1280309378	4160	0	0
com_det_ctl_2_rd_A	1280309378	4129	0	0
com_det_ctl_3_rd_A	1280309378	4275	0	0
com_out_ctl_0_rd_A	1280309378	4549	0	0
com_out_ctl_1_rd_A	1280309378	4622	0	0
com_out_ctl_2_rd_A	1280309378	4824	0	0
com_out_ctl_3_rd_A	1280309378	4793	0	0
com_pre_det_ctl_0_rd_A	1280309378	1343	0	0
com_pre_det_ctl_1_rd_A	1280309378	1441	0	0
com_pre_det_ctl_2_rd_A	1280309378	1299	0	0
com_pre_det_ctl_3_rd_A	1280309378	1382	0	0
com_pre_sel_ctl_0_rd_A	1280309378	4775	0	0
com_pre_sel_ctl_1_rd_A	1280309378	5083	0	0
com_pre_sel_ctl_2_rd_A	1280309378	4796	0	0
com_pre_sel_ctl_3_rd_A	1280309378	4849	0	0
com_sel_ctl_0_rd_A	1280309378	4854	0	0
com_sel_ctl_1_rd_A	1280309378	4933	0	0
com_sel_ctl_2_rd_A	1280309378	4762	0	0
com_sel_ctl_3_rd_A	1280309378	4896	0	0
ec_rst_ctl_rd_A	1280309378	2378	0	0
intr_enable_rd_A	1280309378	2183	0	0
key_intr_ctl_rd_A	1280309378	4418	0	0
key_intr_debounce_ctl_rd_A	1280309378	1569	0	0
key_invert_ctl_rd_A	1280309378	4969	0	0
pin_allowed_ctl_rd_A	1280309378	5291	0	0
pin_out_ctl_rd_A	1280309378	4057	0	0
pin_out_value_rd_A	1280309378	3918	0	0
regwen_rd_A	1280309378	1649	0	0
ulp_ac_debounce_ctl_rd_A	1280309378	1528	0	0
ulp_ctl_rd_A	1280309378	1564	0	0
ulp_lid_debounce_ctl_rd_A	1280309378	1511	0	0
ulp_pwrb_debounce_ctl_rd_A	1280309378	1690	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	10224	0	0
T2	269667	12	0	0
T3	429032	0	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	4	0	0
T22	0	9	0	0
T35	0	8	0	0
T45	0	12	0	0
T47	0	16	0	0
T59	101692	0	0	0
T75	0	5	0	0
T183	0	10	0	0
T215	0	28	0	0
T308	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1925	0	0
T20	0	15	0	0
T21	122437	0	0	0
T25	41349	10	0	0
T26	71815	16	0	0
T32	706669	0	0	0
T36	80269	0	0	0
T47	0	12	0	0
T49	82712	0	0	0
T50	53261	0	0	0
T51	211289	0	0	0
T52	180939	0	0	0
T53	808389	0	0	0
T183	0	39	0	0
T219	0	10	0	0
T272	0	13	0	0
T308	0	4	0	0
T309	0	18	0	0
T310	0	4	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	2746	0	0
T20	0	20	0	0
T21	122437	0	0	0
T25	41349	10	0	0
T26	71815	21	0	0
T32	706669	0	0	0
T36	80269	0	0	0
T47	0	31	0	0
T49	82712	0	0	0
T50	53261	0	0	0
T51	211289	0	0	0
T52	180939	0	0	0
T53	808389	0	0	0
T183	0	41	0	0
T219	0	18	0	0
T272	0	7	0	0
T308	0	16	0	0
T309	0	22	0	0
T310	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	3974	0	0
T1	166151	58	0	0
T2	269667	0	0	0
T3	429032	51	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	61	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	13	0	0
T43	0	71	0	0
T52	0	60	0	0
T72	0	49	0	0
T99	0	65	0	0
T169	0	97	0	0
T245	0	62	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4160	0	0
T1	166151	87	0	0
T2	269667	0	0	0
T3	429032	59	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	80	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	7	0	0
T43	0	72	0	0
T52	0	86	0	0
T72	0	71	0	0
T99	0	51	0	0
T169	0	81	0	0
T245	0	62	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4129	0	0
T1	166151	57	0	0
T2	269667	0	0	0
T3	429032	48	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	71	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	14	0	0
T43	0	75	0	0
T52	0	67	0	0
T72	0	59	0	0
T99	0	41	0	0
T169	0	84	0	0
T245	0	81	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4275	0	0
T1	166151	70	0	0
T2	269667	0	0	0
T3	429032	33	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	76	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	11	0	0
T43	0	74	0	0
T52	0	74	0	0
T72	0	49	0	0
T99	0	49	0	0
T169	0	99	0	0
T245	0	48	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4549	0	0
T1	166151	70	0	0
T2	269667	0	0	0
T3	429032	30	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	59	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	17	0	0
T43	0	54	0	0
T52	0	62	0	0
T72	0	46	0	0
T99	0	48	0	0
T169	0	84	0	0
T245	0	64	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4622	0	0
T1	166151	70	0	0
T2	269667	0	0	0
T3	429032	40	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	59	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	15	0	0
T43	0	61	0	0
T52	0	68	0	0
T72	0	67	0	0
T99	0	77	0	0
T169	0	65	0	0
T245	0	76	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4824	0	0
T1	166151	54	0	0
T2	269667	0	0	0
T3	429032	54	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	95	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	3	0	0
T43	0	59	0	0
T52	0	59	0	0
T72	0	46	0	0
T99	0	92	0	0
T169	0	118	0	0
T245	0	46	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4793	0	0
T1	166151	61	0	0
T2	269667	0	0	0
T3	429032	40	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	96	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	29	0	0
T43	0	57	0	0
T52	0	62	0	0
T72	0	55	0	0
T99	0	46	0	0
T169	0	110	0	0
T245	0	50	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1343	0	0
T20	912923	21	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	8	0	0
T58	221442	0	0	0
T125	0	16	0	0
T169	391688	0	0	0
T183	0	38	0	0
T198	63426	0	0	0
T227	0	37	0	0
T237	0	25	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	9	0	0
T311	0	18	0	0
T312	0	9	0	0
T313	0	12	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1441	0	0
T20	912923	18	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	13	0	0
T58	221442	0	0	0
T125	0	29	0	0
T169	391688	0	0	0
T183	0	43	0	0
T198	63426	0	0	0
T227	0	44	0	0
T237	0	39	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	8	0	0
T311	0	28	0	0
T312	0	12	0	0
T313	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1299	0	0
T20	912923	10	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	5	0	0
T58	221442	0	0	0
T125	0	16	0	0
T169	391688	0	0	0
T183	0	50	0	0
T198	63426	0	0	0
T227	0	53	0	0
T237	0	22	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	13	0	0
T311	0	27	0	0
T312	0	11	0	0
T313	0	19	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1382	0	0
T20	912923	17	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	6	0	0
T58	221442	0	0	0
T125	0	14	0	0
T169	391688	0	0	0
T183	0	31	0	0
T198	63426	0	0	0
T227	0	27	0	0
T237	0	18	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	10	0	0
T311	0	24	0	0
T312	0	8	0	0
T313	0	27	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4775	0	0
T1	166151	76	0	0
T2	269667	0	0	0
T3	429032	49	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	66	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	12	0	0
T43	0	66	0	0
T52	0	76	0	0
T72	0	56	0	0
T99	0	58	0	0
T169	0	86	0	0
T245	0	51	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	5083	0	0
T1	166151	59	0	0
T2	269667	0	0	0
T3	429032	57	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	68	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	21	0	0
T43	0	84	0	0
T52	0	59	0	0
T72	0	43	0	0
T99	0	78	0	0
T169	0	91	0	0
T245	0	67	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4796	0	0
T1	166151	63	0	0
T2	269667	0	0	0
T3	429032	66	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	75	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	16	0	0
T43	0	55	0	0
T52	0	88	0	0
T72	0	64	0	0
T99	0	79	0	0
T169	0	84	0	0
T245	0	65	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4849	0	0
T1	166151	54	0	0
T2	269667	0	0	0
T3	429032	68	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	62	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	10	0	0
T43	0	56	0	0
T52	0	75	0	0
T72	0	67	0	0
T99	0	53	0	0
T169	0	70	0	0
T245	0	73	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4854	0	0
T1	166151	65	0	0
T2	269667	0	0	0
T3	429032	51	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	90	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	4	0	0
T43	0	67	0	0
T52	0	81	0	0
T72	0	54	0	0
T99	0	59	0	0
T169	0	112	0	0
T245	0	66	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4933	0	0
T1	166151	63	0	0
T2	269667	0	0	0
T3	429032	45	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	68	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	9	0	0
T43	0	47	0	0
T52	0	65	0	0
T72	0	47	0	0
T99	0	68	0	0
T169	0	94	0	0
T245	0	55	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4762	0	0
T1	166151	57	0	0
T2	269667	0	0	0
T3	429032	56	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	74	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	13	0	0
T43	0	61	0	0
T52	0	72	0	0
T72	0	44	0	0
T99	0	67	0	0
T169	0	92	0	0
T245	0	60	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4896	0	0
T1	166151	62	0	0
T2	269667	0	0	0
T3	429032	40	0	0
T4	804509	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T10	250520	0	0	0
T12	0	65	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	18	0	0
T43	0	64	0	0
T52	0	63	0	0
T72	0	66	0	0
T99	0	74	0	0
T169	0	67	0	0
T245	0	43	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	2378	0	0
T1	166151	11	0	0
T2	269667	0	0	0
T3	429032	15	0	0
T4	804509	0	0	0
T6	620364	4	0	0
T7	193496	0	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T12	0	32	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T43	0	12	0	0
T52	0	10	0	0
T53	0	3	0	0
T72	0	17	0	0
T99	0	52	0	0
T196	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	2183	0	0
T20	912923	25	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	34	0	0
T58	221442	0	0	0
T169	391688	0	0	0
T183	0	36	0	0
T198	63426	0	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T272	0	18	0	0
T308	0	46	0	0
T311	0	47	0	0
T312	0	25	0	0
T314	0	50	0	0
T315	0	13	0	0
T316	0	20	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4418	0	0
T11	227094	8	0	0
T12	262868	0	0	0
T13	304832	0	0	0
T20	0	26	0	0
T33	284928	0	0	0
T34	0	1	0	0
T43	136937	0	0	0
T47	0	20	0	0
T68	133699	0	0	0
T69	49965	0	0	0
T79	509272	0	0	0
T86	105688	0	0	0
T89	16860	0	0	0
T177	0	3	0	0
T183	0	44	0	0
T212	0	2	0	0
T308	0	14	0	0
T311	0	22	0	0
T317	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1569	0	0
T20	912923	5	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	19	0	0
T58	221442	0	0	0
T125	0	25	0	0
T169	391688	0	0	0
T183	0	40	0	0
T198	63426	0	0	0
T227	0	46	0	0
T237	0	6	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	9	0	0
T311	0	26	0	0
T312	0	10	0	0
T313	0	20	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4969	0	0
T20	912923	8	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	80	0	0
T58	221442	0	0	0
T150	0	41	0	0
T169	391688	0	0	0
T183	0	131	0	0
T198	63426	0	0	0
T220	0	67	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	179	0	0
T309	0	48	0	0
T311	0	76	0	0
T318	0	39	0	0
T319	0	81	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	5291	0	0
T1	166151	0	0	0
T2	269667	0	0	0
T3	429032	0	0	0
T4	804509	0	0	0
T7	193496	83	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	77	0	0
T47	0	19	0	0
T53	0	26	0	0
T183	0	29	0	0
T198	0	10	0	0
T308	0	51	0	0
T320	0	76	0	0
T321	0	73	0	0
T322	0	74	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	4057	0	0
T1	166151	0	0	0
T2	269667	0	0	0
T3	429032	0	0	0
T4	804509	0	0	0
T7	193496	77	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	85	0	0
T47	0	17	0	0
T53	0	45	0	0
T183	0	36	0	0
T198	0	53	0	0
T308	0	77	0	0
T320	0	86	0	0
T321	0	86	0	0
T322	0	75	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	3918	0	0
T1	166151	0	0	0
T2	269667	0	0	0
T3	429032	0	0	0
T4	804509	0	0	0
T7	193496	64	0	0
T8	538288	0	0	0
T9	211292	0	0	0
T14	189570	0	0	0
T15	47091	0	0	0
T16	696278	0	0	0
T20	0	94	0	0
T47	0	14	0	0
T53	0	39	0	0
T183	0	38	0	0
T198	0	52	0	0
T308	0	89	0	0
T320	0	72	0	0
T321	0	43	0	0
T322	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1649	0	0
T20	912923	12	0	0
T41	123041	0	0	0
T45	285035	0	0	0
T46	315265	0	0	0
T47	0	19	0	0
T58	221442	0	0	0
T125	0	27	0	0
T169	391688	0	0	0
T183	0	37	0	0
T198	63426	0	0	0
T227	0	34	0	0
T237	0	18	0	0
T245	983368	0	0	0
T246	38396	0	0	0
T247	48913	0	0	0
T308	0	20	0	0
T311	0	24	0	0
T312	0	16	0	0
T313	0	12	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1528	0	0
T20	0	26	0	0
T21	122437	0	0	0
T25	41349	0	0	0
T26	71815	0	0	0
T36	80269	0	0	0
T47	0	19	0	0
T49	82712	0	0	0
T50	53261	0	0	0
T51	211289	0	0	0
T52	180939	0	0	0
T53	808389	0	0	0
T56	105339	8	0	0
T57	0	9	0	0
T58	0	1	0	0
T137	0	9	0	0
T138	0	12	0	0
T183	0	30	0	0
T308	0	22	0	0
T323	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1564	0	0
T20	0	31	0	0
T21	122437	0	0	0
T25	41349	0	0	0
T26	71815	0	0	0
T36	80269	0	0	0
T47	0	13	0	0
T49	82712	0	0	0
T50	53261	0	0	0
T51	211289	0	0	0
T52	180939	0	0	0
T53	808389	0	0	0
T56	105339	6	0	0
T57	0	9	0	0
T58	0	4	0	0
T137	0	3	0	0
T138	0	1	0	0
T183	0	34	0	0
T308	0	10	0	0
T323	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1511	0	0
T20	0	32	0	0
T21	122437	0	0	0
T25	41349	0	0	0
T26	71815	0	0	0
T36	80269	0	0	0
T47	0	18	0	0
T49	82712	0	0	0
T50	53261	0	0	0
T51	211289	0	0	0
T52	180939	0	0	0
T53	808389	0	0	0
T56	105339	1	0	0
T57	0	8	0	0
T58	0	3	0	0
T137	0	12	0	0
T138	0	5	0	0
T183	0	34	0	0
T308	0	14	0	0
T323	0	6	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280309378	1690	0	0
T20	0	30	0	0
T21	122437	0	0	0
T25	41349	0	0	0
T26	71815	0	0	0
T36	80269	0	0	0
T47	0	22	0	0
T49	82712	0	0	0
T50	53261	0	0	0
T51	211289	0	0	0
T52	180939	0	0	0
T53	808389	0	0	0
T56	105339	7	0	0
T58	0	7	0	0
T137	0	9	0	0
T138	0	9	0	0
T183	0	42	0	0
T269	0	5	0	0
T308	0	12	0	0
T323	0	5	0	0