Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T1

16

T27

5

T5

42

auto[1]

634

1

T27

3

T5

6

T12

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1928

1

T1

14

T27

8

T5

48

auto[1]

641

1

T1

2

T12

11

T93

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1939

1

T1

14

T5

38

T12

12

auto[1]

630

1

T1

2

T27

8

T5

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1924

1

T1

14

T5

32

T12

16

auto[1]

645

1

T1

2

T27

8

T5

16

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2372

1

T1

8

T27

8

T5

45

auto[1]

197

1

T1

8

T5

3

T69

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T1

16

T27

8

T5

32

auto[1]

275

1

T5

16

T33

7

T69

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2382

1

T1

16

T27

8

T5

48

auto[1]

187

1

T32

4

T70

3

T122

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2347

1

T1

12

T27

8

T5

45

auto[1]

222

1

T1

4

T5

3

T70

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2375

1

T1

12

T27

8

T5

42

auto[1]

194

1

T1

4

T5

6

T33

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2006

1

T1

12

T27

5

T5

35

auto[1]

563

1

T1

4

T27

3

T5

13

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	916	1			T27	8		T12	26		T34	13
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	32	1			T69	8		T212	3		T86	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	47	1			T33	5		T32	5		T367	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	55	1			T1	4		T122	5		T100	14
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	49	1			T70	4		T377	3		T378	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	33	1			T1	4		T5	3		T272	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	15	1			T182	1		T117	4		T371	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T379	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	55	1			T269	4		T98	4		T378	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T70	1		T380	2		T369	7
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	9	1			T32	4		T272	2		T379	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T381	2		T382	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	37	1			T367	1		T379	4		T383	3
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T247	5		T372	3		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T369	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	134	1			T5	10		T33	7		T69	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	30	1			T202	7		T206	1		T384	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	17	1			T5	6		T86	4		T385	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	3	1			T70	1		T107	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	29	1			T386	6		T385	5		T178	14
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	9	1			T100	4		T387	5		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	10	1			T122	3		T386	2		T202	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	13	1			T212	1		T377	1		T276	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T388	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T276	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T386	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T122	1		T389	3		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

123

1

T78

9

T122

1

T59

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

67

1

T1

4

T5

3

T354

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

70

1

T191

7

T277

5

T390

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

105

1

T32

5

T191

14

T212

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

42

1

T5

6

T98

4

T364

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

81

1

T34

4

T69

4

T70

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T34

1

T359

1

T391

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

107

1

T1

2

T12

12

T33

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

81

1

T34

6

T93

3

T69

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

74

1

T33

7

T100

4

T224

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T358

4

T366

3

T167

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

71

1

T27

5

T12

3

T224

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T94

1

T357

4

T86

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32

1

T5

10

T34

2

T277

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T27

3

T360

1

T83

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

149

1

T122

5

T359

10

T101

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T32

4

T269

4

T392

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T12

1

T391

5

T378

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T224

1

T367

1

T167

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T1

2

T12

4

T191

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

49

1

T12

3

T93

3

T191

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T112

2

T191

2

T366

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T191

1

T393

1

T184

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T277

4

T212

3

T367

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T93

3

T94

2

T112

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T12

3

T94

3

T78

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T278

2

T366

1

T184

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T35

2

T393

1

T321

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T35

2

T357

3

T83

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T69

4

T314

1

T358

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T112

1

T354

1

T360

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded