Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T13

10

T17

11

T65

10

auto[1]

1075

1

T13

10

T17

9

T65

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T13

3

T17

4

T65

6

from_0to1

520

1

T13

4

T17

5

T65

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T13

10

T17

8

T65

9

auto[1]

1124

1

T13

10

T17

12

T65

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T13

10

T17

9

T65

9

auto[1]

1092

1

T13

10

T17

11

T65

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T17

1

T65

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T65

2

T58

2

T199

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T13

2

T66

1

T199

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T66

1

T58

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T58

1

T67

1

T199

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T13

1

T17

1

T58

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T65

2

T58

1

T196

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T13

1

T65

2

T58

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T13

1

T65

1

T199

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T65

1

T67

1

T285

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T17

1

T196

1

T199

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T17

2

T65

1

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T17

1

T66

3

T58

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T17

2

T65

2

T196

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T13

1

T17

1

T196

2

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T13

1

T59

2

T50

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T13

13

T17

12

T65

11

auto[1]

1035

1

T13

7

T17

8

T65

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T13

6

T17

4

T65

4

from_0to1

515

1

T13

6

T17

4

T65

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T13

12

T17

6

T65

12

auto[1]

1117

1

T13

8

T17

14

T65

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T13

10

T17

10

T65

8

auto[1]

1076

1

T13

10

T17

10

T65

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T13

1

T17

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T13

1

T65

1

T58

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T66

1

T58

1

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T13

2

T17

2

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T13

3

T17

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T13

1

T17

2

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T13

1

T17

1

T58

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T65

2

T66

1

T59

2

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T13

1

T66

2

T58

1

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T65

2

T67

1

T199

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T65

1

T196

2

T59

2

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T13

1

T17

1

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T285

1

T50

1

T51

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T13

1

T66

1

T199

2

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T66

1

T67

1

T196

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T65

1

T196

1

T285

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T13

8

T17

8

T65

8

auto[1]

1097

1

T13

12

T17

12

T65

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T13

8

T17

5

T65

6

from_0to1

524

1

T13

8

T17

5

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T13

13

T17

13

T65

8

auto[1]

1102

1

T13

7

T17

7

T65

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T13

12

T17

14

T65

12

auto[1]

1102

1

T13

8

T17

6

T65

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T13

2

T65

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T13

1

T196

1

T199

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T58

2

T67

1

T199

2

auto[0]

from_1to0

auto[1]

auto[1]

82

1

T13

1

T17

1

T65

2

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T13

1

T17

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T17

1

T65

1

T66

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T65

1

T66

1

T58

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T13

1

T65

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T13

2

T17

2

T285

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T13

1

T17

1

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T13

1

T17

1

T65

3

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T58

1

T67

1

T196

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T13

2

T17

1

T65

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T13

2

T58

1

T59

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T13

1

T17

2

T66

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T13

1

T51

2

T38

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T13

10

T17

12

T65

12

auto[1]

1081

1

T13

10

T17

8

T65

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T13

4

T17

7

T65

6

from_0to1

521

1

T13

4

T17

6

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T13

12

T17

14

T65

8

auto[1]

1100

1

T13

8

T17

6

T65

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T13

10

T17

10

T65

14

auto[1]

1095

1

T13

10

T17

10

T65

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T13

1

T17

2

T66

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T66

1

T58

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T65

3

T67

1

T199

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T13

1

T17

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T65

1

T66

2

T196

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T17

2

T66

2

T196

1

auto[0]

from_0to1

auto[1]

auto[0]

84

1

T17

1

T67

2

T196

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T13

1

T17

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T13

2

T17

3

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T17

1

T196

2

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T65

1

T58

1

T196

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T66

1

T58

1

T285

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T13

1

T17

1

T58

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T17

1

T65

2

T58

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T13

2

T58

1

T199

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T65

1

T66

1

T199

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T13

10

T17

13

T65

12

auto[1]

1087

1

T13

10

T17

7

T65

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

542

1

T13

4

T17

3

T65

4

from_0to1

547

1

T13

5

T17

3

T65

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1076

1

T13

9

T17

9

T65

3

auto[1]

1135

1

T13

11

T17

11

T65

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T13

12

T17

4

T65

14

auto[1]

1136

1

T13

8

T17

16

T65

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T66

1

T58

1

T196

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T17

1

T58

2

T196

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T13

1

T65

1

T199

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T17

2

T65

1

T66

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T66

1

T199

1

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T65

1

T66

3

T196

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T13

1

T65

1

T58

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T13

2

T17

2

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T13

2

T66

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T66

1

T67

2

T199

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T13

1

T65

2

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T58

1

T285

1

T59

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T66

1

T58

2

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T67

2

T50

1

T191

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T13

1

T17

1

T65

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T13

1

T65

1

T58

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T13

9

T17

12

T65

5

auto[1]

1117

1

T13

11

T17

8

T65

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T13

6

T17

5

T65

6

from_0to1

543

1

T13

7

T17

4

T65

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T13

10

T17

11

T65

11

auto[1]

1092

1

T13

10

T17

9

T65

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T13

6

T17

9

T65

8

auto[1]

1110

1

T13

14

T17

11

T65

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T17

1

T65

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T13

2

T65

1

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T13

1

T17

1

T67

2

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T17

1

T65

1

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T17

1

T66

1

T58

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T58

2

T67

2

T196

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T66

4

T199

2

T191

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T13

3

T17

2

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T13

2

T17

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T17

1

T65

1

T66

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T196

1

T199

1

T59

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T13

1

T65

1

T58

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T65

1

T66

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T13

2

T17

1

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T13

1

T65

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T13

1

T65

3

T196

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T13

11

T17

12

T65

10

auto[1]

1095

1

T13

9

T17

8

T65

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T13

6

T17

5

T65

3

from_0to1

528

1

T13

5

T17

6

T65

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T13

10

T17

10

T65

12

auto[1]

1116

1

T13

10

T17

10

T65

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T13

12

T17

12

T65

12

auto[1]

1117

1

T13

8

T17

8

T65

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T13

2

T17

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T13

1

T58

2

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T17

1

T58

2

T67

3

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T13

1

T66

1

T58

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T13

2

T17

2

T67

2

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T66

1

T58

2

T285

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T17

1

T66

2

T58

3

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T13

1

T17

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T13

2

T65

1

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T17

1

T66

1

T58

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T17

1

T65

1

T196

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T17

1

T58

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T65

1

T58

1

T285

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T17

2

T196

1

T50

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T13

1

T58

1

T196

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T13

1

T65

1

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T13

8

T17

8

T65

9

auto[1]

1155

1

T13

12

T17

12

T65

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T13

6

T17

5

T65

3

from_0to1

536

1

T13

5

T17

4

T65

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T13

11

T17

14

T65

12

auto[1]

1119

1

T13

9

T17

6

T65

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T13

9

T17

10

T65

9

auto[1]

1148

1

T13

11

T17

10

T65

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T17

2

T58

2

T285

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T13

1

T58

1

T196

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T58

1

T67

2

T196

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T13

1

T17

1

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T13

1

T66

1

T58

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T17

1

T65

1

T66

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T13

1

T66

2

T199

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T65

1

T58

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T17

1

T65

2

T66

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T13

3

T17

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T66

2

T58

1

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T13

1

T65

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T13

1

T17

2

T58

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T196

1

T285

2

T50

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T13

1

T67

1

T196

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T13

1

T17

1

T65

1