Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119368

1

T1

333

T6

29

T7

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143539	1			T1	319		T6	14		T7	22
values[0x0]	66572	1			T1	268		T6	30		T7	10
values[0x1]	66771	1			T1	293		T6	41		T7	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127657	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149225

1

T1

419

T6

37

T7

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1201	1			T1	4		T53	1		T26	1
valid_sources[0x01]	973	1			T14	1		T53	1		T26	3
valid_sources[0x02]	1022	1			T1	4		T6	1		T14	5
valid_sources[0x03]	1039	1			T1	2		T14	3		T26	2
valid_sources[0x04]	1079	1			T1	2		T14	3		T27	7
valid_sources[0x05]	1073	1			T7	1		T14	1		T26	3
valid_sources[0x06]	934	1			T1	2		T6	2		T14	2
valid_sources[0x07]	1148	1			T1	2		T14	2		T53	2
valid_sources[0x08]	936	1			T1	4		T14	2		T26	1
valid_sources[0x09]	898	1			T14	1		T26	2		T5	2
valid_sources[0x0a]	1029	1			T1	6		T14	4		T27	8
valid_sources[0x0b]	1141	1			T1	7		T7	1		T14	2
valid_sources[0x0c]	863	1			T1	5		T14	1		T25	1
valid_sources[0x0d]	1011	1			T1	2		T14	2		T26	5
valid_sources[0x0e]	1198	1			T1	3		T6	2		T14	1
valid_sources[0x0f]	1009	1			T1	3		T26	1		T65	3
valid_sources[0x10]	2708	1			T1	4		T7	1		T14	3
valid_sources[0x11]	882	1			T1	5		T26	3		T54	2
valid_sources[0x12]	1004	1			T1	4		T14	2		T26	1
valid_sources[0x13]	1612	1			T1	6		T14	4		T53	3
valid_sources[0x14]	1013	1			T1	5		T27	13		T26	1
valid_sources[0x15]	823	1			T1	3		T14	1		T27	5
valid_sources[0x16]	1111	1			T1	5		T14	2		T27	1
valid_sources[0x17]	1345	1			T1	4		T6	1		T2	1
valid_sources[0x18]	886	1			T1	4		T6	2		T14	1
valid_sources[0x19]	956	1			T1	4		T26	2		T54	1
valid_sources[0x1a]	1131	1			T1	1		T14	2		T27	13
valid_sources[0x1b]	976	1			T1	3		T26	1		T5	8
valid_sources[0x1c]	1790	1			T1	4		T14	4		T27	1
valid_sources[0x1d]	1066	1			T1	2		T14	4		T27	6
valid_sources[0x1e]	1039	1			T1	2		T14	3		T27	3
valid_sources[0x1f]	1237	1			T1	3		T14	5		T16	45
valid_sources[0x20]	873	1			T1	3		T53	1		T26	2
valid_sources[0x21]	1011	1			T1	1		T14	2		T27	1
valid_sources[0x22]	1092	1			T1	2		T14	2		T45	1
valid_sources[0x23]	1042	1			T1	4		T14	2		T26	1
valid_sources[0x24]	1002	1			T1	2		T6	2		T2	3
valid_sources[0x25]	929	1			T1	3		T14	1		T27	7
valid_sources[0x26]	1064	1			T1	3		T26	1		T5	1
valid_sources[0x27]	790	1			T1	7		T25	1		T26	1
valid_sources[0x28]	1063	1			T1	1		T14	1		T53	1
valid_sources[0x29]	970	1			T1	3		T14	5		T53	1
valid_sources[0x2a]	855	1			T1	6		T5	2		T45	1
valid_sources[0x2b]	1154	1			T1	2		T6	1		T14	1
valid_sources[0x2c]	926	1			T1	2		T14	1		T53	1
valid_sources[0x2d]	815	1			T1	4		T14	2		T26	2
valid_sources[0x2e]	888	1			T1	3		T7	1		T14	1
valid_sources[0x2f]	915	1			T1	5		T14	1		T26	3
valid_sources[0x30]	895	1			T1	2		T6	2		T14	2
valid_sources[0x31]	805	1			T1	1		T6	1		T26	1
valid_sources[0x32]	1141	1			T1	6		T7	1		T14	1
valid_sources[0x33]	882	1			T1	5		T14	5		T25	1
valid_sources[0x34]	1973	1			T1	4		T14	1		T26	6
valid_sources[0x35]	1212	1			T1	3		T7	3		T53	1
valid_sources[0x36]	961	1			T1	1		T14	2		T27	5
valid_sources[0x37]	935	1			T1	3		T14	2		T53	1
valid_sources[0x38]	849	1			T1	5		T7	1		T14	1
valid_sources[0x39]	1068	1			T1	7		T7	2		T14	2
valid_sources[0x3a]	940	1			T1	4		T6	5		T14	1
valid_sources[0x3b]	1091	1			T1	2		T6	4		T14	3
valid_sources[0x3c]	1259	1			T1	2		T14	3		T26	2
valid_sources[0x3d]	1256	1			T1	2		T14	1		T27	3
valid_sources[0x3e]	1301	1			T1	1		T14	3		T26	2
valid_sources[0x3f]	912	1			T1	7		T27	2		T26	1
valid_sources[0x40]	1100	1			T1	5		T14	2		T27	4
valid_sources[0x41]	934	1			T1	1		T14	1		T26	4
valid_sources[0x42]	1147	1			T1	3		T14	1		T26	2
valid_sources[0x43]	902	1			T1	6		T25	1		T5	5
valid_sources[0x44]	926	1			T1	3		T53	1		T26	2
valid_sources[0x45]	1263	1			T1	4		T14	1		T26	1
valid_sources[0x46]	1223	1			T1	6		T6	1		T14	3
valid_sources[0x47]	1036	1			T1	5		T25	1		T26	3
valid_sources[0x48]	1009	1			T14	2		T26	1		T5	8
valid_sources[0x49]	1148	1			T1	5		T6	1		T7	4
valid_sources[0x4a]	916	1			T1	3		T14	3		T27	1
valid_sources[0x4b]	1041	1			T14	2		T5	4		T66	3
valid_sources[0x4c]	1345	1			T1	2		T6	1		T14	3
valid_sources[0x4d]	1010	1			T1	3		T14	3		T27	11
valid_sources[0x4e]	1191	1			T1	10		T6	2		T13	122
valid_sources[0x4f]	883	1			T1	4		T14	1		T53	1
valid_sources[0x50]	908	1			T1	3		T27	15		T26	3
valid_sources[0x51]	1056	1			T1	3		T14	2		T26	4
valid_sources[0x52]	932	1			T1	3		T6	1		T14	4
valid_sources[0x53]	974	1			T1	1		T14	3		T26	2
valid_sources[0x54]	1110	1			T1	5		T14	2		T27	5
valid_sources[0x55]	1009	1			T1	5		T14	1		T27	2
valid_sources[0x56]	1044	1			T1	1		T7	3		T26	2
valid_sources[0x57]	1238	1			T1	1		T14	1		T53	1
valid_sources[0x58]	905	1			T1	2		T26	1		T5	2
valid_sources[0x59]	973	1			T1	1		T14	3		T26	3
valid_sources[0x5a]	994	1			T1	4		T14	1		T53	1
valid_sources[0x5b]	879	1			T1	3		T14	2		T26	5
valid_sources[0x5c]	951	1			T1	3		T14	3		T26	2
valid_sources[0x5d]	1007	1			T1	8		T2	1		T27	1
valid_sources[0x5e]	1046	1			T1	3		T14	4		T27	3
valid_sources[0x5f]	904	1			T14	1		T26	1		T5	6
valid_sources[0x60]	1033	1			T1	8		T14	3		T26	1
valid_sources[0x61]	994	1			T1	3		T14	1		T2	2
valid_sources[0x62]	940	1			T1	4		T6	2		T14	2
valid_sources[0x63]	912	1			T1	3		T14	2		T18	15
valid_sources[0x64]	1048	1			T1	6		T14	1		T26	1
valid_sources[0x65]	1886	1			T1	1		T14	3		T27	2
valid_sources[0x66]	1097	1			T1	3		T26	3		T54	6
valid_sources[0x67]	1212	1			T1	2		T27	8		T53	2
valid_sources[0x68]	1217	1			T6	1		T14	2		T26	1
valid_sources[0x69]	1455	1			T1	3		T14	1		T17	123
valid_sources[0x6a]	886	1			T1	10		T14	3		T27	8
valid_sources[0x6b]	1039	1			T1	2		T5	5		T45	3
valid_sources[0x6c]	1009	1			T1	6		T6	9		T14	1
valid_sources[0x6d]	936	1			T1	4		T6	1		T14	4
valid_sources[0x6e]	937	1			T1	2		T6	1		T14	2
valid_sources[0x6f]	1052	1			T14	1		T53	1		T25	1
valid_sources[0x70]	1232	1			T1	2		T14	1		T26	1
valid_sources[0x71]	1840	1			T6	6		T14	1		T27	8
valid_sources[0x72]	901	1			T1	5		T6	2		T7	1
valid_sources[0x73]	939	1			T1	3		T14	2		T27	4
valid_sources[0x74]	1039	1			T14	4		T53	1		T26	3
valid_sources[0x75]	886	1			T6	1		T14	1		T27	4
valid_sources[0x76]	933	1			T1	2		T14	3		T26	3
valid_sources[0x77]	888	1			T1	5		T6	3		T26	2
valid_sources[0x78]	1689	1			T53	2		T26	2		T5	4
valid_sources[0x79]	1410	1			T1	6		T27	4		T26	2
valid_sources[0x7a]	901	1			T1	6		T14	1		T5	2
valid_sources[0x7b]	990	1			T1	6		T14	1		T26	2
valid_sources[0x7c]	1018	1			T1	5		T6	1		T14	1
valid_sources[0x7d]	981	1			T1	2		T14	5		T53	1
valid_sources[0x7e]	877	1			T1	2		T14	2		T26	2
valid_sources[0x7f]	1114	1			T53	2		T65	1		T5	8
valid_sources[0x80]	869	1			T1	5		T26	1		T45	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64999

1

T1

167

T6

8

T7

12

values[0x0]

all_enables

biggest_size

32017

1

T1

100

T6

14

T7

5

values[0x1]

all_enables

biggest_size

22352

1

T1

66

T6

7

T7

3