Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1441916269	9936	0	0
auto_block_debounce_ctl_rd_A	1441916269	1525	0	0
auto_block_out_ctl_rd_A	1441916269	1827	0	0
com_det_ctl_0_rd_A	1441916269	4119	0	0
com_det_ctl_1_rd_A	1441916269	4138	0	0
com_det_ctl_2_rd_A	1441916269	4176	0	0
com_det_ctl_3_rd_A	1441916269	4035	0	0
com_out_ctl_0_rd_A	1441916269	4593	0	0
com_out_ctl_1_rd_A	1441916269	4347	0	0
com_out_ctl_2_rd_A	1441916269	4586	0	0
com_out_ctl_3_rd_A	1441916269	4267	0	0
com_pre_det_ctl_0_rd_A	1441916269	1279	0	0
com_pre_det_ctl_1_rd_A	1441916269	1203	0	0
com_pre_det_ctl_2_rd_A	1441916269	1225	0	0
com_pre_det_ctl_3_rd_A	1441916269	1277	0	0
com_pre_sel_ctl_0_rd_A	1441916269	4708	0	0
com_pre_sel_ctl_1_rd_A	1441916269	4584	0	0
com_pre_sel_ctl_2_rd_A	1441916269	4569	0	0
com_pre_sel_ctl_3_rd_A	1441916269	4673	0	0
com_sel_ctl_0_rd_A	1441916269	4376	0	0
com_sel_ctl_1_rd_A	1441916269	4334	0	0
com_sel_ctl_2_rd_A	1441916269	4455	0	0
com_sel_ctl_3_rd_A	1441916269	4574	0	0
ec_rst_ctl_rd_A	1441916269	2190	0	0
intr_enable_rd_A	1441916269	1969	0	0
key_intr_ctl_rd_A	1441916269	2728	0	0
key_intr_debounce_ctl_rd_A	1441916269	1330	0	0
key_invert_ctl_rd_A	1441916269	3724	0	0
pin_allowed_ctl_rd_A	1441916269	5233	0	0
pin_out_ctl_rd_A	1441916269	3533	0	0
pin_out_value_rd_A	1441916269	4309	0	0
regwen_rd_A	1441916269	1558	0	0
ulp_ac_debounce_ctl_rd_A	1441916269	1510	0	0
ulp_ctl_rd_A	1441916269	1540	0	0
ulp_lid_debounce_ctl_rd_A	1441916269	1270	0	0
ulp_pwrb_debounce_ctl_rd_A	1441916269	1421	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	9936	0	0
T23	58847	0	0	0
T31	969190	0	0	0
T34	106042	0	0	0
T36	179482	0	0	0
T37	0	12	0	0
T38	0	15	0	0
T48	349571	0	0	0
T49	382354	0	0	0
T50	0	7	0	0
T51	0	14	0	0
T58	186443	5	0	0
T59	0	9	0	0
T67	70919	0	0	0
T71	0	8	0	0
T93	261465	0	0	0
T125	0	7	0	0
T129	119334	0	0	0
T174	0	16	0	0
T316	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1525	0	0
T2	213766	0	0	0
T6	177087	3	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T27	139044	0	0	0
T59	0	19	0	0
T95	0	6	0	0
T96	0	10	0	0
T123	0	2	0	0
T167	0	15	0	0
T317	0	25	0	0
T318	0	8	0	0
T319	0	10	0	0
T320	0	4	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1827	0	0
T2	213766	0	0	0
T6	177087	17	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T25	0	13	0	0
T27	139044	0	0	0
T59	0	20	0	0
T95	0	10	0	0
T96	0	9	0	0
T123	0	7	0	0
T317	0	8	0	0
T318	0	4	0	0
T319	0	6	0	0
T320	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4119	0	0
T3	77123	0	0	0
T5	0	63	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	83	0	0
T30	56123	0	0	0
T34	0	71	0	0
T35	0	54	0	0
T47	0	15	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	61	0	0
T94	0	91	0	0
T122	0	68	0	0
T191	0	213	0	0
T321	0	51	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4138	0	0
T3	77123	0	0	0
T5	0	32	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	62	0	0
T30	56123	0	0	0
T34	0	68	0	0
T35	0	73	0	0
T47	0	41	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	64	0	0
T94	0	44	0	0
T122	0	53	0	0
T191	0	236	0	0
T321	0	68	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4176	0	0
T3	77123	0	0	0
T5	0	51	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	56	0	0
T30	56123	0	0	0
T34	0	51	0	0
T35	0	79	0	0
T47	0	21	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	45	0	0
T94	0	73	0	0
T122	0	57	0	0
T191	0	203	0	0
T321	0	72	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4035	0	0
T3	77123	0	0	0
T5	0	52	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	70	0	0
T30	56123	0	0	0
T34	0	65	0	0
T35	0	109	0	0
T47	0	25	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	50	0	0
T94	0	73	0	0
T122	0	58	0	0
T191	0	207	0	0
T321	0	72	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4593	0	0
T3	77123	0	0	0
T5	0	53	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	84	0	0
T30	56123	0	0	0
T34	0	63	0	0
T35	0	65	0	0
T47	0	46	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	76	0	0
T94	0	84	0	0
T122	0	50	0	0
T191	0	161	0	0
T321	0	65	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4347	0	0
T3	77123	0	0	0
T5	0	40	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	57	0	0
T30	56123	0	0	0
T34	0	56	0	0
T35	0	69	0	0
T47	0	48	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	45	0	0
T94	0	64	0	0
T122	0	62	0	0
T191	0	205	0	0
T321	0	80	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4586	0	0
T3	77123	0	0	0
T5	0	65	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	64	0	0
T30	56123	0	0	0
T34	0	75	0	0
T35	0	78	0	0
T47	0	55	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	34	0	0
T94	0	71	0	0
T122	0	62	0	0
T191	0	191	0	0
T321	0	60	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4267	0	0
T3	77123	0	0	0
T5	0	66	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	71	0	0
T30	56123	0	0	0
T34	0	63	0	0
T35	0	64	0	0
T47	0	22	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	44	0	0
T94	0	65	0	0
T122	0	59	0	0
T191	0	212	0	0
T321	0	59	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1279	0	0
T19	0	53	0	0
T29	0	43	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	12	0	0
T60	53814	0	0	0
T88	0	20	0	0
T118	0	8	0	0
T163	0	10	0	0
T167	0	19	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	11	0	0
T258	0	20	0	0
T298	0	333	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1203	0	0
T19	0	53	0	0
T29	0	35	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	16	0	0
T60	53814	0	0	0
T88	0	16	0	0
T118	0	6	0	0
T163	0	9	0	0
T167	0	34	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	16	0	0
T258	0	25	0	0
T298	0	321	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1225	0	0
T19	0	36	0	0
T29	0	5	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	26	0	0
T60	53814	0	0	0
T88	0	31	0	0
T118	0	6	0	0
T163	0	7	0	0
T167	0	32	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	11	0	0
T258	0	16	0	0
T298	0	326	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1277	0	0
T19	0	66	0	0
T29	0	28	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	18	0	0
T60	53814	0	0	0
T88	0	33	0	0
T118	0	9	0	0
T163	0	6	0	0
T167	0	14	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	6	0	0
T258	0	8	0	0
T298	0	294	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4708	0	0
T3	77123	0	0	0
T5	0	55	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	53	0	0
T30	56123	0	0	0
T34	0	49	0	0
T35	0	73	0	0
T47	0	50	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	52	0	0
T94	0	68	0	0
T122	0	51	0	0
T191	0	233	0	0
T321	0	78	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4584	0	0
T3	77123	0	0	0
T5	0	30	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	77	0	0
T30	56123	0	0	0
T34	0	78	0	0
T35	0	56	0	0
T47	0	40	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	52	0	0
T94	0	62	0	0
T122	0	51	0	0
T191	0	215	0	0
T321	0	56	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4569	0	0
T3	77123	0	0	0
T5	0	67	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	80	0	0
T30	56123	0	0	0
T34	0	77	0	0
T35	0	57	0	0
T47	0	69	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	51	0	0
T94	0	75	0	0
T122	0	43	0	0
T191	0	241	0	0
T321	0	74	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4673	0	0
T3	77123	0	0	0
T5	0	47	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	83	0	0
T30	56123	0	0	0
T34	0	82	0	0
T35	0	65	0	0
T47	0	31	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	60	0	0
T94	0	74	0	0
T122	0	46	0	0
T191	0	169	0	0
T321	0	88	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4376	0	0
T3	77123	0	0	0
T5	0	35	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	60	0	0
T30	56123	0	0	0
T34	0	78	0	0
T35	0	78	0	0
T47	0	67	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	43	0	0
T94	0	52	0	0
T122	0	64	0	0
T191	0	181	0	0
T321	0	80	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4334	0	0
T3	77123	0	0	0
T5	0	47	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	62	0	0
T30	56123	0	0	0
T34	0	77	0	0
T35	0	59	0	0
T47	0	40	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	52	0	0
T94	0	81	0	0
T122	0	36	0	0
T191	0	188	0	0
T321	0	83	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4455	0	0
T3	77123	0	0	0
T5	0	67	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	59	0	0
T30	56123	0	0	0
T34	0	63	0	0
T35	0	84	0	0
T47	0	47	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	47	0	0
T94	0	68	0	0
T122	0	57	0	0
T191	0	205	0	0
T321	0	75	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4574	0	0
T3	77123	0	0	0
T5	0	30	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	56	0	0
T30	56123	0	0	0
T34	0	48	0	0
T35	0	79	0	0
T47	0	17	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	48	0	0
T94	0	59	0	0
T122	0	88	0	0
T191	0	202	0	0
T321	0	76	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2190	0	0
T3	77123	0	0	0
T5	0	28	0	0
T8	220081	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T27	139044	8	0	0
T30	56123	0	0	0
T34	0	27	0	0
T35	0	8	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	46	0	0
T94	0	16	0	0
T98	0	1	0	0
T122	0	11	0	0
T191	0	75	0	0
T321	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1969	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	75	0	0
T60	53814	0	0	0
T88	0	14	0	0
T118	0	1	0	0
T163	0	17	0	0
T167	0	49	0	0
T173	0	12	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T194	0	18	0	0
T200	0	72	0	0
T258	0	15	0	0
T322	0	13	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2728	0	0
T43	0	2	0	0
T59	0	17	0	0
T63	37382	0	0	0
T68	31583	6	0	0
T69	108679	0	0	0
T70	210227	0	0	0
T78	863219	0	0	0
T110	63007	0	0	0
T111	251596	0	0	0
T112	744195	0	0	0
T122	599932	0	0	0
T136	0	5	0	0
T166	0	7	0	0
T167	0	37	0	0
T173	0	1	0	0
T194	0	6	0	0
T253	0	1	0	0
T285	30805	0	0	0
T323	0	8	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1330	0	0
T19	0	42	0	0
T29	0	28	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	15	0	0
T60	53814	0	0	0
T88	0	21	0	0
T118	0	10	0	0
T163	0	9	0	0
T167	0	19	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	12	0	0
T258	0	13	0	0
T298	0	339	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	3724	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	133	0	0
T60	53814	0	0	0
T118	0	135	0	0
T167	0	102	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	18	0	0
T220	0	55	0	0
T244	0	60	0	0
T258	0	24	0	0
T324	0	38	0	0
T325	0	56	0	0
T326	0	76	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	5233	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	172	0	0
T60	53814	0	0	0
T72	0	141	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T191	0	73	0	0
T215	0	65	0	0
T217	0	77	0	0
T240	0	69	0	0
T327	0	79	0	0
T328	0	76	0	0
T329	0	89	0	0
T330	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	3533	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	168	0	0
T60	53814	0	0	0
T72	0	146	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T191	0	68	0	0
T215	0	56	0	0
T217	0	69	0	0
T240	0	51	0	0
T327	0	55	0	0
T328	0	60	0	0
T329	0	68	0	0
T330	0	59	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	4309	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	193	0	0
T60	53814	0	0	0
T72	0	132	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T191	0	78	0	0
T215	0	51	0	0
T217	0	82	0	0
T240	0	82	0	0
T327	0	76	0	0
T328	0	72	0	0
T329	0	60	0	0
T330	0	83	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1558	0	0
T19	0	75	0	0
T29	0	246	0	0
T38	351483	0	0	0
T50	184939	0	0	0
T51	127245	0	0	0
T59	642681	11	0	0
T60	53814	0	0	0
T88	0	22	0	0
T118	0	3	0	0
T163	0	5	0	0
T167	0	29	0	0
T186	58413	0	0	0
T187	305684	0	0	0
T188	52827	0	0	0
T189	48755	0	0	0
T190	55692	0	0	0
T200	0	4	0	0
T258	0	23	0	0
T298	0	346	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1510	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T22	0	9	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	2	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	25	0	0
T60	0	12	0	0
T61	0	2	0	0
T72	0	4	0	0
T73	0	5	0	0
T127	0	5	0	0
T331	0	2	0	0
T332	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1540	0	0
T22	118214	10	0	0
T23	58847	0	0	0
T31	969190	0	0	0
T34	106042	0	0	0
T36	179482	0	0	0
T48	349571	0	0	0
T58	186443	0	0	0
T59	0	36	0	0
T60	0	7	0	0
T61	0	9	0	0
T67	70919	0	0	0
T72	0	7	0	0
T73	0	8	0	0
T93	261465	0	0	0
T127	0	10	0	0
T129	119334	0	0	0
T167	0	46	0	0
T173	0	11	0	0
T333	0	14	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1270	0	0
T22	118214	5	0	0
T23	58847	0	0	0
T31	969190	0	0	0
T34	106042	0	0	0
T36	179482	0	0	0
T48	349571	0	0	0
T58	186443	0	0	0
T59	0	28	0	0
T60	0	1	0	0
T61	0	2	0	0
T67	70919	0	0	0
T72	0	3	0	0
T93	261465	0	0	0
T127	0	5	0	0
T129	119334	0	0	0
T167	0	22	0	0
T173	0	8	0	0
T331	0	10	0	0
T333	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1421	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T22	0	1	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	7	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T59	0	21	0	0
T60	0	1	0	0
T61	0	6	0	0
T72	0	3	0	0
T127	0	1	0	0
T167	0	19	0	0
T331	0	6	0	0
T332	0	3	0	0