Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_lid_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_pwrb_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_ulp_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.88	100.00	87.50			100.00	100.00	u_wkup_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_invert_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_allowed_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_out_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_out_value_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_intr_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_intr_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_auto_block_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_auto_block_out_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T9,T22,T23
1	1	Covered	T1,T14,T27

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	231670	0	0
SrcPulseCheck_M	2147483647	234286	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	231670	0	0
T1	3305307	68	0	0
T2	6218180	0	0	0
T3	154888	0	0	0
T4	279186	0	0	0
T5	0	204	0	0
T6	5777487	16	0	0
T7	1750280	0	0	0
T8	440766	0	0	0
T12	0	400	0	0
T13	3613708	0	0	0
T14	16231628	17	0	0
T15	1655640	0	0	0
T16	3447024	0	0	0
T17	1783964	0	0	0
T18	20789172	14	0	0
T24	895421	0	0	0
T25	167201	14	0	0
T26	219177	17	0	0
T27	867630	16	0	0
T30	170667	0	0	0
T31	0	14	0	0
T32	0	2	0	0
T33	0	119	0	0
T34	0	160	0	0
T38	0	14	0	0
T45	0	17	0	0
T46	0	18	0	0
T47	0	16	0	0
T48	0	14	0	0
T49	0	1	0	0
T50	0	12	0	0
T51	0	8	0	0
T52	611446	0	0	0
T53	64466	0	0	0
T54	250600	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	234286	0	0
T1	3305307	68	0	0
T2	6218180	0	0	0
T3	78407	0	0	0
T4	46053	0	0	0
T5	0	204	0	0
T6	5777487	16	0	0
T7	1750280	0	0	0
T8	221289	0	0	0
T12	0	400	0	0
T13	3613708	0	0	0
T14	16231628	17	0	0
T15	1655640	0	0	0
T16	3447024	0	0	0
T17	1783964	0	0	0
T18	20789172	14	0	0
T24	450445	0	0	0
T25	84640	14	0	0
T26	4565	17	0	0
T27	867630	16	0	0
T30	115693	0	0	0
T31	0	14	0	0
T32	0	2	0	0
T33	0	119	0	0
T34	0	160	0	0
T38	0	14	0	0
T45	0	17	0	0
T46	0	18	0	0
T47	0	16	0	0
T48	0	14	0	0
T49	0	1	0	0
T50	0	12	0	0
T51	0	8	0	0
T52	306677	0	0	0
T53	33031	0	0	0
T54	522	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T19,T29,T298

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T19,T29,T298
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1980	0	0
SrcPulseCheck_M	1441916269	2056	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1980	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	25	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T45	0	1	0	0
T52	0	1	0	0
T57	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2056	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	25	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T45	0	1	0	0
T52	0	1	0	0
T57	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T19,T29,T298

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T19,T29,T298
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	2049	0	0
SrcPulseCheck_M	7317763	2049	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2049	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	25	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T45	0	1	0	0
T52	0	1	0	0
T57	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	2049	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	25	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T45	0	1	0	0
T52	0	1	0	0
T57	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T30,T9,T22
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T9,T22,T23
1	1	Covered	T30,T9,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	984	0	0
SrcPulseCheck_M	1441916269	1065	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	984	0	0
T3	642	0	0	0
T4	46053	0	0	0
T8	604	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T30	1149	1	0	0
T51	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1065	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	1	0	0
T51	0	1	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T30,T9,T22
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T9,T22,T23
1	1	Covered	T30,T9,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1059	0	0
SrcPulseCheck_M	7317763	1059	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1059	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	1	0	0
T51	0	1	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1059	0	0
T3	642	0	0	0
T4	46053	0	0	0
T8	604	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T30	1149	1	0	0
T51	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T30,T9,T22
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T9,T22,T23
1	1	Covered	T30,T9,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	975	0	0
SrcPulseCheck_M	1441916269	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	975	0	0
T3	642	0	0	0
T4	46053	0	0	0
T8	604	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T30	1149	1	0	0
T51	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1052	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	1	0	0
T51	0	1	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T30,T9,T22
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T9,T22,T23
1	1	Covered	T30,T9,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1043	0	0
SrcPulseCheck_M	7317763	1043	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1043	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	1	0	0
T51	0	1	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1043	0	0
T3	642	0	0	0
T4	46053	0	0	0
T8	604	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T30	1149	1	0	0
T51	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T30,T9,T22
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T9,T22,T23
1	1	Covered	T30,T9,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	993	0	0
SrcPulseCheck_M	1441916269	1068	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	993	0	0
T3	642	0	0	0
T4	46053	0	0	0
T8	604	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T30	1149	1	0	0
T51	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1068	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	1	0	0
T51	0	1	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T30,T9,T22
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T30,T9,T22
1	0	Covered	T9,T22,T23
1	1	Covered	T30,T9,T22

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1063	0	0
SrcPulseCheck_M	7317763	1063	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1063	0	0
T3	77123	0	0	0
T4	279186	0	0	0
T8	220081	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T26	219177	0	0	0
T30	56123	1	0	0
T51	0	1	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T54	250600	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1063	0	0
T3	642	0	0	0
T4	46053	0	0	0
T8	604	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T23	0	2	0	0
T24	1823	0	0	0
T25	693	0	0	0
T26	4565	0	0	0
T30	1149	1	0	0
T51	0	1	0	0
T52	636	0	0	0
T53	532	0	0	0
T54	522	0	0	0
T56	0	3	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T9,T22,T23
1	0	Covered	T9,T22,T23
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T9,T22,T23
1	0	Covered	T9,T22,T23
1	1	Covered	T9,T22,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1024	0	0
SrcPulseCheck_M	1441916269	1099	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1024	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	4	0	0
T61	0	2	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	420	0	0	0
T77	449	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1099	0	0
T9	112883	2	0	0
T10	160414	0	0	0
T11	195301	0	0	0
T12	303261	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T45	136677	0	0	0
T46	356021	0	0	0
T56	0	4	0	0
T61	0	2	0	0
T62	54276	0	0	0
T66	246272	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	100979	0	0	0
T77	53994	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T9,T22,T23
1	0	Covered	T9,T22,T23
1	1	Covered	T9,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T9,T22,T23
1	0	Covered	T9,T22,T23
1	1	Covered	T9,T22,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1094	0	0
SrcPulseCheck_M	7317763	1094	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1094	0	0
T9	112883	2	0	0
T10	160414	0	0	0
T11	195301	0	0	0
T12	303261	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T45	136677	0	0	0
T46	356021	0	0	0
T56	0	4	0	0
T61	0	2	0	0
T62	54276	0	0	0
T66	246272	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	100979	0	0	0
T77	53994	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1094	0	0
T9	1381	2	0	0
T10	628	0	0	0
T11	535	0	0	0
T12	60652	0	0	0
T22	0	2	0	0
T23	0	2	0	0
T45	5467	0	0	0
T46	749	0	0	0
T56	0	4	0	0
T61	0	2	0	0
T62	493	0	0	0
T66	502	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	420	0	0	0
T77	449	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T5,T9
1	1	Covered	T56,T32,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T5,T9
1	0	Covered	T56,T32,T122
1	1	Covered	T1,T5,T9

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1129	0	0
SrcPulseCheck_M	1441916269	1207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1129	0	0
T1	13064	1	0	0
T2	654	0	0	0
T5	0	7	0	0
T6	36894	0	0	0
T7	496	0	0	0
T9	0	1	0	0
T12	0	7	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T33	0	6	0	0
T34	0	9	0	0
T35	0	2	0	0
T56	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1207	0	0
T1	130645	1	0	0
T2	213766	0	0	0
T5	0	7	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T9	0	1	0	0
T12	0	7	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T33	0	6	0	0
T34	0	9	0	0
T35	0	2	0	0
T56	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T7,T16,T24
1	0	Covered	T7,T16,T24
1	1	Covered	T7,T16,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T7,T16,T24
1	0	Covered	T7,T16,T24
1	1	Covered	T7,T16,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	2858	0	0
SrcPulseCheck_M	1441916269	2932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	2858	0	0
T2	654	0	0	0
T7	496	20	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	20	0	0
T17	505	0	0	0
T18	55144	0	0	0
T24	0	20	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T50	0	40	0	0
T51	0	20	0	0
T58	0	20	0	0
T59	0	40	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2932	0	0
T2	213766	0	0	0
T7	62014	20	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	20	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T24	0	20	0	0
T27	139044	0	0	0
T30	56123	0	0	0
T50	0	40	0	0
T51	0	20	0	0
T58	0	20	0	0
T59	0	40	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T7,T16,T24
1	0	Covered	T7,T16,T24
1	1	Covered	T7,T16,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T7,T16,T24
1	0	Covered	T7,T16,T24
1	1	Covered	T7,T16,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	2926	0	0
SrcPulseCheck_M	7317763	2926	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2926	0	0
T2	213766	0	0	0
T7	62014	20	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	20	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T24	0	20	0	0
T27	139044	0	0	0
T30	56123	0	0	0
T50	0	40	0	0
T51	0	20	0	0
T58	0	20	0	0
T59	0	40	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	2926	0	0
T2	654	0	0	0
T7	496	20	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	20	0	0
T17	505	0	0	0
T18	55144	0	0	0
T24	0	20	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T50	0	40	0	0
T51	0	20	0	0
T58	0	20	0	0
T59	0	40	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T7,T13
1	0	Covered	T6,T7,T13
1	1	Covered	T6,T13,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T7,T13
1	0	Covered	T6,T13,T17
1	1	Covered	T6,T7,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	6560	0	0
SrcPulseCheck_M	1441916269	6635	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	6560	0	0
T2	654	0	0	0
T6	36894	20	0	0
T7	496	1	0	0
T13	503	20	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	1	0	0
T17	505	20	0	0
T18	55144	0	0	0
T24	0	21	0	0
T27	5561	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T62	0	1	0	0
T65	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	6635	0	0
T2	213766	0	0	0
T6	177087	20	0	0
T7	62014	1	0	0
T13	128558	20	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	1	0	0
T17	63208	20	0	0
T18	661724	0	0	0
T24	0	21	0	0
T27	139044	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T62	0	1	0	0
T65	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T7,T13
1	0	Covered	T6,T7,T13
1	1	Covered	T6,T13,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T7,T13
1	0	Covered	T6,T13,T17
1	1	Covered	T6,T7,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	6631	0	0
SrcPulseCheck_M	7317763	6631	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	6631	0	0
T2	213766	0	0	0
T6	177087	20	0	0
T7	62014	1	0	0
T13	128558	20	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	1	0	0
T17	63208	20	0	0
T18	661724	0	0	0
T24	0	21	0	0
T27	139044	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T62	0	1	0	0
T65	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	6631	0	0
T2	654	0	0	0
T6	36894	20	0	0
T7	496	1	0	0
T13	503	20	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	1	0	0
T17	505	20	0	0
T18	55144	0	0	0
T24	0	21	0	0
T27	5561	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T62	0	1	0	0
T65	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T6,T13,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T6,T13,T17
1	1	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7825	0	0
SrcPulseCheck_M	1441916269	7905	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7825	0	0
T1	13064	4	0	0
T2	654	0	0	0
T6	36894	20	0	0
T7	496	1	0	0
T13	503	20	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	1	0	0
T17	505	20	0	0
T18	55144	0	0	0
T27	0	1	0	0
T52	0	1	0	0
T53	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7905	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T6	177087	20	0	0
T7	62014	1	0	0
T13	128558	20	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	1	0	0
T17	63208	20	0	0
T18	661724	0	0	0
T27	0	1	0	0
T52	0	1	0	0
T53	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
1	1	Covered	T6,T13,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T6,T13,T17
1	1	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7900	0	0
SrcPulseCheck_M	7317763	7900	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7900	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T6	177087	20	0	0
T7	62014	1	0	0
T13	128558	20	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	1	0	0
T17	63208	20	0	0
T18	661724	0	0	0
T27	0	1	0	0
T52	0	1	0	0
T53	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7900	0	0
T1	13064	4	0	0
T2	654	0	0	0
T6	36894	20	0	0
T7	496	1	0	0
T13	503	20	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	1	0	0
T17	505	20	0	0
T18	55144	0	0	0
T27	0	1	0	0
T52	0	1	0	0
T53	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T13,T17
1	0	Covered	T6,T13,T17
1	1	Covered	T6,T13,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T13,T17
1	0	Covered	T6,T13,T17
1	1	Covered	T6,T13,T17

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	6484	0	0
SrcPulseCheck_M	1441916269	6561	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	6484	0	0
T2	654	0	0	0
T6	36894	20	0	0
T7	496	0	0	0
T13	503	20	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	20	0	0
T18	55144	0	0	0
T24	0	20	0	0
T27	5561	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T58	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	6561	0	0
T2	213766	0	0	0
T6	177087	20	0	0
T7	62014	0	0	0
T13	128558	20	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	20	0	0
T18	661724	0	0	0
T24	0	20	0	0
T27	139044	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T58	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T13,T17
1	0	Covered	T6,T13,T17
1	1	Covered	T6,T13,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T13,T17
1	0	Covered	T6,T13,T17
1	1	Covered	T6,T13,T17

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	6555	0	0
SrcPulseCheck_M	7317763	6555	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	6555	0	0
T2	213766	0	0	0
T6	177087	20	0	0
T7	62014	0	0	0
T13	128558	20	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	20	0	0
T18	661724	0	0	0
T24	0	20	0	0
T27	139044	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T58	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	6555	0	0
T2	654	0	0	0
T6	36894	20	0	0
T7	496	0	0	0
T13	503	20	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	20	0	0
T18	55144	0	0	0
T24	0	20	0	0
T27	5561	0	0	0
T53	0	20	0	0
T54	0	20	0	0
T58	0	20	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T2,T3,T8
1	0	Covered	T79,T80,T19
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	989	0	0
SrcPulseCheck_M	1441916269	1062	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	989	0	0
T2	654	1	0	0
T3	642	1	0	0
T4	0	1	0	0
T8	604	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	55144	0	0	0
T24	1823	0	0	0
T25	693	0	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T52	636	0	0	0
T53	532	0	0	0
T58	0	2	0	0
T68	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1062	0	0
T2	213766	1	0	0
T3	77123	1	0	0
T4	0	1	0	0
T8	220081	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	661724	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T27	139044	0	0	0
T30	56123	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T58	0	2	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T8
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T2,T3,T8
1	0	Covered	T79,T80,T19
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1058	0	0
SrcPulseCheck_M	7317763	1058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1058	0	0
T2	213766	1	0	0
T3	77123	1	0	0
T4	0	1	0	0
T8	220081	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	661724	0	0	0
T24	446799	0	0	0
T25	83254	0	0	0
T27	139044	0	0	0
T30	56123	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T52	305405	0	0	0
T53	31967	0	0	0
T58	0	2	0	0
T68	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1058	0	0
T2	654	1	0	0
T3	642	1	0	0
T4	0	1	0	0
T8	604	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	55144	0	0	0
T24	1823	0	0	0
T25	693	0	0	0
T27	5561	0	0	0
T30	1149	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T52	636	0	0	0
T53	532	0	0	0
T58	0	2	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T2
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T2
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T2

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1956	0	0
SrcPulseCheck_M	1441916269	2033	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1956	0	0
T1	13064	4	0	0
T2	654	1	0	0
T3	0	1	0	0
T4	0	1	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2033	0	0
T1	130645	4	0	0
T2	213766	1	0	0
T3	0	1	0	0
T4	0	1	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T2
1	0	Covered	T1,T14,T2
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T2
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T2

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	2027	0	0
SrcPulseCheck_M	7317763	2027	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	2027	0	0
T1	130645	4	0	0
T2	213766	1	0	0
T3	0	1	0	0
T4	0	1	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	2027	0	0
T1	13064	4	0	0
T2	654	1	0	0
T3	0	1	0	0
T4	0	1	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1210	0	0
SrcPulseCheck_M	1441916269	1287	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1210	0	0
T2	654	0	0	0
T6	36894	5	0	0
T7	496	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	4	0	0
T25	0	4	0	0
T27	5561	0	0	0
T31	0	4	0	0
T38	0	4	0	0
T46	0	6	0	0
T48	0	4	0	0
T50	0	3	0	0
T51	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1287	0	0
T2	213766	0	0	0
T6	177087	5	0	0
T7	62014	0	0	0
T12	0	5	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	4	0	0
T25	0	4	0	0
T27	139044	0	0	0
T31	0	4	0	0
T38	0	4	0	0
T46	0	6	0	0
T48	0	4	0	0
T50	0	3	0	0
T51	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1282	0	0
SrcPulseCheck_M	7317763	1282	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1282	0	0
T2	213766	0	0	0
T6	177087	5	0	0
T7	62014	0	0	0
T12	0	5	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	4	0	0
T25	0	4	0	0
T27	139044	0	0	0
T31	0	4	0	0
T38	0	4	0	0
T46	0	6	0	0
T48	0	4	0	0
T50	0	3	0	0
T51	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1282	0	0
T2	654	0	0	0
T6	36894	5	0	0
T7	496	0	0	0
T12	0	5	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	4	0	0
T25	0	4	0	0
T27	5561	0	0	0
T31	0	4	0	0
T38	0	4	0	0
T46	0	6	0	0
T48	0	4	0	0
T50	0	3	0	0
T51	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1132	0	0
SrcPulseCheck_M	1441916269	1210	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1132	0	0
T2	654	0	0	0
T6	36894	3	0	0
T7	496	0	0	0
T12	0	3	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	3	0	0
T25	0	3	0	0
T27	5561	0	0	0
T31	0	3	0	0
T38	0	3	0	0
T46	0	3	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1210	0	0
T2	213766	0	0	0
T6	177087	3	0	0
T7	62014	0	0	0
T12	0	3	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	3	0	0
T25	0	3	0	0
T27	139044	0	0	0
T31	0	3	0	0
T38	0	3	0	0
T46	0	3	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T6,T18,T25
1	0	Covered	T6,T18,T25
1	1	Covered	T6,T18,T25

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1203	0	0
SrcPulseCheck_M	7317763	1203	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1203	0	0
T2	213766	0	0	0
T6	177087	3	0	0
T7	62014	0	0	0
T12	0	3	0	0
T13	128558	0	0	0
T14	574479	0	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	3	0	0
T25	0	3	0	0
T27	139044	0	0	0
T31	0	3	0	0
T38	0	3	0	0
T46	0	3	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1203	0	0
T2	654	0	0	0
T6	36894	3	0	0
T7	496	0	0	0
T12	0	3	0	0
T13	503	0	0	0
T14	5222	0	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	3	0	0
T25	0	3	0	0
T27	5561	0	0	0
T31	0	3	0	0
T38	0	3	0	0
T46	0	3	0	0
T48	0	3	0	0
T50	0	3	0	0
T51	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7006	0	0
SrcPulseCheck_M	1441916269	7082	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7006	0	0
T1	13064	71	0	0
T2	654	0	0	0
T5	0	76	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T32	0	66	0	0
T33	0	81	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	94	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7082	0	0
T1	130645	71	0	0
T2	213766	0	0	0
T5	0	76	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	66	0	0
T33	0	81	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	94	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7076	0	0
SrcPulseCheck_M	7317763	7076	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7076	0	0
T1	130645	71	0	0
T2	213766	0	0	0
T5	0	76	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	66	0	0
T33	0	81	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	94	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7076	0	0
T1	13064	71	0	0
T2	654	0	0	0
T5	0	76	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T32	0	66	0	0
T33	0	81	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	94	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	6978	0	0
SrcPulseCheck_M	1441916269	7058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	6978	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	81	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T32	0	67	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	93	0	0
T70	0	74	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7058	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	82	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	67	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	93	0	0
T70	0	74	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7054	0	0
SrcPulseCheck_M	7317763	7054	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7054	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	82	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	67	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	93	0	0
T70	0	74	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7054	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	82	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T32	0	67	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	93	0	0
T70	0	74	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7126	0	0
SrcPulseCheck_M	1441916269	7203	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7126	0	0
T1	13064	56	0	0
T2	654	0	0	0
T5	0	67	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T32	0	76	0	0
T33	0	77	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	88	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7203	0	0
T1	130645	56	0	0
T2	213766	0	0	0
T5	0	68	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	76	0	0
T33	0	77	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	88	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7198	0	0
SrcPulseCheck_M	7317763	7198	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7198	0	0
T1	130645	56	0	0
T2	213766	0	0	0
T5	0	68	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	76	0	0
T33	0	77	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	88	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7198	0	0
T1	13064	56	0	0
T2	654	0	0	0
T5	0	68	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T32	0	76	0	0
T33	0	77	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	67	0	0
T70	0	88	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7274	0	0
SrcPulseCheck_M	1441916269	7356	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7274	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	89	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T32	0	82	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	69	0	0
T70	0	66	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7356	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	90	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	82	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	69	0	0
T70	0	66	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7352	0	0
SrcPulseCheck_M	7317763	7352	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7352	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	90	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T32	0	82	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	69	0	0
T70	0	66	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7352	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	90	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T32	0	82	0	0
T33	0	66	0	0
T45	0	51	0	0
T49	0	51	0	0
T69	0	69	0	0
T70	0	66	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1231	0	0
SrcPulseCheck_M	1441916269	1309	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1231	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1309	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1306	0	0
SrcPulseCheck_M	7317763	1306	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1306	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1306	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1186	0	0
SrcPulseCheck_M	1441916269	1260	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1186	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1260	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1255	0	0
SrcPulseCheck_M	7317763	1255	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1255	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1255	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1209	0	0
SrcPulseCheck_M	1441916269	1280	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1209	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1280	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1274	0	0
SrcPulseCheck_M	7317763	1274	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1274	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1274	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1219	0	0
SrcPulseCheck_M	1441916269	1295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1219	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1295	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T1,T14,T26
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T26
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1289	0	0
SrcPulseCheck_M	7317763	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1289	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1289	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T33	0	7	0	0
T45	0	1	0	0
T49	0	1	0	0
T69	0	7	0	0
T70	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7672	0	0
SrcPulseCheck_M	1441916269	7750	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7672	0	0
T1	13064	71	0	0
T2	654	0	0	0
T5	0	76	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T27	0	1	0	0
T33	0	81	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7750	0	0
T1	130645	71	0	0
T2	213766	0	0	0
T5	0	76	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	81	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7745	0	0
SrcPulseCheck_M	7317763	7745	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7745	0	0
T1	130645	71	0	0
T2	213766	0	0	0
T5	0	76	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	81	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7745	0	0
T1	13064	71	0	0
T2	654	0	0	0
T5	0	76	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	81	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7632	0	0
SrcPulseCheck_M	1441916269	7707	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7632	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	81	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7707	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	82	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7700	0	0
SrcPulseCheck_M	7317763	7700	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7700	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	82	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7700	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	82	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7751	0	0
SrcPulseCheck_M	1441916269	7834	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7751	0	0
T1	13064	56	0	0
T2	654	0	0	0
T5	0	67	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T27	0	1	0	0
T33	0	77	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7834	0	0
T1	130645	56	0	0
T2	213766	0	0	0
T5	0	68	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	77	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	7828	0	0
SrcPulseCheck_M	7317763	7828	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	7828	0	0
T1	130645	56	0	0
T2	213766	0	0	0
T5	0	68	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	77	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7828	0	0
T1	13064	56	0	0
T2	654	0	0	0
T5	0	68	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	77	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	7941	0	0
SrcPulseCheck_M	1441916269	8025	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	7941	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	89	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	50	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	8025	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	90	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T1,T14,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T26
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	8019	0	0
SrcPulseCheck_M	7317763	8019	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	8019	0	0
T1	130645	61	0	0
T2	213766	0	0	0
T5	0	90	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	51	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	8019	0	0
T1	13064	61	0	0
T2	654	0	0	0
T5	0	90	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	51	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	51	0	0
T27	0	1	0	0
T33	0	66	0	0
T34	0	10	0	0
T45	0	51	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1898	0	0
SrcPulseCheck_M	1441916269	1976	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1898	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1976	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1971	0	0
SrcPulseCheck_M	7317763	1971	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1971	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1971	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1834	0	0
SrcPulseCheck_M	1441916269	1913	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1834	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1913	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1907	0	0
SrcPulseCheck_M	7317763	1907	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1907	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1907	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1825	0	0
SrcPulseCheck_M	1441916269	1901	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1825	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1901	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1896	0	0
SrcPulseCheck_M	7317763	1896	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1896	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1896	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1865	0	0
SrcPulseCheck_M	1441916269	1939	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1865	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1939	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1933	0	0
SrcPulseCheck_M	7317763	1933	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1933	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1933	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1894	0	0
SrcPulseCheck_M	1441916269	1972	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1894	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1972	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1965	0	0
SrcPulseCheck_M	7317763	1965	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1965	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1965	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1864	0	0
SrcPulseCheck_M	1441916269	1936	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1864	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1936	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1929	0	0
SrcPulseCheck_M	7317763	1929	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1929	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1929	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1879	0	0
SrcPulseCheck_M	1441916269	1956	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1879	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1956	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1952	0	0
SrcPulseCheck_M	7317763	1952	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1952	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1952	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7317763	1839	0	0
SrcPulseCheck_M	1441916269	1914	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1839	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1914	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T14,T27
1	1	Covered	T79,T80,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T14,T27
1	0	Covered	T79,T80,T19
1	1	Covered	T1,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1441916269	1909	0	0
SrcPulseCheck_M	7317763	1909	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1441916269	1909	0	0
T1	130645	4	0	0
T2	213766	0	0	0
T5	0	12	0	0
T6	177087	0	0	0
T7	62014	0	0	0
T12	0	24	0	0
T13	128558	0	0	0
T14	574479	1	0	0
T15	58711	0	0	0
T16	122618	0	0	0
T17	63208	0	0	0
T18	661724	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	7317763	1909	0	0
T1	13064	4	0	0
T2	654	0	0	0
T5	0	12	0	0
T6	36894	0	0	0
T7	496	0	0	0
T12	0	24	0	0
T13	503	0	0	0
T14	5222	1	0	0
T15	419	0	0	0
T16	490	0	0	0
T17	505	0	0	0
T18	55144	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T33	0	7	0	0
T34	0	10	0	0
T45	0	1	0	0
T47	0	1	0	0