Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
89.02	89.02	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	89.02	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.02	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	9	53	85.48

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	9	22	70.97	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1809

1

T1

14

T2

2

T5

32

auto[1]

632

1

T1

5

T2

2

T6

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1841

1

T1

19

T2

2

T5

32

auto[1]

600

1

T2

2

T6

3

T9

5

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1913

1

T1

18

T2

2

T5

24

auto[1]

528

1

T1

1

T2

2

T5

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1841

1

T1

6

T2

2

T5

32

auto[1]

600

1

T1

13

T2

2

T6

11

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2209

1

T1

19

T2

4

T5

24

auto[1]

232

1

T5

8

T6

3

T9

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2247

1

T1

19

T2

4

T5

24

auto[1]

194

1

T5

8

T8

1

T9

46

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2170

1

T1

19

T2

4

T5

32

auto[1]

271

1

T6

8

T8

1

T9

10

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2258

1

T1

19

T2

4

T5

32

auto[1]

183

1

T9

36

T70

7

T71

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2295

1

T1

19

T2

4

T5

32

auto[1]

146

1

T9

5

T70

6

T71

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1866

1

T1

13

T2

2

T5

32

auto[1]

575

1

T1

6

T2

2

T6

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	9	22	70.97	9
Automatically Generated Cross Bins	31	9	22	70.97	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	861	1			T1	19		T2	4		T10	2
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	84	1			T6	1		T347	4		T360	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	48	1			T78	7		T364	4		T365	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	10	1			T9	5		T248	3		T366	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	75	1			T121	4		T251	1		T102	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	15	1			T70	7		T121	4		T364	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T71	5		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	71	1			T6	4		T64	1		T121	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	40	1			T39	6		T111	4		T151	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	26	1			T70	6		T251	2		T367	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	16	1			T102	2		T368	3		T367	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T269	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T365	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	14	1			T104	1		T171	4		T369	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	30	1			T5	8		T370	2		T347	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	14	1			T261	4		T102	4		T371	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	46	1			T9	36		T372	4		T373	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T102	1		T374	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	46	1			T8	1		T9	10		T269	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	17	1			T111	3		T364	1		T365	1
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T240	3		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T375	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

114

1

T9

10

T155

1

T96

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

113

1

T9

18

T70

7

T111

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

54

1

T1

5

T27

5

T121

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

131

1

T1

13

T6

2

T27

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

55

1

T8

1

T26

3

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T2

2

T27

3

T111

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T6

2

T28

8

T104

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

101

1

T5

8

T121

4

T251

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

58

1

T10

1

T71

5

T18

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T1

1

T364

1

T376

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T9

18

T26

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T261

4

T227

4

T102

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T27

2

T75

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T195

4

T177

1

T267

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T97

1

T266

2

T177

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

98

1

T39

3

T28

11

T110

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T75

6

T102

5

T270

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T39

3

T117

3

T102

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T121

6

T97

1

T171

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T9

5

T70

6

T75

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T26

2

T34

1

T377

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T110

4

T262

4

T94

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T28

2

T155

1

T378

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T10

1

T28

1

T112

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T2

2

T133

6

T243

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T94

3

T133

2

T271

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T18

1

T110

2

T231

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

11

1

T253

1

T346

1

T379

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T93

1

T272

1

T362

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

11

1

T6

1

T352

3

T380

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T184

1

T381

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded