Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T21

5

T65

8

T18

26

auto[1]

1095

1

T21

15

T65

12

T18

34

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T21

5

T65

3

T18

16

from_0to1

527

1

T21

4

T65

2

T18

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T21

11

T65

6

T18

31

auto[1]

1065

1

T21

9

T65

14

T18

29

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T21

7

T65

6

T18

36

auto[1]

1070

1

T21

13

T65

14

T18

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T18

5

T20

2

T302

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T21

1

T20

2

T302

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T65

1

T18

1

T302

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T18

3

T20

2

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T18

1

T20

2

T112

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T18

1

T302

1

T112

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T34

1

T296

1

T230

2

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T21

1

T18

3

T302

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T21

1

T18

2

T296

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T21

2

T18

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T18

4

T302

1

T34

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T21

1

T65

2

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T21

1

T18

3

T20

3

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T18

3

T34

2

T112

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T21

1

T65

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T21

1

T65

1

T18

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T21

9

T65

10

T18

30

auto[1]

1115

1

T21

11

T65

10

T18

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T21

4

T65

5

T18

14

from_0to1

514

1

T21

5

T65

5

T18

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T21

11

T65

10

T18

29

auto[1]

1104

1

T21

9

T65

10

T18

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T21

12

T65

11

T18

27

auto[1]

1079

1

T21

8

T65

9

T18

33

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T65

2

T18

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T18

5

T112

2

T394

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T21

1

T18

2

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T18

1

T302

1

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T21

1

T65

1

T18

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T21

1

T18

3

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T21

2

T18

1

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T65

1

T18

5

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T21

1

T18

2

T302

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T21

2

T65

1

T112

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T65

1

T18

2

T20

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T65

1

T18

1

T302

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T21

1

T65

1

T18

2

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T302

2

T112

1

T296

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T65

1

T18

1

T302

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T65

1

T18

1

T34

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T21

8

T65

11

T18

36

auto[1]

1088

1

T21

12

T65

9

T18

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T21

5

T65

4

T18

17

from_0to1

516

1

T21

6

T65

4

T18

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T21

12

T65

9

T18

37

auto[1]

1015

1

T21

8

T65

11

T18

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T21

12

T65

11

T18

26

auto[1]

1117

1

T21

8

T65

9

T18

34

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T65

1

T18

3

T302

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T21

1

T65

1

T18

4

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T18

1

T226

1

T230

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T18

2

T34

1

T112

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T21

1

T18

6

T302

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T21

2

T65

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T21

1

T18

2

T112

2

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T65

1

T18

5

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T21

1

T18

3

T20

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T21

1

T18

4

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T21

1

T65

1

T112

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T21

1

T65

1

T34

2

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T21

1

T20

1

T112

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T18

2

T302

1

T34

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T21

1

T18

2

T302

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T65

2

T34

1

T296

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T21

8

T65

8

T18

35

auto[1]

1044

1

T21

12

T65

12

T18

25

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T21

6

T65

3

T18

18

from_0to1

524

1

T21

6

T65

3

T18

19

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T21

6

T65

10

T18

33

auto[1]

1097

1

T21

14

T65

10

T18

27

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T21

11

T65

9

T18

22

auto[1]

1059

1

T21

9

T65

11

T18

38

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T18

2

T20

2

T112

3

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T21

1

T18

3

T112

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T21

2

T18

3

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T65

2

T18

4

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T21

1

T18

3

T302

3

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T18

3

T20

1

T112

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T21

1

T18

1

T20

3

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T18

2

T20

1

T112

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T65

1

T34

1

T112

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T21

1

T18

4

T302

2

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T21

1

T18

1

T34

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T21

1

T18

1

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T21

1

T18

1

T34

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T65

3

T18

3

T20

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T21

2

T18

3

T34

2

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T21

1

T18

3

T302

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T21

10

T65

11

T18

28

auto[1]

1099

1

T21

10

T65

9

T18

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T21

5

T65

5

T18

16

from_0to1

533

1

T21

6

T65

6

T18

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T21

4

T65

6

T18

28

auto[1]

1083

1

T21

16

T65

14

T18

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T21

11

T65

11

T18

30

auto[1]

1103

1

T21

9

T65

9

T18

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T18

2

T34

1

T226

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T18

1

T34

2

T112

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T65

1

T18

1

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T65

3

T18

2

T20

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T18

2

T20

1

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T65

1

T18

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T21

1

T65

1

T18

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T21

3

T18

2

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T112

1

T226

1

T244

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T18

3

T302

2

T112

2

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T21

4

T18

4

T112

2

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T21

1

T65

1

T18

3

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T302

2

T230

1

T116

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T21

1

T65

1

T18

3

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T65

1

T18

3

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T21

1

T65

2

T18

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T21

10

T65

7

T18

35

auto[1]

1077

1

T21

10

T65

13

T18

25

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T21

4

T65

5

T18

15

from_0to1

520

1

T21

5

T65

5

T18

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T21

13

T65

6

T18

31

auto[1]

1008

1

T21

7

T65

14

T18

29

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T21

12

T65

13

T18

29

auto[1]

1028

1

T21

8

T65

7

T18

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T21

1

T18

3

T302

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T18

3

T226

1

T230

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T21

1

T65

2

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T65

2

T18

1

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T18

1

T20

4

T302

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T18

3

T20

1

T302

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T21

1

T18

3

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T21

1

T18

2

T112

3

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T18

2

T20

1

T302

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T21

2

T18

2

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T65

1

T18

2

T20

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T18

2

T112

3

T394

1

auto[1]

from_0to1

auto[0]

auto[0]

93

1

T21

2

T65

1

T18

2

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T21

1

T65

1

T18

3

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T65

2

T18

2

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T65

1

T20

1

T112

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T21

10

T65

7

T18

30

auto[1]

1067

1

T21

10

T65

13

T18

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T21

4

T65

5

T18

17

from_0to1

516

1

T21

4

T65

4

T18

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T21

12

T65

10

T18

27

auto[1]

1103

1

T21

8

T65

10

T18

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T21

7

T65

12

T18

22

auto[1]

1079

1

T21

13

T65

8

T18

38

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T65

1

T18

1

T302

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T21

1

T18

4

T20

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T21

1

T18

1

T230

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T21

1

T20

1

T302

1

auto[0]

from_0to1

auto[0]

auto[0]

81

1

T18

3

T20

1

T302

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T18

5

T34

1

T296

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T18

1

T20

1

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T21

1

T18

1

T302

2

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T21

1

T18

3

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T18

1

T20

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T65

2

T18

2

T20

1

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T65

2

T18

5

T302

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T21

1

T112

2

T394

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T21

1

T65

1

T18

3

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T65

1

T18

1

T20

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T21

1

T65

2

T18

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T21

7

T65

9

T18

28

auto[1]

1083

1

T21

13

T65

11

T18

32

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

513

1

T21

5

T65

5

T18

13

from_0to1

520

1

T21

5

T65

4

T18

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T21

8

T65

9

T18

23

auto[1]

1092

1

T21

12

T65

11

T18

37

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T21

8

T65

7

T18

26

auto[1]

1058

1

T21

12

T65

13

T18

34

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T65

1

T34

1

T296

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T65

1

T18

2

T20

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T65

1

T18

2

T302

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T18

1

T20

2

T296

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T18

2

T20

1

T302

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T65

1

T18

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T20

1

T302

1

T112

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T21

1

T18

5

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T21

2

T18

1

T302

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T65

2

T18

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T21

1

T18

2

T20

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T21

2

T18

4

T20

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T21

1

T20

3

T302

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T65

1

T18

3

T34

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T21

1

T18

2

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T21

2

T65

2

T18

1