Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115401

1

T1

237

T2

232

T4

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138128	1			T1	427		T2	391		T4	24
values[0x0]	63106	1			T1	38		T2	43		T4	7
values[0x1]	64181	1			T1	43		T2	38		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144135

1

T1

287

T2

272

T4

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	796	1			T2	1		T6	5		T21	2
valid_sources[0x01]	874	1			T1	2		T8	4		T27	3
valid_sources[0x02]	1070	1			T2	3		T27	1		T71	8
valid_sources[0x03]	808	1			T2	2		T6	11		T8	6
valid_sources[0x04]	721	1			T2	3		T12	1		T6	1
valid_sources[0x05]	773	1			T2	2		T8	2		T27	4
valid_sources[0x06]	920	1			T2	4		T21	1		T51	1
valid_sources[0x07]	996	1			T6	16		T299	1		T65	1
valid_sources[0x08]	1079	1			T2	2		T13	1		T6	14
valid_sources[0x09]	775	1			T2	8		T6	23		T22	1
valid_sources[0x0a]	766	1			T13	1		T8	5		T65	1
valid_sources[0x0b]	890	1			T2	1		T8	1		T27	3
valid_sources[0x0c]	809	1			T2	6		T10	20		T27	2
valid_sources[0x0d]	910	1			T2	6		T8	7		T21	1
valid_sources[0x0e]	1299	1			T2	1		T8	2		T21	1
valid_sources[0x0f]	851	1			T2	1		T4	1		T6	3
valid_sources[0x10]	874	1			T21	1		T65	1		T71	1
valid_sources[0x11]	937	1			T1	1		T4	1		T27	3
valid_sources[0x12]	1527	1			T2	1		T13	1		T8	3
valid_sources[0x13]	987	1			T8	18		T21	2		T27	1
valid_sources[0x14]	953	1			T6	8		T27	2		T65	1
valid_sources[0x15]	1002	1			T13	1		T6	7		T8	1
valid_sources[0x16]	1099	1			T4	1		T8	2		T114	1
valid_sources[0x17]	719	1			T6	8		T8	1		T27	6
valid_sources[0x18]	870	1			T12	1		T6	2		T27	8
valid_sources[0x19]	908	1			T2	4		T13	1		T27	2
valid_sources[0x1a]	823	1			T1	50		T6	11		T8	4
valid_sources[0x1b]	885	1			T1	2		T2	1		T71	2
valid_sources[0x1c]	801	1			T13	1		T27	5		T71	3
valid_sources[0x1d]	841	1			T2	4		T4	1		T12	1
valid_sources[0x1e]	1475	1			T4	2		T21	2		T113	12
valid_sources[0x1f]	911	1			T2	7		T6	46		T8	8
valid_sources[0x20]	746	1			T6	6		T8	11		T27	6
valid_sources[0x21]	949	1			T2	6		T21	1		T27	2
valid_sources[0x22]	1389	1			T2	3		T6	5		T8	3
valid_sources[0x23]	941	1			T1	1		T12	1		T8	1
valid_sources[0x24]	1277	1			T4	1		T12	1		T13	1
valid_sources[0x25]	1195	1			T2	1		T12	1		T6	5
valid_sources[0x26]	789	1			T2	3		T12	1		T8	5
valid_sources[0x27]	2648	1			T2	3		T8	2		T9	1600
valid_sources[0x28]	1351	1			T1	25		T2	1		T21	1
valid_sources[0x29]	968	1			T2	8		T4	1		T12	1
valid_sources[0x2a]	802	1			T2	1		T27	5		T71	4
valid_sources[0x2b]	749	1			T4	2		T8	5		T71	1
valid_sources[0x2c]	1496	1			T2	9		T12	1		T6	5
valid_sources[0x2d]	1042	1			T2	6		T21	1		T10	4
valid_sources[0x2e]	1009	1			T1	1		T8	2		T27	2
valid_sources[0x2f]	742	1			T4	1		T6	6		T8	5
valid_sources[0x30]	1314	1			T2	1		T6	6		T27	2
valid_sources[0x31]	891	1			T1	4		T2	9		T21	1
valid_sources[0x32]	870	1			T2	2		T6	1		T8	1
valid_sources[0x33]	969	1			T2	6		T7	6		T8	5
valid_sources[0x34]	872	1			T2	2		T12	1		T6	9
valid_sources[0x35]	998	1			T2	14		T6	15		T8	1
valid_sources[0x36]	782	1			T2	1		T4	1		T27	1
valid_sources[0x37]	889	1			T2	4		T8	3		T21	1
valid_sources[0x38]	748	1			T2	1		T6	5		T27	2
valid_sources[0x39]	1333	1			T8	8		T27	1		T65	1
valid_sources[0x3a]	835	1			T2	6		T8	3		T21	1
valid_sources[0x3b]	1902	1			T12	1		T8	2		T27	1
valid_sources[0x3c]	698	1			T2	2		T22	1		T8	9
valid_sources[0x3d]	1013	1			T1	4		T2	1		T4	1
valid_sources[0x3e]	677	1			T27	4		T71	6		T18	2
valid_sources[0x3f]	876	1			T2	3		T6	1		T47	6
valid_sources[0x40]	1403	1			T8	1		T65	1		T71	5
valid_sources[0x41]	1608	1			T2	6		T8	3		T21	1
valid_sources[0x42]	2154	1			T2	1		T4	2		T8	5
valid_sources[0x43]	841	1			T65	1		T71	1		T18	5
valid_sources[0x44]	1833	1			T1	1		T2	4		T6	1
valid_sources[0x45]	905	1			T1	6		T8	1		T21	2
valid_sources[0x46]	934	1			T6	3		T8	3		T27	2
valid_sources[0x47]	955	1			T1	29		T4	1		T21	1
valid_sources[0x48]	870	1			T1	1		T2	2		T8	4
valid_sources[0x49]	801	1			T6	3		T22	1		T8	3
valid_sources[0x4a]	813	1			T2	4		T4	1		T22	1
valid_sources[0x4b]	886	1			T2	1		T8	1		T21	1
valid_sources[0x4c]	1230	1			T12	1		T8	3		T27	1
valid_sources[0x4d]	1820	1			T2	1		T6	26		T8	1
valid_sources[0x4e]	903	1			T6	10		T27	1		T65	1
valid_sources[0x4f]	807	1			T2	1		T8	4		T27	3
valid_sources[0x50]	721	1			T8	6		T51	1		T27	2
valid_sources[0x51]	1188	1			T2	3		T6	16		T8	17
valid_sources[0x52]	908	1			T2	1		T12	1		T6	11
valid_sources[0x53]	874	1			T2	2		T8	3		T10	20
valid_sources[0x54]	1256	1			T2	4		T8	7		T21	1
valid_sources[0x55]	860	1			T1	6		T2	5		T6	9
valid_sources[0x56]	893	1			T2	11		T6	2		T22	2
valid_sources[0x57]	850	1			T8	3		T27	4		T70	24
valid_sources[0x58]	1077	1			T2	1		T12	1		T8	1
valid_sources[0x59]	909	1			T8	9		T21	1		T27	1
valid_sources[0x5a]	928	1			T6	4		T8	12		T21	1
valid_sources[0x5b]	1627	1			T1	1		T2	2		T6	15
valid_sources[0x5c]	1422	1			T6	1		T8	4		T21	1
valid_sources[0x5d]	719	1			T1	7		T2	2		T8	3
valid_sources[0x5e]	1120	1			T1	6		T2	1		T6	4
valid_sources[0x5f]	780	1			T2	1		T12	1		T8	6
valid_sources[0x60]	975	1			T2	3		T12	2		T6	1
valid_sources[0x61]	830	1			T2	2		T8	2		T27	4
valid_sources[0x62]	806	1			T1	1		T12	2		T8	1
valid_sources[0x63]	952	1			T2	3		T12	1		T6	1
valid_sources[0x64]	789	1			T2	1		T6	18		T8	3
valid_sources[0x65]	815	1			T13	1		T8	1		T114	1
valid_sources[0x66]	2126	1			T6	8		T27	2		T71	5
valid_sources[0x67]	867	1			T2	5		T12	1		T21	1
valid_sources[0x68]	896	1			T12	2		T13	1		T8	24
valid_sources[0x69]	1247	1			T2	1		T12	2		T6	7
valid_sources[0x6a]	1020	1			T1	2		T12	1		T27	3
valid_sources[0x6b]	743	1			T1	27		T6	1		T21	2
valid_sources[0x6c]	862	1			T2	2		T4	2		T3	28
valid_sources[0x6d]	935	1			T22	1		T8	5		T21	1
valid_sources[0x6e]	853	1			T1	8		T2	1		T22	1
valid_sources[0x6f]	781	1			T2	2		T6	22		T8	5
valid_sources[0x70]	2540	1			T6	14		T71	2		T18	7
valid_sources[0x71]	749	1			T2	4		T22	2		T27	2
valid_sources[0x72]	1768	1			T6	6		T27	2		T65	1
valid_sources[0x73]	1235	1			T2	5		T6	10		T21	1
valid_sources[0x74]	1012	1			T21	1		T27	10		T299	3
valid_sources[0x75]	856	1			T2	2		T12	1		T6	5
valid_sources[0x76]	1077	1			T1	16		T2	2		T12	1
valid_sources[0x77]	907	1			T2	4		T21	1		T27	2
valid_sources[0x78]	1049	1			T2	6		T6	3		T65	1
valid_sources[0x79]	1183	1			T1	5		T2	2		T8	8
valid_sources[0x7a]	876	1			T8	2		T27	4		T71	1
valid_sources[0x7b]	1325	1			T2	2		T21	1		T10	95
valid_sources[0x7c]	850	1			T1	6		T6	2		T8	2
valid_sources[0x7d]	1019	1			T2	1		T8	2		T21	1
valid_sources[0x7e]	933	1			T2	1		T4	1		T21	2
valid_sources[0x7f]	734	1			T8	2		T71	3		T18	5
valid_sources[0x80]	862	1			T2	2		T6	17		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62856

1

T1

214

T2

193

T4

12

values[0x0]

all_enables

biggest_size

30738

1

T1

14

T2

21

T4

4

values[0x1]

all_enables

biggest_size

21807

1

T1

9

T2

18

T4

4