Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T22,T18,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T22,T18,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T22,T18,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T18,T41
1	0	Covered	T1,T2,T4
1	1	Covered	T22,T18,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T41
0	1	Covered	T77,T99
1	0	Covered	T49

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T18,T41
0	1	Covered	T22,T18,T41
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T18,T41
1	-	Covered	T22,T18,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T18,T41
DetectSt	168	Covered	T22,T18,T41
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T22,T18,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T18,T41
DebounceSt->IdleSt	163	Covered	T20,T28,T42
DetectSt->IdleSt	186	Covered	T77,T49,T99
DetectSt->StableSt	191	Covered	T22,T18,T41
IdleSt->DebounceSt	148	Covered	T22,T18,T41
StableSt->IdleSt	206	Covered	T22,T18,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T18,T41
0	1	Covered	T22,T18,T41
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T18,T41
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T18,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T18,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T42,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T18,T41
DetectSt	-	-	-	-	1	-	-	Covered	T77,T49,T99
DetectSt	-	-	-	-	0	1	-	Covered	T22,T18,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T18,T41
StableSt	-	-	-	-	-	-	0	Covered	T22,T18,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	283	0	0
CntIncr_A	7861742	207343	0	0
CntNoWrap_A	7861742	7219827	0	0
DetectStDropOut_A	7861742	2	0	0
DetectedOut_A	7861742	868	0	0
DetectedPulseOut_A	7861742	127	0	0
DisabledIdleSt_A	7861742	7006135	0	0
DisabledNoDetection_A	7861742	7008353	0	0
EnterDebounceSt_A	7861742	157	0	0
EnterDetectSt_A	7861742	130	0	0
EnterStableSt_A	7861742	127	0	0
PulseIsPulse_A	7861742	127	0	0
StayInStableSt	7861742	741	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6663	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	126	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	283	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	2	0	0
T20	0	2	0	0
T21	509	0	0	0
T22	715	4	0	0
T28	0	1	0	0
T41	0	2	0	0
T42	0	5	0	0
T43	0	5	0	0
T44	0	6	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	4	0	0
T87	0	2	0	0
T88	404	0	0	0
T89	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	207343	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	46	0	0
T20	0	10889	0	0
T21	509	0	0	0
T22	715	92	0	0
T28	0	38	0	0
T41	0	63	0	0
T42	0	144	0	0
T43	0	170	0	0
T44	0	213	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	88	0	0
T87	0	62	0	0
T88	404	0	0	0
T89	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219827	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2	0	0
T49	7945	0	0	0
T77	622	1	0	0
T99	0	1	0	0
T102	25764	0	0	0
T103	402	0	0	0
T104	9146	0	0	0
T105	132009	0	0	0
T106	695	0	0	0
T107	6052	0	0	0
T108	493	0	0	0
T109	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	868	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	4	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	19	0	0
T41	0	10	0	0
T42	0	20	0	0
T43	0	16	0	0
T44	0	24	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	18	0	0
T87	0	4	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	127	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	509	0	0	0
T22	715	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7006135	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7008353	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	157	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T21	509	0	0	0
T22	715	2	0	0
T28	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	130	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	509	0	0	0
T22	715	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	127	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	509	0	0	0
T22	715	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	127	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	509	0	0	0
T22	715	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	741	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	3	0	0
T20	0	2	0	0
T21	509	0	0	0
T22	715	17	0	0
T41	0	9	0	0
T42	0	18	0	0
T43	0	14	0	0
T44	0	21	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	16	0	0
T87	0	3	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	21	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6663	0	0
T1	8172	13	0	0
T2	13431	12	0	0
T3	1179	6	0	0
T4	2117	3	0	0
T5	23603	30	0	0
T6	12030	28	0	0
T7	136751	6	0	0
T12	524	4	0	0
T13	614	3	0	0
T14	423	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	126	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	509	0	0	0
T22	715	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T112	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T20,T74,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Unreachable
1	0	Covered	T3,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T3,T7,T10
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T10
DebounceSt->IdleSt	163	Covered	T11,T20,T74
DetectSt->IdleSt	186	Covered	T20,T74,T85
DetectSt->StableSt	191	Covered	T3,T7,T10
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T10
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T20,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T20,T74,T85
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	136	0	0
CntIncr_A	7861742	255095	0	0
CntNoWrap_A	7861742	7219974	0	0
DetectStDropOut_A	7861742	10	0	0
DetectedOut_A	7861742	246665	0	0
DetectedPulseOut_A	7861742	51	0	0
DisabledIdleSt_A	7861742	6452181	0	0
DisabledNoDetection_A	7861742	6454445	0	0
EnterDebounceSt_A	7861742	77	0	0
EnterDetectSt_A	7861742	61	0	0
EnterStableSt_A	7861742	51	0	0
PulseIsPulse_A	7861742	51	0	0
StayInStableSt	7861742	246614	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6663	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_sticky_sva.StableStDropOut_A	7861742	264034	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	136	0	0
T3	1179	2	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	4	0	0
T8	7275	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	423	0	0	0
T18	0	2	0	0
T20	0	9	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	4	0	0
T72	0	2	0	0
T73	0	4	0	0
T74	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	255095	0	0
T3	1179	52	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	105	0	0
T8	7275	0	0	0
T10	0	16	0	0
T11	0	194	0	0
T14	423	0	0	0
T18	0	85	0	0
T20	0	325	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	34	0	0
T72	0	58826	0	0
T73	0	48	0	0
T74	0	244	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219974	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	776	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134743	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	10	0	0
T20	128362	1	0	0
T28	53166	0	0	0
T36	501	0	0	0
T74	0	2	0	0
T75	28571	0	0	0
T85	0	3	0	0
T101	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	246665	0	0
T3	1179	151	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	109	0	0
T8	7275	0	0	0
T10	0	19	0	0
T14	423	0	0	0
T18	0	466	0	0
T20	0	71	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	150	0	0
T72	0	52812	0	0
T73	0	180	0	0
T74	0	1	0	0
T79	0	206	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T3	1179	1	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T79	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6452181	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	411	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134269	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6454445	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	412	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134273	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	77	0	0
T3	1179	1	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T11	0	2	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	6	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	61	0	0
T3	1179	1	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	3	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	3	0	0
T79	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T3	1179	1	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T79	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T3	1179	1	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T79	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	246614	0	0
T3	1179	150	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	107	0	0
T8	7275	0	0	0
T10	0	18	0	0
T14	423	0	0	0
T18	0	465	0	0
T20	0	69	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	148	0	0
T72	0	52811	0	0
T73	0	178	0	0
T79	0	205	0	0
T115	0	340	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6663	0	0
T1	8172	13	0	0
T2	13431	12	0	0
T3	1179	6	0	0
T4	2117	3	0	0
T5	23603	30	0	0
T6	12030	28	0	0
T7	136751	6	0	0
T12	524	4	0	0
T13	614	3	0	0
T14	423	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	264034	0	0
T3	1179	144	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	238	0	0
T8	7275	0	0	0
T10	0	161	0	0
T14	423	0	0	0
T18	0	101	0	0
T20	0	100469	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	927	0	0
T72	0	24	0	0
T73	0	575	0	0
T74	0	115	0	0
T79	0	227	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T12,T3
1	1	Covered	T4,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T4,T12,T3
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T20,T79,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Unreachable
1	0	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T7,T10,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T11
DebounceSt->IdleSt	163	Covered	T3,T79,T49
DetectSt->IdleSt	186	Covered	T20,T79,T84
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T79,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T20,T79,T84
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	137	0	0
CntIncr_A	7861742	83093	0	0
CntNoWrap_A	7861742	7219973	0	0
DetectStDropOut_A	7861742	10	0	0
DetectedOut_A	7861742	71132	0	0
DetectedPulseOut_A	7861742	42	0	0
DisabledIdleSt_A	7861742	6452181	0	0
DisabledNoDetection_A	7861742	6454445	0	0
EnterDebounceSt_A	7861742	87	0	0
EnterDetectSt_A	7861742	52	0	0
EnterStableSt_A	7861742	42	0	0
PulseIsPulse_A	7861742	42	0	0
StayInStableSt	7861742	71090	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_sticky_sva.StableStDropOut_A	7861742	596412	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	137	0	0
T3	1179	3	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	4	0	0
T8	7275	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	423	0	0	0
T18	0	2	0	0
T20	0	8	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	4	0	0
T72	0	2	0	0
T73	0	4	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	83093	0	0
T3	1179	33	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	108	0	0
T8	7275	0	0	0
T10	0	19	0	0
T11	0	57	0	0
T14	423	0	0	0
T18	0	42	0	0
T20	0	157	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	164	0	0
T72	0	14	0	0
T73	0	120	0	0
T74	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219973	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	775	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134743	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	10	0	0
T20	128362	1	0	0
T28	53166	0	0	0
T36	501	0	0	0
T75	28571	0	0	0
T79	0	2	0	0
T84	0	1	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T128	0	4	0	0
T129	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	71132	0	0
T7	136751	60	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	46	0	0
T11	0	60	0	0
T18	0	227	0	0
T20	0	186	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	772	0	0
T72	0	7	0	0
T73	0	397	0	0
T74	0	445	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	510	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	42	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6452181	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	411	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134269	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6454445	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	412	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134273	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	87	0	0
T3	1179	3	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	4	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	52	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	4	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T79	0	2	0	0
T88	404	0	0	0
T89	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	42	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	42	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	71090	0	0
T7	136751	58	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	45	0	0
T11	0	59	0	0
T18	0	226	0	0
T20	0	183	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	770	0	0
T72	0	6	0	0
T73	0	395	0	0
T74	0	444	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	509	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	596412	0	0
T7	136751	265	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	133	0	0
T11	0	160	0	0
T18	0	389	0	0
T20	0	100599	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	165	0	0
T72	0	111649	0	0
T73	0	284	0	0
T74	0	160	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	85	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T7,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T79,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Unreachable
1	0	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T7,T10,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T11
DebounceSt->IdleSt	163	Covered	T3,T72,T74
DetectSt->IdleSt	186	Covered	T79,T80,T81
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T72,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T79,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	141	0	0
CntIncr_A	7861742	56561	0	0
CntNoWrap_A	7861742	7219969	0	0
DetectStDropOut_A	7861742	11	0	0
DetectedOut_A	7861742	66321	0	0
DetectedPulseOut_A	7861742	44	0	0
DisabledIdleSt_A	7861742	6452181	0	0
DisabledNoDetection_A	7861742	6454445	0	0
EnterDebounceSt_A	7861742	88	0	0
EnterDetectSt_A	7861742	55	0	0
EnterStableSt_A	7861742	44	0	0
PulseIsPulse_A	7861742	44	0	0
StayInStableSt	7861742	66277	0	0
gen_high_event_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_sticky_sva.StableStDropOut_A	7861742	529734	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	141	0	0
T3	1179	3	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	4	0	0
T8	7275	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T14	423	0	0	0
T18	0	2	0	0
T20	0	6	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	4	0	0
T72	0	1	0	0
T73	0	4	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	56561	0	0
T3	1179	138	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	111	0	0
T8	7275	0	0	0
T10	0	84	0	0
T11	0	41	0	0
T14	423	0	0	0
T18	0	25	0	0
T20	0	39087	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	164	0	0
T72	0	40	0	0
T73	0	162	0	0
T74	0	160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219969	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	775	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134743	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	11	0	0
T79	942	2	0	0
T80	0	2	0	0
T81	0	1	0	0
T95	5316	0	0	0
T101	0	3	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	17310	0	0	0
T134	495	0	0	0
T135	581	0	0	0
T136	422	0	0	0
T137	405	0	0	0
T138	403	0	0	0
T139	695	0	0	0
T140	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	66321	0	0
T7	136751	240	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	87	0	0
T11	0	71	0	0
T18	0	87	0	0
T20	0	61716	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	862	0	0
T73	0	564	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	144	0	0
T116	0	131	0	0
T117	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	44	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T73	0	2	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6452181	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	411	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134269	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6454445	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	412	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134273	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	88	0	0
T3	1179	3	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T14	423	0	0	0
T18	0	1	0	0
T20	0	3	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	55	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T73	0	2	0	0
T79	0	2	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	44	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T73	0	2	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	44	0	0
T7	136751	2	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	0	1	0	0
T20	0	3	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	2	0	0
T73	0	2	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	66277	0	0
T7	136751	238	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	86	0	0
T11	0	70	0	0
T18	0	86	0	0
T20	0	61713	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	860	0	0
T73	0	562	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	143	0	0
T116	0	130	0	0
T117	0	89	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	529734	0	0
T7	136751	114	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T10	0	34	0	0
T11	0	166	0	0
T18	0	549	0	0
T20	0	182	0	0
T21	509	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T53	0	98	0	0
T73	0	98	0	0
T88	404	0	0	0
T89	403	0	0	0
T115	0	544	0	0
T116	0	397	0	0
T117	0	208	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T18,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T18,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T18,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T35
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T18,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T35
0	1	Covered	T141
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T35
0	1	Covered	T19,T34,T32
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T35
1	-	Covered	T19,T34,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T35
DetectSt	168	Covered	T1,T18,T35
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T18,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T35
DebounceSt->IdleSt	163	Covered	T142
DetectSt->IdleSt	186	Covered	T141
DetectSt->StableSt	191	Covered	T1,T18,T35
IdleSt->DebounceSt	148	Covered	T1,T18,T35
StableSt->IdleSt	206	Covered	T1,T18,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T18,T35
0	1	Covered	T1,T18,T35
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T35
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T142
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T35
DetectSt	-	-	-	-	1	-	-	Covered	T141
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T34,T32
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	103	0	0
CntIncr_A	7861742	88986	0	0
CntNoWrap_A	7861742	7220007	0	0
DetectStDropOut_A	7861742	1	0	0
DetectedOut_A	7861742	51390	0	0
DetectedPulseOut_A	7861742	50	0	0
DisabledIdleSt_A	7861742	6980048	0	0
DisabledNoDetection_A	7861742	6982249	0	0
EnterDebounceSt_A	7861742	52	0	0
EnterDetectSt_A	7861742	51	0	0
EnterStableSt_A	7861742	50	0	0
PulseIsPulse_A	7861742	50	0	0
StayInStableSt	7861742	51316	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	103	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	6	0	0
T29	0	2	0	0
T32	0	4	0	0
T34	0	4	0	0
T35	0	2	0	0
T83	0	4	0	0
T143	0	2	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	88986	0	0
T1	8172	63	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	77	0	0
T19	0	198	0	0
T29	0	73	0	0
T32	0	166	0	0
T34	0	54	0	0
T35	0	88	0	0
T83	0	110	0	0
T143	0	25	0	0
T144	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220007	0	0
T1	8172	6966	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1	0	0
T141	14112	1	0	0
T145	41071	0	0	0
T146	7374	0	0	0
T147	588	0	0	0
T148	402	0	0	0
T149	498	0	0	0
T150	402	0	0	0
T151	12729	0	0	0
T152	402	0	0	0
T153	782	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51390	0	0
T1	8172	39	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	295	0	0
T19	0	125	0	0
T29	0	338	0	0
T32	0	327	0	0
T34	0	86	0	0
T35	0	43	0	0
T83	0	126	0	0
T143	0	43	0	0
T144	0	149	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	50	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	3	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6980048	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6982249	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	52	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	3	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	3	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	50	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	3	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	50	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	3	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51316	0	0
T1	8172	37	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	293	0	0
T19	0	121	0	0
T29	0	336	0	0
T32	0	324	0	0
T34	0	84	0	0
T35	0	41	0	0
T83	0	124	0	0
T143	0	41	0	0
T144	0	148	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	24	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T75	28571	0	0	0
T81	0	1	0	0
T83	0	2	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T144	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T35
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T10,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T29
0	1	Covered	T35,T34,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T29
0	1	Covered	T1,T10,T29
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T29
1	-	Covered	T1,T10,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T35
DetectSt	168	Covered	T1,T10,T35
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T35
DebounceSt->IdleSt	163	Covered	T36,T143,T83
DetectSt->IdleSt	186	Covered	T35,T34,T81
DetectSt->StableSt	191	Covered	T1,T10,T29
IdleSt->DebounceSt	148	Covered	T1,T10,T35
StableSt->IdleSt	206	Covered	T1,T10,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T35
0	1	Covered	T1,T10,T35
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T35
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T143,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35,T34,T81
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T29
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	117	0	0
CntIncr_A	7861742	89534	0	0
CntNoWrap_A	7861742	7219993	0	0
DetectStDropOut_A	7861742	3	0	0
DetectedOut_A	7861742	3737	0	0
DetectedPulseOut_A	7861742	51	0	0
DisabledIdleSt_A	7861742	6985024	0	0
DisabledNoDetection_A	7861742	6987237	0	0
EnterDebounceSt_A	7861742	63	0	0
EnterDetectSt_A	7861742	54	0	0
EnterStableSt_A	7861742	51	0	0
PulseIsPulse_A	7861742	51	0	0
StayInStableSt	7861742	3660	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	2568	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	117	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	6	0	0
T29	0	2	0	0
T34	0	6	0	0
T35	0	2	0	0
T36	0	1	0	0
T44	0	2	0	0
T83	0	3	0	0
T143	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	89534	0	0
T1	8172	63	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	47	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	198	0	0
T29	0	73	0	0
T34	0	81	0	0
T35	0	88	0	0
T36	0	43	0	0
T44	0	14	0	0
T83	0	140	0	0
T143	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219993	0	0
T1	8172	6966	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T34	0	1	0	0
T35	630	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T81	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3737	0	0
T1	8172	105	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	29	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	94	0	0
T29	0	43	0	0
T34	0	112	0	0
T44	0	41	0	0
T49	0	28	0	0
T83	0	61	0	0
T154	0	131	0	0
T158	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	3	0	0
T29	0	1	0	0
T34	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T154	0	2	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6985024	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6987237	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	63	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	3	0	0
T29	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	0	1	0	0
T83	0	2	0	0
T143	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	54	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	3	0	0
T29	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T44	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T154	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	3	0	0
T29	0	1	0	0
T34	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T154	0	2	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	3	0	0
T29	0	1	0	0
T34	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T154	0	2	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3660	0	0
T1	8172	104	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	28	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	91	0	0
T29	0	42	0	0
T34	0	109	0	0
T44	0	39	0	0
T49	0	27	0	0
T83	0	59	0	0
T154	0	128	0	0
T158	0	136	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2568	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	4	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	2	0	0
T10	0	13	0	0
T12	524	6	0	0
T13	614	0	0	0
T14	423	1	0	0
T21	0	7	0	0
T46	0	2	0	0
T113	0	2	0	0
T114	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	23	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	3	0	0
T29	0	1	0	0
T34	0	1	0	0
T154	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0