Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T10,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T19
0	1	Covered	T1,T18,T19
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T19
1	-	Covered	T1,T18,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T18
DetectSt	168	Covered	T1,T10,T18
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T18
DebounceSt->IdleSt	163	Covered	T163,T164
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T10,T18
IdleSt->DebounceSt	148	Covered	T1,T10,T18
StableSt->IdleSt	206	Covered	T1,T10,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T18
0	1	Covered	T1,T10,T18
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T18
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	62	0	0
CntIncr_A	7861742	1868	0	0
CntNoWrap_A	7861742	7220048	0	0
DetectStDropOut_A	7861742	0	0	0
DetectedOut_A	7861742	1592	0	0
DetectedPulseOut_A	7861742	30	0	0
DisabledIdleSt_A	7861742	7206640	0	0
DisabledNoDetection_A	7861742	7208864	0	0
EnterDebounceSt_A	7861742	32	0	0
EnterDetectSt_A	7861742	30	0	0
EnterStableSt_A	7861742	30	0	0
PulseIsPulse_A	7861742	30	0	0
StayInStableSt	7861742	1550	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	62	0	0
T1	8172	4	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T49	0	2	0	0
T154	0	2	0	0
T163	0	1	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1868	0	0
T1	8172	126	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	47	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	77	0	0
T19	0	66	0	0
T30	0	55	0	0
T32	0	83	0	0
T49	0	15	0	0
T154	0	79	0	0
T163	0	34	0	0
T165	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220048	0	0
T1	8172	6964	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1592	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	44	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	124	0	0
T30	0	43	0	0
T32	0	193	0	0
T49	0	29	0	0
T141	0	50	0	0
T154	0	141	0	0
T165	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	30	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T141	0	1	0	0
T154	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7206640	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7208864	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	32	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	30	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T141	0	1	0	0
T154	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	30	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T141	0	1	0	0
T154	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	30	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T141	0	1	0	0
T154	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1550	0	0
T1	8172	11	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	42	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T19	0	123	0	0
T30	0	42	0	0
T32	0	192	0	0
T49	0	28	0	0
T141	0	48	0	0
T154	0	140	0	0
T156	0	45	0	0
T165	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	16	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T97	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T18,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T18,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T18,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T35
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T18,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T35
0	1	Covered	T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T35
0	1	Covered	T1,T18,T29
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T35
1	-	Covered	T1,T18,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T35
DetectSt	168	Covered	T1,T18,T35
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T18,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T35
DebounceSt->IdleSt	163	Covered	T32,T166,T168
DetectSt->IdleSt	186	Covered	T167
DetectSt->StableSt	191	Covered	T1,T18,T35
IdleSt->DebounceSt	148	Covered	T1,T18,T35
StableSt->IdleSt	206	Covered	T1,T18,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T18,T35
0	1	Covered	T1,T18,T35
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T35
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T166,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T35
DetectSt	-	-	-	-	1	-	-	Covered	T167
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T29
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	142	0	0
CntIncr_A	7861742	3967	0	0
CntNoWrap_A	7861742	7219968	0	0
DetectStDropOut_A	7861742	2	0	0
DetectedOut_A	7861742	5030	0	0
DetectedPulseOut_A	7861742	65	0	0
DisabledIdleSt_A	7861742	7202142	0	0
DisabledNoDetection_A	7861742	7204352	0	0
EnterDebounceSt_A	7861742	75	0	0
EnterDetectSt_A	7861742	67	0	0
EnterStableSt_A	7861742	65	0	0
PulseIsPulse_A	7861742	65	0	0
StayInStableSt	7861742	4937	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	2912	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	142	0	0
T1	8172	6	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	6	0	0
T19	0	4	0	0
T29	0	4	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T82	0	2	0	0
T163	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3967	0	0
T1	8172	189	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	276	0	0
T19	0	132	0	0
T29	0	146	0	0
T32	0	166	0	0
T33	0	85	0	0
T35	0	88	0	0
T36	0	43	0	0
T82	0	24	0	0
T163	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219968	0	0
T1	8172	6962	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2	0	0
T167	17928	2	0	0
T169	675	0	0	0
T170	523	0	0	0
T171	17285	0	0	0
T172	522	0	0	0
T173	506	0	0	0
T174	8402	0	0	0
T175	617	0	0	0
T176	496	0	0	0
T177	11306	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	5030	0	0
T1	8172	186	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	215	0	0
T19	0	164	0	0
T29	0	129	0	0
T32	0	49	0	0
T33	0	46	0	0
T35	0	43	0	0
T36	0	48	0	0
T82	0	65	0	0
T163	0	123	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	65	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T19	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T82	0	1	0	0
T163	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7202142	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7204352	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	75	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T19	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T82	0	1	0	0
T163	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	67	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T19	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T82	0	1	0	0
T163	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	65	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T19	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T82	0	1	0	0
T163	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	65	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T19	0	2	0	0
T29	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T82	0	1	0	0
T163	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	4937	0	0
T1	8172	182	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	211	0	0
T19	0	161	0	0
T29	0	127	0	0
T32	0	47	0	0
T33	0	44	0	0
T35	0	41	0	0
T36	0	46	0	0
T82	0	63	0	0
T163	0	120	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2912	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	2	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	4	0	0
T10	0	17	0	0
T12	524	6	0	0
T13	614	0	0	0
T14	423	2	0	0
T21	0	6	0	0
T46	0	3	0	0
T47	0	5	0	0
T51	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	35	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T83	0	1	0	0
T141	0	1	0	0
T153	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T37
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T10,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T37
0	1	Covered	T178,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T37
0	1	Covered	T1,T10,T34
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T37
1	-	Covered	T1,T10,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T37
DetectSt	168	Covered	T1,T10,T37
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T37
DebounceSt->IdleSt	163	Covered	T180,T156,T181
DetectSt->IdleSt	186	Covered	T178,T179
DetectSt->StableSt	191	Covered	T1,T10,T37
IdleSt->DebounceSt	148	Covered	T1,T10,T37
StableSt->IdleSt	206	Covered	T1,T10,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T37
0	1	Covered	T1,T10,T37
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T37
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T180,T156,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T37
DetectSt	-	-	-	-	1	-	-	Covered	T178,T179
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	119	0	0
CntIncr_A	7861742	3361	0	0
CntNoWrap_A	7861742	7219991	0	0
DetectStDropOut_A	7861742	2	0	0
DetectedOut_A	7861742	4718	0	0
DetectedPulseOut_A	7861742	55	0	0
DisabledIdleSt_A	7861742	7204426	0	0
DisabledNoDetection_A	7861742	7206644	0	0
EnterDebounceSt_A	7861742	62	0	0
EnterDetectSt_A	7861742	57	0	0
EnterStableSt_A	7861742	55	0	0
PulseIsPulse_A	7861742	55	0	0
StayInStableSt	7861742	4637	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	119	0	0
T1	8172	4	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	4	0	0
T34	0	4	0	0
T37	0	2	0	0
T49	0	2	0	0
T83	0	2	0	0
T144	0	4	0	0
T180	0	1	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3361	0	0
T1	8172	126	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	47	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	110	0	0
T34	0	54	0	0
T37	0	71	0	0
T49	0	15	0	0
T83	0	70	0	0
T144	0	186	0	0
T180	0	37	0	0
T182	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219991	0	0
T1	8172	6964	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2	0	0
T178	997	1	0	0
T179	0	1	0	0
T183	522	0	0	0
T184	16158	0	0	0
T185	8293	0	0	0
T186	5222	0	0	0
T187	503	0	0	0
T188	408	0	0	0
T189	402	0	0	0
T190	525	0	0	0
T191	442	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	4718	0	0
T1	8172	40	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	27	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	62	0	0
T34	0	110	0	0
T37	0	226	0	0
T49	0	29	0	0
T83	0	214	0	0
T144	0	86	0	0
T159	0	205	0	0
T182	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	55	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T144	0	2	0	0
T159	0	2	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7204426	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7206644	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	62	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T144	0	2	0	0
T180	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	57	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T144	0	2	0	0
T159	0	2	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	55	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T144	0	2	0	0
T159	0	2	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	55	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T37	0	1	0	0
T49	0	1	0	0
T83	0	1	0	0
T144	0	2	0	0
T159	0	2	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	4637	0	0
T1	8172	38	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	26	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	60	0	0
T34	0	108	0	0
T37	0	224	0	0
T49	0	28	0	0
T83	0	212	0	0
T144	0	83	0	0
T159	0	202	0	0
T182	0	116	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	27	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T141	0	1	0	0
T144	0	1	0	0
T157	0	2	0	0
T159	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T10,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Covered	T1,T18,T34
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T18
1	-	Covered	T1,T18,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T18
DetectSt	168	Covered	T1,T10,T18
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T18
DebounceSt->IdleSt	163	Covered	T154
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T10,T18
IdleSt->DebounceSt	148	Covered	T1,T10,T18
StableSt->IdleSt	206	Covered	T1,T10,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T18
0	1	Covered	T1,T10,T18
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T18
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T154
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	81	0	0
CntIncr_A	7861742	2226	0	0
CntNoWrap_A	7861742	7220029	0	0
DetectStDropOut_A	7861742	0	0	0
DetectedOut_A	7861742	2509	0	0
DetectedPulseOut_A	7861742	40	0	0
DisabledIdleSt_A	7861742	7202655	0	0
DisabledNoDetection_A	7861742	7204867	0	0
EnterDebounceSt_A	7861742	41	0	0
EnterDetectSt_A	7861742	40	0	0
EnterStableSt_A	7861742	40	0	0
PulseIsPulse_A	7861742	40	0	0
StayInStableSt	7861742	2448	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6342	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	81	0	0
T1	8172	4	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T32	0	4	0	0
T34	0	4	0	0
T49	0	2	0	0
T154	0	3	0	0
T155	0	4	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2226	0	0
T1	8172	126	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	47	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	77	0	0
T29	0	73	0	0
T32	0	166	0	0
T34	0	54	0	0
T49	0	15	0	0
T154	0	158	0	0
T155	0	52	0	0
T180	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220029	0	0
T1	8172	6964	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2509	0	0
T1	8172	222	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	45	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	42	0	0
T29	0	42	0	0
T32	0	172	0	0
T34	0	117	0	0
T49	0	28	0	0
T154	0	47	0	0
T155	0	123	0	0
T180	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	40	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T49	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7202655	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7204867	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	41	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T49	0	1	0	0
T154	0	2	0	0
T155	0	2	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	40	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T49	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T180	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	40	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T49	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	40	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T32	0	2	0	0
T34	0	2	0	0
T49	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2448	0	0
T1	8172	219	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	43	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	41	0	0
T29	0	40	0	0
T32	0	169	0	0
T34	0	114	0	0
T49	0	27	0	0
T154	0	45	0	0
T155	0	120	0	0
T180	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6342	0	0
T1	8172	15	0	0
T2	13431	11	0	0
T3	1179	6	0	0
T4	2117	2	0	0
T5	23603	23	0	0
T6	12030	23	0	0
T7	136751	6	0	0
T8	0	23	0	0
T12	524	4	0	0
T13	614	0	0	0
T14	423	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	17	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T155	0	1	0	0
T161	0	1	0	0
T166	0	1	0	0
T178	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T10,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Covered	T1,T10,T18
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T18
1	-	Covered	T1,T10,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T18
DetectSt	168	Covered	T1,T10,T18
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T18
DebounceSt->IdleSt	163	Covered	T160,T194,T195
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T10,T18
IdleSt->DebounceSt	148	Covered	T1,T10,T18
StableSt->IdleSt	206	Covered	T1,T10,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T18
0	1	Covered	T1,T10,T18
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T18
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T160,T194,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T18
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	142	0	0
CntIncr_A	7861742	154436	0	0
CntNoWrap_A	7861742	7219968	0	0
DetectStDropOut_A	7861742	0	0	0
DetectedOut_A	7861742	91702	0	0
DetectedPulseOut_A	7861742	68	0	0
DisabledIdleSt_A	7861742	6852966	0	0
DisabledNoDetection_A	7861742	6855170	0	0
EnterDebounceSt_A	7861742	74	0	0
EnterDetectSt_A	7861742	68	0	0
EnterStableSt_A	7861742	68	0	0
PulseIsPulse_A	7861742	68	0	0
StayInStableSt	7861742	91597	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	142	0	0
T1	8172	4	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	6	0	0
T29	0	2	0	0
T30	0	4	0	0
T34	0	4	0	0
T35	0	2	0	0
T83	0	4	0	0
T135	0	2	0	0
T143	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	154436	0	0
T1	8172	126	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	47	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	261	0	0
T29	0	73	0	0
T30	0	110	0	0
T34	0	54	0	0
T35	0	88	0	0
T83	0	80	0	0
T135	0	62	0	0
T143	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219968	0	0
T1	8172	6964	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	91702	0	0
T1	8172	51	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	29	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	356	0	0
T29	0	180	0	0
T30	0	61	0	0
T34	0	88	0	0
T35	0	2	0	0
T83	0	159	0	0
T135	0	46	0	0
T143	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	68	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T135	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6852966	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6855170	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	74	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T135	0	1	0	0
T143	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	68	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T135	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	68	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T135	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	68	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T29	0	1	0	0
T30	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T83	0	2	0	0
T135	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	91597	0	0
T1	8172	48	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	28	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	351	0	0
T29	0	179	0	0
T30	0	58	0	0
T34	0	85	0	0
T35	0	1	0	0
T83	0	156	0	0
T135	0	44	0	0
T143	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	29	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T83	0	1	0	0
T155	0	1	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T19,T34,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T19,T34,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T19,T34,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T36
1	0	Covered	T1,T2,T4
1	1	Covered	T19,T34,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T34,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T34,T30
0	1	Covered	T19,T34,T30
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T34,T30
1	-	Covered	T19,T34,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T34,T30
DetectSt	168	Covered	T19,T34,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T19,T34,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T34,T30
DebounceSt->IdleSt	163	Covered	T167
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T19,T34,T30
IdleSt->DebounceSt	148	Covered	T19,T34,T30
StableSt->IdleSt	206	Covered	T19,T34,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T34,T30
0	1	Covered	T19,T34,T30
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T34,T30
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T34,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T34,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T167
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T34,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T19,T34,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T34,T30
StableSt	-	-	-	-	-	-	0	Covered	T19,T34,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	59	0	0
CntIncr_A	7861742	44650	0	0
CntNoWrap_A	7861742	7220051	0	0
DetectStDropOut_A	7861742	0	0	0
DetectedOut_A	7861742	6551	0	0
DetectedPulseOut_A	7861742	29	0	0
DisabledIdleSt_A	7861742	6984266	0	0
DisabledNoDetection_A	7861742	6986481	0	0
EnterDebounceSt_A	7861742	30	0	0
EnterDetectSt_A	7861742	29	0	0
EnterStableSt_A	7861742	29	0	0
PulseIsPulse_A	7861742	29	0	0
StayInStableSt	7861742	6512	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6006	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	59	0	0
T19	3300	4	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	2	0	0
T34	0	2	0	0
T49	0	2	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	4	0	0
T156	0	4	0	0
T159	0	2	0	0
T160	0	4	0	0
T194	0	2	0	0
T197	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	44650	0	0
T19	3300	132	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	55	0	0
T34	0	27	0	0
T49	0	15	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	87	0	0
T156	0	136	0	0
T159	0	79	0	0
T160	0	43249	0	0
T194	0	23	0	0
T197	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220051	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6551	0	0
T19	3300	60	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	337	0	0
T34	0	118	0	0
T49	0	29	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	167	0	0
T156	0	43	0	0
T159	0	72	0	0
T160	0	4431	0	0
T194	0	41	0	0
T197	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	29	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T49	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T159	0	1	0	0
T160	0	2	0	0
T194	0	1	0	0
T197	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6984266	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6986481	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	30	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T49	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T159	0	1	0	0
T160	0	2	0	0
T194	0	1	0	0
T197	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	29	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T49	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T159	0	1	0	0
T160	0	2	0	0
T194	0	1	0	0
T197	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	29	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T49	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T159	0	1	0	0
T160	0	2	0	0
T194	0	1	0	0
T197	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	29	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T49	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	2	0	0
T156	0	2	0	0
T159	0	1	0	0
T160	0	2	0	0
T194	0	1	0	0
T197	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6512	0	0
T19	3300	58	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	336	0	0
T34	0	117	0	0
T49	0	28	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	164	0	0
T156	0	40	0	0
T159	0	71	0	0
T160	0	4428	0	0
T194	0	40	0	0
T197	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6006	0	0
T1	8172	14	0	0
T2	13431	8	0	0
T3	1179	0	0	0
T4	2117	5	0	0
T5	23603	26	0	0
T6	12030	25	0	0
T7	136751	1	0	0
T8	0	18	0	0
T12	524	4	0	0
T13	614	0	0	0
T14	423	2	0	0
T46	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	17	0	0
T19	3300	2	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0
T198	0	1	0	0