Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T35,T19,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T35,T19,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T35,T19,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T19,T36
1	0	Covered	T1,T2,T4
1	1	Covered	T35,T19,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T19,T36
0	1	Covered	T37,T82,T199
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T36,T112
0	1	Covered	T35,T19,T32
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T36,T112
1	-	Covered	T35,T19,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T19,T36
DetectSt	168	Covered	T35,T19,T36
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T35,T19,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T19,T36
DebounceSt->IdleSt	163	Covered	T200,T181,T160
DetectSt->IdleSt	186	Covered	T37,T82,T199
DetectSt->StableSt	191	Covered	T35,T19,T36
IdleSt->DebounceSt	148	Covered	T35,T19,T36
StableSt->IdleSt	206	Covered	T35,T19,T112

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T19,T36
0	1	Covered	T35,T19,T36
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T19,T36
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T19,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T19,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T200,T181,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T19,T36
DetectSt	-	-	-	-	1	-	-	Covered	T37,T82,T199
DetectSt	-	-	-	-	0	1	-	Covered	T35,T19,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T19,T32
StableSt	-	-	-	-	-	-	0	Covered	T19,T36,T112
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	114	0	0
CntIncr_A	7861742	153843	0	0
CntNoWrap_A	7861742	7219996	0	0
DetectStDropOut_A	7861742	4	0	0
DetectedOut_A	7861742	4042	0	0
DetectedPulseOut_A	7861742	51	0	0
DisabledIdleSt_A	7861742	6855612	0	0
DisabledNoDetection_A	7861742	6857827	0	0
EnterDebounceSt_A	7861742	59	0	0
EnterDetectSt_A	7861742	55	0	0
EnterStableSt_A	7861742	51	0	0
PulseIsPulse_A	7861742	51	0	0
StayInStableSt	7861742	3970	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	114	0	0
T19	0	4	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	630	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T82	0	2	0	0
T112	0	2	0	0
T163	0	4	0	0
T201	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	153843	0	0
T19	0	132	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	83	0	0
T33	0	85	0	0
T35	630	88	0	0
T36	0	43	0	0
T37	0	142	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T82	0	24	0	0
T112	0	71	0	0
T163	0	68	0	0
T201	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219996	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	4	0	0
T37	779	2	0	0
T43	698	0	0	0
T44	9198	0	0	0
T53	2236	0	0	0
T54	1086	0	0	0
T82	0	1	0	0
T90	5068	0	0	0
T199	0	1	0	0
T202	428	0	0	0
T203	422	0	0	0
T204	402	0	0	0
T205	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	4042	0	0
T19	0	162	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	521	0	0
T33	0	67	0	0
T35	630	1	0	0
T36	0	42	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T112	0	134	0	0
T144	0	5	0	0
T163	0	88	0	0
T201	0	80	0	0
T206	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	630	1	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T112	0	1	0	0
T144	0	1	0	0
T163	0	2	0	0
T201	0	2	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6855612	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6857827	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	59	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	630	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T82	0	1	0	0
T112	0	1	0	0
T163	0	2	0	0
T201	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	55	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	630	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T82	0	1	0	0
T112	0	1	0	0
T163	0	2	0	0
T201	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	630	1	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T112	0	1	0	0
T144	0	1	0	0
T163	0	2	0	0
T201	0	2	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	630	1	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T112	0	1	0	0
T144	0	1	0	0
T163	0	2	0	0
T201	0	2	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3970	0	0
T19	3300	159	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T32	0	520	0	0
T33	0	66	0	0
T36	0	40	0	0
T49	0	28	0	0
T75	28571	0	0	0
T112	0	132	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T144	0	4	0	0
T163	0	85	0	0
T201	0	77	0	0
T206	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	28	0	0
T19	0	1	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	630	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T144	0	1	0	0
T159	0	2	0	0
T163	0	1	0	0
T165	0	1	0	0
T201	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T31,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T31,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T31,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T32
1	0	Covered	T1,T2,T4
1	1	Covered	T31,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T31,T30,T83
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T33
1	-	Covered	T31,T30,T83

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T32,T33
DetectSt	168	Covered	T31,T32,T33
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T31,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T33
DebounceSt->IdleSt	163	Covered	T163,T175,T207
DetectSt->IdleSt	186	Covered	T101
DetectSt->StableSt	191	Covered	T31,T32,T33
IdleSt->DebounceSt	148	Covered	T31,T32,T33
StableSt->IdleSt	206	Covered	T31,T30,T83

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T32,T33
0	1	Covered	T31,T32,T33
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T175,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	1	-	-	Covered	T101
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T30,T83
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	77	0	0
CntIncr_A	7861742	2203	0	0
CntNoWrap_A	7861742	7220033	0	0
DetectStDropOut_A	7861742	1	0	0
DetectedOut_A	7861742	3765	0	0
DetectedPulseOut_A	7861742	36	0	0
DisabledIdleSt_A	7861742	7202287	0	0
DisabledNoDetection_A	7861742	7204498	0	0
EnterDebounceSt_A	7861742	40	0	0
EnterDetectSt_A	7861742	37	0	0
EnterStableSt_A	7861742	36	0	0
PulseIsPulse_A	7861742	36	0	0
StayInStableSt	7861742	3705	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6095	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	77	0	0
T30	0	4	0	0
T31	821	2	0	0
T32	1145	2	0	0
T33	693	2	0	0
T83	0	4	0	0
T116	0	2	0	0
T143	0	2	0	0
T163	635	1	0	0
T182	0	2	0	0
T206	0	2	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2203	0	0
T30	0	110	0	0
T31	821	44	0	0
T32	1145	83	0	0
T33	693	85	0	0
T83	0	140	0	0
T116	0	77	0	0
T143	0	25	0	0
T163	635	34	0	0
T182	0	46	0	0
T206	0	29	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220033	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1	0	0
T50	7935	0	0	0
T101	29301	1	0	0
T214	402	0	0	0
T215	497	0	0	0
T216	502	0	0	0
T217	655	0	0	0
T218	912	0	0	0
T219	426	0	0	0
T220	1466	0	0	0
T221	686	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3765	0	0
T30	0	85	0	0
T31	821	213	0	0
T32	1145	48	0	0
T33	693	45	0	0
T49	0	28	0	0
T83	0	230	0	0
T116	0	37	0	0
T143	0	42	0	0
T163	635	0	0	0
T182	0	41	0	0
T206	0	45	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T30	0	2	0	0
T31	821	1	0	0
T32	1145	1	0	0
T33	693	1	0	0
T49	0	1	0	0
T83	0	2	0	0
T116	0	1	0	0
T143	0	1	0	0
T163	635	0	0	0
T182	0	1	0	0
T206	0	1	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7202287	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7204498	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	40	0	0
T30	0	2	0	0
T31	821	1	0	0
T32	1145	1	0	0
T33	693	1	0	0
T83	0	2	0	0
T116	0	1	0	0
T143	0	1	0	0
T163	635	1	0	0
T182	0	1	0	0
T206	0	1	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	37	0	0
T30	0	2	0	0
T31	821	1	0	0
T32	1145	1	0	0
T33	693	1	0	0
T49	0	1	0	0
T83	0	2	0	0
T116	0	1	0	0
T143	0	1	0	0
T163	635	0	0	0
T182	0	1	0	0
T206	0	1	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T30	0	2	0	0
T31	821	1	0	0
T32	1145	1	0	0
T33	693	1	0	0
T49	0	1	0	0
T83	0	2	0	0
T116	0	1	0	0
T143	0	1	0	0
T163	635	0	0	0
T182	0	1	0	0
T206	0	1	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T30	0	2	0	0
T31	821	1	0	0
T32	1145	1	0	0
T33	693	1	0	0
T49	0	1	0	0
T83	0	2	0	0
T116	0	1	0	0
T143	0	1	0	0
T163	635	0	0	0
T182	0	1	0	0
T206	0	1	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	3705	0	0
T30	0	82	0	0
T31	821	212	0	0
T32	1145	46	0	0
T33	693	43	0	0
T49	0	27	0	0
T83	0	227	0	0
T116	0	35	0	0
T143	0	40	0	0
T163	635	0	0	0
T182	0	39	0	0
T206	0	43	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6095	0	0
T1	8172	6	0	0
T2	13431	16	0	0
T3	1179	0	0	0
T4	2117	4	0	0
T5	23603	36	0	0
T6	12030	29	0	0
T7	136751	2	0	0
T8	0	27	0	0
T12	524	6	0	0
T13	614	0	0	0
T14	423	1	0	0
T46	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	10	0	0
T30	0	1	0	0
T31	821	1	0	0
T32	1145	0	0	0
T33	693	0	0	0
T83	0	1	0	0
T159	0	1	0	0
T162	0	1	0	0
T163	635	0	0	0
T175	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0
T207	0	1	0	0
T208	408	0	0	0
T209	422	0	0	0
T210	434	0	0	0
T211	423	0	0	0
T212	623	0	0	0
T213	395188	0	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T18,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T18,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T18,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T35
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T18,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T29
0	1	Covered	T83,T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T29
0	1	Covered	T1,T18,T29
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T29
1	-	Covered	T1,T18,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T29
DetectSt	168	Covered	T1,T18,T29
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T18,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T29
DebounceSt->IdleSt	163	Covered	T18,T29,T192
DetectSt->IdleSt	186	Covered	T83,T223
DetectSt->StableSt	191	Covered	T1,T18,T29
IdleSt->DebounceSt	148	Covered	T1,T18,T29
StableSt->IdleSt	206	Covered	T1,T18,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T18,T29
0	1	Covered	T1,T18,T29
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T29
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T29,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T29
DetectSt	-	-	-	-	1	-	-	Covered	T83,T223
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T29
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	140	0	0
CntIncr_A	7861742	154102	0	0
CntNoWrap_A	7861742	7219970	0	0
DetectStDropOut_A	7861742	2	0	0
DetectedOut_A	7861742	193904	0	0
DetectedPulseOut_A	7861742	64	0	0
DisabledIdleSt_A	7861742	6855081	0	0
DisabledNoDetection_A	7861742	6857291	0	0
EnterDebounceSt_A	7861742	74	0	0
EnterDetectSt_A	7861742	66	0	0
EnterStableSt_A	7861742	64	0	0
PulseIsPulse_A	7861742	64	0	0
StayInStableSt	7861742	193812	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	140	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T32	0	4	0	0
T44	0	2	0	0
T82	0	2	0	0
T143	0	2	0	0
T163	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	154102	0	0
T1	8172	63	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	169	0	0
T29	0	146	0	0
T30	0	110	0	0
T31	0	88	0	0
T32	0	166	0	0
T44	0	14	0	0
T82	0	24	0	0
T143	0	25	0	0
T163	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219970	0	0
T1	8172	6966	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2	0	0
T83	2538	1	0	0
T116	5455	0	0	0
T223	0	1	0	0
T224	5067	0	0	0
T225	402	0	0	0
T226	503	0	0	0
T227	22341	0	0	0
T228	525	0	0	0
T229	1926	0	0	0
T230	504	0	0	0
T231	29338	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	193904	0	0
T1	8172	115	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	361	0	0
T29	0	178	0	0
T30	0	160	0	0
T31	0	235	0	0
T32	0	227	0	0
T44	0	58	0	0
T82	0	66	0	0
T143	0	64	0	0
T163	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	64	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T143	0	1	0	0
T163	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6855081	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6857291	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	74	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T143	0	1	0	0
T163	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	66	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T143	0	1	0	0
T163	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	64	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T143	0	1	0	0
T163	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	64	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T82	0	1	0	0
T143	0	1	0	0
T163	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	193812	0	0
T1	8172	114	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	360	0	0
T29	0	177	0	0
T30	0	157	0	0
T31	0	232	0	0
T32	0	225	0	0
T44	0	56	0	0
T82	0	64	0	0
T143	0	62	0	0
T163	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	34	0	0
T1	8172	1	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T154	0	2	0	0
T163	0	1	0	0
T201	0	2	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T18,T19,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T18,T19,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T18,T19,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T82
1	0	Covered	T1,T2,T4
1	1	Covered	T18,T19,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T30
0	1	Covered	T232
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T30
0	1	Covered	T19,T30,T201
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T19,T30
1	-	Covered	T19,T30,T201

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T19,T30
DetectSt	168	Covered	T18,T19,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T18,T19,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T19,T30
DebounceSt->IdleSt	163	Covered	T201,T164
DetectSt->IdleSt	186	Covered	T232
DetectSt->StableSt	191	Covered	T18,T19,T30
IdleSt->DebounceSt	148	Covered	T18,T19,T30
StableSt->IdleSt	206	Covered	T18,T19,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T19,T30
0	1	Covered	T18,T19,T30
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T30
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T19,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T19,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T201,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T19,T30
DetectSt	-	-	-	-	1	-	-	Covered	T232
DetectSt	-	-	-	-	0	1	-	Covered	T18,T19,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T30,T201
StableSt	-	-	-	-	-	-	0	Covered	T18,T19,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	76	0	0
CntIncr_A	7861742	45128	0	0
CntNoWrap_A	7861742	7220034	0	0
DetectStDropOut_A	7861742	1	0	0
DetectedOut_A	7861742	2437	0	0
DetectedPulseOut_A	7861742	36	0	0
DisabledIdleSt_A	7861742	6983086	0	0
DisabledNoDetection_A	7861742	6985295	0	0
EnterDebounceSt_A	7861742	39	0	0
EnterDetectSt_A	7861742	37	0	0
EnterStableSt_A	7861742	36	0	0
PulseIsPulse_A	7861742	36	0	0
StayInStableSt	7861742	2382	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6042	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	76	0	0
T18	23345	2	0	0
T19	0	4	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	2	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	2	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	8	0	0
T154	0	4	0	0
T156	0	2	0	0
T201	0	3	0	0
T206	0	2	0	0
T233	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	45128	0	0
T18	23345	92	0	0
T19	0	132	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	55	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	15	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	250	0	0
T154	0	158	0	0
T156	0	69	0	0
T201	0	80	0	0
T206	0	29	0	0
T233	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220034	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1	0	0
T129	2261	0	0	0
T232	844	1	0	0
T234	437	0	0	0
T235	145528	0	0	0
T236	502	0	0	0
T237	2505	0	0	0
T238	422	0	0	0
T239	446	0	0	0
T240	16715	0	0	0
T241	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2437	0	0
T18	23345	195	0	0
T19	0	138	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	237	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	30	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	164	0	0
T154	0	90	0	0
T156	0	39	0	0
T201	0	16	0	0
T206	0	45	0	0
T233	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	1	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	4	0	0
T154	0	2	0	0
T156	0	1	0	0
T201	0	1	0	0
T206	0	1	0	0
T233	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6983086	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6985295	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	39	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	1	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	4	0	0
T154	0	2	0	0
T156	0	1	0	0
T201	0	2	0	0
T206	0	1	0	0
T233	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	37	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	1	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	4	0	0
T154	0	2	0	0
T156	0	1	0	0
T201	0	1	0	0
T206	0	1	0	0
T233	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	1	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	4	0	0
T154	0	2	0	0
T156	0	1	0	0
T201	0	1	0	0
T206	0	1	0	0
T233	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	1	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	4	0	0
T154	0	2	0	0
T156	0	1	0	0
T201	0	1	0	0
T206	0	1	0	0
T233	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2382	0	0
T18	23345	193	0	0
T19	0	135	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T30	0	236	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	29	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	158	0	0
T154	0	87	0	0
T156	0	37	0	0
T201	0	15	0	0
T206	0	43	0	0
T233	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6042	0	0
T1	8172	11	0	0
T2	13431	13	0	0
T3	1179	0	0	0
T4	2117	5	0	0
T5	23603	20	0	0
T6	12030	29	0	0
T7	136751	2	0	0
T8	0	20	0	0
T12	524	5	0	0
T13	614	0	0	0
T14	423	2	0	0
T46	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	15	0	0
T19	3300	1	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T30	0	1	0	0
T75	28571	0	0	0
T83	0	2	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T154	0	1	0	0
T160	0	1	0	0
T164	0	1	0	0
T167	0	1	0	0
T194	0	1	0	0
T201	0	1	0	0
T242	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T10,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T10,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T18
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T10,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Covered	T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T18
0	1	Covered	T1,T18,T19
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T18
1	-	Covered	T1,T18,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T18
DetectSt	168	Covered	T1,T10,T18
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T10,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T18
DebounceSt->IdleSt	163	Covered	T36,T31,T32
DetectSt->IdleSt	186	Covered	T83
DetectSt->StableSt	191	Covered	T1,T10,T18
IdleSt->DebounceSt	148	Covered	T1,T10,T18
StableSt->IdleSt	206	Covered	T1,T10,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T18
0	1	Covered	T1,T10,T18
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T18
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T31,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	1	-	-	Covered	T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	128	0	0
CntIncr_A	7861742	153811	0	0
CntNoWrap_A	7861742	7219982	0	0
DetectStDropOut_A	7861742	1	0	0
DetectedOut_A	7861742	69205	0	0
DetectedPulseOut_A	7861742	60	0	0
DisabledIdleSt_A	7861742	6855816	0	0
DisabledNoDetection_A	7861742	6858028	0	0
EnterDebounceSt_A	7861742	67	0	0
EnterDetectSt_A	7861742	61	0	0
EnterStableSt_A	7861742	60	0	0
PulseIsPulse_A	7861742	60	0	0
StayInStableSt	7861742	69118	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	128	0	0
T1	8172	6	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	4	0	0
T19	0	4	0	0
T31	0	5	0	0
T32	0	1	0	0
T36	0	1	0	0
T112	0	2	0	0
T163	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	153811	0	0
T1	8172	189	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	47	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	184	0	0
T19	0	132	0	0
T31	0	132	0	0
T32	0	83	0	0
T36	0	43	0	0
T112	0	71	0	0
T163	0	34	0	0
T182	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219982	0	0
T1	8172	6962	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1	0	0
T83	2538	1	0	0
T116	5455	0	0	0
T224	5067	0	0	0
T225	402	0	0	0
T226	503	0	0	0
T227	22341	0	0	0
T228	525	0	0	0
T229	1926	0	0	0
T230	504	0	0	0
T231	29338	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	69205	0	0
T1	8172	116	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	45	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	102	0	0
T19	0	169	0	0
T31	0	65	0	0
T83	0	52	0	0
T112	0	41	0	0
T163	0	156	0	0
T182	0	40	0	0
T201	0	236	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	60	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T31	0	2	0	0
T83	0	1	0	0
T112	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6855816	0	0
T1	8172	6446	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6858028	0	0
T1	8172	6448	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	67	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T31	0	3	0	0
T32	0	1	0	0
T36	0	1	0	0
T112	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	61	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T31	0	2	0	0
T83	0	2	0	0
T112	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	60	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T31	0	2	0	0
T83	0	1	0	0
T112	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	60	0	0
T1	8172	3	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T31	0	2	0	0
T83	0	1	0	0
T112	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	69118	0	0
T1	8172	112	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	43	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	100	0	0
T19	0	167	0	0
T31	0	62	0	0
T83	0	51	0	0
T112	0	39	0	0
T163	0	154	0	0
T182	0	38	0	0
T201	0	235	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	31	0	0
T1	8172	2	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T31	0	1	0	0
T83	0	1	0	0
T97	0	1	0	0
T116	0	1	0	0
T144	0	1	0	0
T201	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T18,T29,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T18,T29,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T18,T29,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T18,T29
1	0	Covered	T1,T2,T4
1	1	Covered	T18,T29,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T29,T19
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T29,T19
0	1	Covered	T19,T34,T168
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T29,T19
1	-	Covered	T19,T34,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T29,T19
DetectSt	168	Covered	T18,T29,T19
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T18,T29,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T29,T19
DebounceSt->IdleSt	163	Covered	T18,T160
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T18,T29,T19
IdleSt->DebounceSt	148	Covered	T18,T29,T19
StableSt->IdleSt	206	Covered	T18,T19,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T29,T19
0	1	Covered	T18,T29,T19
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T29,T19
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T29,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T29,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T29,T19
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T18,T29,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T34,T49
StableSt	-	-	-	-	-	-	0	Covered	T18,T29,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	74	0	0
CntIncr_A	7861742	45149	0	0
CntNoWrap_A	7861742	7220036	0	0
DetectStDropOut_A	7861742	1	0	0
DetectedOut_A	7861742	2681	0	0
DetectedPulseOut_A	7861742	35	0	0
DisabledIdleSt_A	7861742	6852597	0	0
DisabledNoDetection_A	7861742	6854802	0	0
EnterDebounceSt_A	7861742	38	0	0
EnterDetectSt_A	7861742	36	0	0
EnterStableSt_A	7861742	35	0	0
PulseIsPulse_A	7861742	35	0	0
StayInStableSt	7861742	2621	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7861742	6663	0	0
gen_low_level_sva.LowLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	74	0	0
T18	23345	3	0	0
T19	0	4	0	0
T26	14698	0	0	0
T29	1012	2	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	630	0	0	0
T36	0	2	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	2	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	4	0	0
T116	0	2	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	45149	0	0
T18	23345	184	0	0
T19	0	132	0	0
T26	14698	0	0	0
T29	1012	73	0	0
T33	0	85	0	0
T34	0	54	0	0
T35	630	0	0	0
T36	0	43	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	15	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	110	0	0
T116	0	77	0	0
T154	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7220036	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1	0	0
T154	964	1	0	0
T158	1704	0	0	0
T180	503	0	0	0
T200	601	0	0	0
T233	9415	0	0	0
T243	29405	0	0	0
T244	501	0	0	0
T245	522	0	0	0
T246	418	0	0	0
T247	880	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2681	0	0
T18	23345	40	0	0
T19	0	53	0	0
T26	14698	0	0	0
T29	1012	41	0	0
T33	0	45	0	0
T34	0	94	0	0
T35	630	0	0	0
T36	0	41	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	28	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	367	0	0
T116	0	37	0	0
T200	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	35	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	630	0	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	2	0	0
T116	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6852597	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6854802	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	38	0	0
T18	23345	2	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	630	0	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	2	0	0
T116	0	1	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	36	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	630	0	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	2	0	0
T116	0	1	0	0
T154	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	35	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	630	0	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	2	0	0
T116	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	35	0	0
T18	23345	1	0	0
T19	0	2	0	0
T26	14698	0	0	0
T29	1012	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	630	0	0	0
T36	0	1	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	2	0	0
T116	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2621	0	0
T18	23345	38	0	0
T19	0	50	0	0
T26	14698	0	0	0
T29	1012	39	0	0
T33	0	43	0	0
T34	0	91	0	0
T35	630	0	0	0
T36	0	39	0	0
T40	648	0	0	0
T48	1001	0	0	0
T49	0	27	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T83	0	363	0	0
T116	0	35	0	0
T200	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6663	0	0
T1	8172	13	0	0
T2	13431	12	0	0
T3	1179	6	0	0
T4	2117	3	0	0
T5	23603	30	0	0
T6	12030	28	0	0
T7	136751	6	0	0
T12	524	4	0	0
T13	614	3	0	0
T14	423	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	8	0	0
T19	3300	1	0	0
T20	128362	0	0	0
T28	53166	0	0	0
T34	0	1	0	0
T75	28571	0	0	0
T121	11726	0	0	0
T122	421	0	0	0
T123	8826	0	0	0
T124	8224	0	0	0
T125	908	0	0	0
T126	651	0	0	0
T161	0	1	0	0
T162	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0
T207	0	1	0	0
T232	0	1	0	0