Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8
1	1	Covered	T5,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T8,T70
1	0	Covered	T5,T8,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T38
0	1	Covered	T6,T9,T38
1	0	Covered	T64,T49,T248

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T38
1	-	Covered	T6,T9,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T8
DetectSt	168	Covered	T5,T6,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T8
DebounceSt->IdleSt	163	Covered	T49,T249,T250
DetectSt->IdleSt	186	Covered	T5,T8,T70
DetectSt->StableSt	191	Covered	T6,T9,T38
IdleSt->DebounceSt	148	Covered	T5,T6,T8
StableSt->IdleSt	206	Covered	T6,T9,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T249,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T5,T8,T70
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T38
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T8
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T38
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	2782	0	0
CntIncr_A	7861742	86137	0	0
CntNoWrap_A	7861742	7217328	0	0
DetectStDropOut_A	7861742	390	0	0
DetectedOut_A	7861742	57834	0	0
DetectedPulseOut_A	7861742	757	0	0
DisabledIdleSt_A	7861742	6822802	0	0
DisabledNoDetection_A	7861742	6824885	0	0
EnterDebounceSt_A	7861742	1406	0	0
EnterDetectSt_A	7861742	1376	0	0
EnterStableSt_A	7861742	757	0	0
PulseIsPulse_A	7861742	757	0	0
StayInStableSt	7861742	56983	0	0
gen_high_event_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	659	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2782	0	0
T5	23603	56	0	0
T6	12030	44	0	0
T7	136751	0	0	0
T8	7275	38	0	0
T9	46086	40	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	18	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	46	0	0
T69	0	2	0	0
T70	0	12	0	0
T71	0	40	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	86137	0	0
T5	23603	1517	0	0
T6	12030	946	0	0
T7	136751	0	0	0
T8	7275	1239	0	0
T9	46086	1400	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	438	0	0
T39	0	567	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	1771	0	0
T69	0	21	0	0
T70	0	396	0	0
T71	0	1361	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7217328	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23130	0	0
T6	12030	11581	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	390	0	0
T5	23603	23	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T8	7275	15	0	0
T9	46086	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T64	0	9	0	0
T70	0	1	0	0
T71	0	11	0	0
T90	0	12	0	0
T91	0	18	0	0
T92	0	24	0	0
T95	0	9	0	0
T224	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	57834	0	0
T6	12030	2158	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	3032	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	264	0	0
T39	0	2209	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	530	0	0
T64	0	2	0	0
T69	0	46	0	0
T88	404	0	0	0
T121	0	805	0	0
T123	0	1562	0	0
T124	0	125	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	757	0	0
T6	12030	22	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	6	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	23	0	0
T64	0	2	0	0
T69	0	1	0	0
T88	404	0	0	0
T121	0	15	0	0
T123	0	22	0	0
T124	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6822802	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	20251	0	0
T6	12030	6222	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6824885	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	20259	0	0
T6	12030	6223	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1406	0	0
T5	23603	28	0	0
T6	12030	22	0	0
T7	136751	0	0	0
T8	7275	19	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	6	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	23	0	0
T69	0	1	0	0
T70	0	6	0	0
T71	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1376	0	0
T5	23603	28	0	0
T6	12030	22	0	0
T7	136751	0	0	0
T8	7275	19	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	6	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	23	0	0
T69	0	1	0	0
T70	0	6	0	0
T71	0	20	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	757	0	0
T6	12030	22	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	6	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	23	0	0
T64	0	2	0	0
T69	0	1	0	0
T88	404	0	0	0
T121	0	15	0	0
T123	0	22	0	0
T124	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	757	0	0
T6	12030	22	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	6	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	23	0	0
T64	0	2	0	0
T69	0	1	0	0
T88	404	0	0	0
T121	0	15	0	0
T123	0	22	0	0
T124	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	56983	0	0
T6	12030	2135	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	3000	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	258	0	0
T39	0	2197	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	507	0	0
T69	0	44	0	0
T88	404	0	0	0
T111	0	1310	0	0
T121	0	788	0	0
T123	0	1540	0	0
T124	0	120	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	659	0	0
T6	12030	21	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	8	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	6	0	0
T39	0	6	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	23	0	0
T88	404	0	0	0
T111	0	6	0	0
T121	0	13	0	0
T123	0	22	0	0
T124	0	5	0	0
T251	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T9,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T27
0	1	Covered	T18,T75,T76
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T27
0	1	Covered	T1,T27,T39
1	0	Covered	T49,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T27
1	-	Covered	T1,T27,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T4,T9
DetectSt	168	Covered	T1,T9,T27
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T9,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T27
DebounceSt->IdleSt	163	Covered	T4,T69,T18
DetectSt->IdleSt	186	Covered	T18,T75,T76
DetectSt->StableSt	191	Covered	T1,T9,T27
IdleSt->DebounceSt	148	Covered	T1,T4,T9
StableSt->IdleSt	206	Covered	T1,T9,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T4,T9
0	1	Covered	T1,T4,T9
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T27
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T69,T18
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T75,T76
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T27
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T27,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	857	0	0
CntIncr_A	7861742	42615	0	0
CntNoWrap_A	7861742	7219253	0	0
DetectStDropOut_A	7861742	64	0	0
DetectedOut_A	7861742	12101	0	0
DetectedPulseOut_A	7861742	317	0	0
DisabledIdleSt_A	7861742	6859786	0	0
DisabledNoDetection_A	7861742	6861362	0	0
EnterDebounceSt_A	7861742	473	0	0
EnterDetectSt_A	7861742	386	0	0
EnterStableSt_A	7861742	317	0	0
PulseIsPulse_A	7861742	317	0	0
StayInStableSt	7861742	11747	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	857	0	0
T1	8172	10	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	2	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	18	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	11	0	0
T19	0	1	0	0
T20	0	2	0	0
T26	0	7	0	0
T27	0	4	0	0
T39	0	6	0	0
T69	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	42615	0	0
T1	8172	260	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	40	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	720	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	384	0	0
T19	0	20	0	0
T20	0	25	0	0
T26	0	323	0	0
T27	0	238	0	0
T39	0	216	0	0
T69	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219253	0	0
T1	8172	6958	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	111	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	64	0	0
T18	23345	5	0	0
T26	14698	0	0	0
T29	1012	0	0	0
T35	630	0	0	0
T40	648	0	0	0
T48	1001	0	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T75	0	1	0	0
T76	0	4	0	0
T93	0	2	0	0
T94	0	3	0	0
T96	0	8	0	0
T97	0	9	0	0
T98	0	9	0	0
T100	0	3	0	0
T101	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	12101	0	0
T1	8172	179	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	555	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T20	0	3	0	0
T26	0	213	0	0
T27	0	87	0	0
T28	0	680	0	0
T39	0	156	0	0
T87	0	4	0	0
T110	0	260	0	0
T111	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	317	0	0
T1	8172	5	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	9	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T20	0	1	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	15	0	0
T39	0	3	0	0
T87	0	1	0	0
T110	0	4	0	0
T111	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6859786	0	0
T1	8172	4556	0	0
T2	13431	10073	0	0
T3	1179	778	0	0
T4	2117	39	0	0
T5	23603	23186	0	0
T6	12030	9468	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6861362	0	0
T1	8172	4557	0	0
T2	13431	10073	0	0
T3	1179	779	0	0
T4	2117	41	0	0
T5	23603	23195	0	0
T6	12030	9470	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	473	0	0
T1	8172	5	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	2	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	9	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	6	0	0
T19	0	1	0	0
T20	0	1	0	0
T26	0	4	0	0
T27	0	2	0	0
T39	0	3	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	386	0	0
T1	8172	5	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	9	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	5	0	0
T20	0	1	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	15	0	0
T39	0	3	0	0
T75	0	1	0	0
T110	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	317	0	0
T1	8172	5	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	9	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T20	0	1	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	15	0	0
T39	0	3	0	0
T87	0	1	0	0
T110	0	4	0	0
T111	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	317	0	0
T1	8172	5	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	9	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T20	0	1	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	15	0	0
T39	0	3	0	0
T87	0	1	0	0
T110	0	4	0	0
T111	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	11747	0	0
T1	8172	174	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	537	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T20	0	2	0	0
T26	0	210	0	0
T27	0	85	0	0
T28	0	665	0	0
T39	0	153	0	0
T87	0	3	0	0
T110	0	256	0	0
T111	0	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	276	0	0
T1	8172	5	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T20	0	1	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	15	0	0
T39	0	3	0	0
T87	0	1	0	0
T110	0	4	0	0
T111	0	2	0	0
T112	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8
1	1	Covered	T5,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T8,T71
1	0	Covered	T5,T8,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T38
0	1	Covered	T6,T9,T38
1	0	Covered	T252

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T38
1	-	Covered	T6,T9,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T8
DetectSt	168	Covered	T5,T6,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T8
DebounceSt->IdleSt	163	Covered	T49,T249,T250
DetectSt->IdleSt	186	Covered	T5,T8,T71
DetectSt->StableSt	191	Covered	T6,T9,T38
IdleSt->DebounceSt	148	Covered	T5,T6,T8
StableSt->IdleSt	206	Covered	T6,T9,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T249,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T5,T8,T71
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T38
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T8
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T38
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	2871	0	0
CntIncr_A	7861742	91343	0	0
CntNoWrap_A	7861742	7217239	0	0
DetectStDropOut_A	7861742	424	0	0
DetectedOut_A	7861742	58946	0	0
DetectedPulseOut_A	7861742	740	0	0
DisabledIdleSt_A	7861742	6820692	0	0
DisabledNoDetection_A	7861742	6822780	0	0
EnterDebounceSt_A	7861742	1449	0	0
EnterDetectSt_A	7861742	1423	0	0
EnterStableSt_A	7861742	740	0	0
PulseIsPulse_A	7861742	740	0	0
StayInStableSt	7861742	58117	0	0
gen_high_event_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	649	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2871	0	0
T5	23603	56	0	0
T6	12030	8	0	0
T7	136751	0	0	0
T8	7275	20	0	0
T9	46086	32	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	24	0	0
T39	0	10	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	30	0	0
T64	0	52	0	0
T70	0	28	0	0
T71	0	68	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	91343	0	0
T5	23603	1517	0	0
T6	12030	232	0	0
T7	136751	0	0	0
T8	7275	653	0	0
T9	46086	896	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	1068	0	0
T39	0	390	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	1320	0	0
T64	0	936	0	0
T70	0	784	0	0
T71	0	2330	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7217239	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23130	0	0
T6	12030	11617	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	424	0	0
T5	23603	23	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T8	7275	6	0	0
T9	46086	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T49	0	1	0	0
T71	0	18	0	0
T90	0	14	0	0
T91	0	10	0	0
T92	0	24	0	0
T95	0	19	0	0
T107	0	8	0	0
T224	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	58946	0	0
T6	12030	72	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	2097	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	341	0	0
T39	0	348	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	169	0	0
T64	0	1801	0	0
T70	0	1672	0	0
T88	404	0	0	0
T121	0	1804	0	0
T123	0	1280	0	0
T124	0	469	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	740	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	16	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	5	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	15	0	0
T64	0	26	0	0
T70	0	14	0	0
T88	404	0	0	0
T121	0	28	0	0
T123	0	27	0	0
T124	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6820692	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	20251	0	0
T6	12030	7702	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6822780	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	20259	0	0
T6	12030	7704	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1449	0	0
T5	23603	28	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	16	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	5	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	15	0	0
T64	0	26	0	0
T70	0	14	0	0
T71	0	34	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1423	0	0
T5	23603	28	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	16	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	5	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	15	0	0
T64	0	26	0	0
T70	0	14	0	0
T71	0	34	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	740	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	16	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	5	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	15	0	0
T64	0	26	0	0
T70	0	14	0	0
T88	404	0	0	0
T121	0	28	0	0
T123	0	27	0	0
T124	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	740	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	16	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	5	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	15	0	0
T64	0	26	0	0
T70	0	14	0	0
T88	404	0	0	0
T121	0	28	0	0
T123	0	27	0	0
T124	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	58117	0	0
T6	12030	68	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	2076	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	329	0	0
T39	0	343	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	154	0	0
T64	0	1774	0	0
T70	0	1651	0	0
T88	404	0	0	0
T121	0	1774	0	0
T123	0	1253	0	0
T124	0	455	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	649	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	11	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	12	0	0
T39	0	5	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	15	0	0
T64	0	25	0	0
T70	0	7	0	0
T88	404	0	0	0
T121	0	26	0	0
T123	0	27	0	0
T124	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T94,T155,T253
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T2,T10,T27
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T2,T10,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T2,T27,T75
DetectSt->IdleSt	186	Covered	T94,T49,T155
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T27,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T94,T49,T155
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T27
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	782	0	0
CntIncr_A	7861742	42111	0	0
CntNoWrap_A	7861742	7219328	0	0
DetectStDropOut_A	7861742	30	0	0
DetectedOut_A	7861742	12897	0	0
DetectedPulseOut_A	7861742	335	0	0
DisabledIdleSt_A	7861742	6867627	0	0
DisabledNoDetection_A	7861742	6869283	0	0
EnterDebounceSt_A	7861742	414	0	0
EnterDetectSt_A	7861742	370	0	0
EnterStableSt_A	7861742	335	0	0
PulseIsPulse_A	7861742	335	0	0
StayInStableSt	7861742	12521	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	782	0	0
T2	13431	5	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	8	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	2	0	0
T27	0	8	0	0
T28	0	10	0	0
T64	0	2	0	0
T70	0	14	0	0
T75	0	15	0	0
T121	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	42111	0	0
T2	13431	173	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	240	0	0
T10	0	174	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	144	0	0
T27	0	518	0	0
T28	0	715	0	0
T64	0	55	0	0
T70	0	280	0	0
T75	0	1030	0	0
T121	0	163	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219328	0	0
T1	8172	6968	0	0
T2	13431	13017	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11625	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	30	0	0
T30	974	0	0	0
T57	506	0	0	0
T58	489	0	0	0
T59	491	0	0	0
T60	493	0	0	0
T94	13769	6	0	0
T96	0	2	0	0
T155	0	1	0	0
T177	0	5	0	0
T184	0	3	0	0
T253	0	4	0	0
T254	0	4	0	0
T255	0	3	0	0
T256	0	2	0	0
T257	422	0	0	0
T258	423	0	0	0
T259	522	0	0	0
T260	1348	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	12897	0	0
T2	13431	28	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	325	0	0
T10	0	59	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	11	0	0
T27	0	112	0	0
T28	0	144	0	0
T64	0	54	0	0
T70	0	507	0	0
T75	0	94	0	0
T121	0	299	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	335	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	1	0	0
T27	0	3	0	0
T28	0	5	0	0
T64	0	1	0	0
T70	0	7	0	0
T75	0	7	0	0
T121	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6867627	0	0
T1	8172	4556	0	0
T2	13431	10073	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11553	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6869283	0	0
T1	8172	4557	0	0
T2	13431	10073	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11556	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	414	0	0
T2	13431	3	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	1	0	0
T27	0	5	0	0
T28	0	5	0	0
T64	0	1	0	0
T70	0	7	0	0
T75	0	8	0	0
T121	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	370	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	1	0	0
T27	0	3	0	0
T28	0	5	0	0
T64	0	1	0	0
T70	0	7	0	0
T75	0	7	0	0
T121	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	335	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	1	0	0
T27	0	3	0	0
T28	0	5	0	0
T64	0	1	0	0
T70	0	7	0	0
T75	0	7	0	0
T121	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	335	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	1	0	0
T27	0	3	0	0
T28	0	5	0	0
T64	0	1	0	0
T70	0	7	0	0
T75	0	7	0	0
T121	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	12521	0	0
T2	13431	26	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T9	0	317	0	0
T10	0	58	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	10	0	0
T27	0	109	0	0
T28	0	139	0	0
T64	0	52	0	0
T70	0	493	0	0
T75	0	87	0	0
T121	0	295	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	292	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T26	0	1	0	0
T27	0	3	0	0
T28	0	5	0	0
T34	0	1	0	0
T75	0	7	0	0
T76	0	2	0	0
T110	0	7	0	0
T121	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T9
1	1	Covered	T5,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T64,T261
1	0	Covered	T5,T70,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T9
0	1	Covered	T6,T8,T9
1	0	Covered	T78,T248

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T9
1	-	Covered	T6,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T8
DetectSt	168	Covered	T5,T6,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T8
DebounceSt->IdleSt	163	Covered	T49,T249,T250
DetectSt->IdleSt	186	Covered	T5,T70,T64
DetectSt->StableSt	191	Covered	T6,T8,T9
IdleSt->DebounceSt	148	Covered	T5,T6,T8
StableSt->IdleSt	206	Covered	T6,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T249,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T5,T70,T64
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T8
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	2991	0	0
CntIncr_A	7861742	97793	0	0
CntNoWrap_A	7861742	7217119	0	0
DetectStDropOut_A	7861742	397	0	0
DetectedOut_A	7861742	81673	0	0
DetectedPulseOut_A	7861742	993	0	0
DisabledIdleSt_A	7861742	6799750	0	0
DisabledNoDetection_A	7861742	6801803	0	0
EnterDebounceSt_A	7861742	1514	0	0
EnterDetectSt_A	7861742	1477	0	0
EnterStableSt_A	7861742	993	0	0
PulseIsPulse_A	7861742	993	0	0
StayInStableSt	7861742	80556	0	0
gen_high_event_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	851	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2991	0	0
T5	23603	22	0	0
T6	12030	50	0	0
T7	136751	0	0	0
T8	7275	20	0	0
T9	46086	40	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	26	0	0
T39	0	18	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	24	0	0
T64	0	58	0	0
T70	0	28	0	0
T71	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	97793	0	0
T5	23603	597	0	0
T6	12030	1250	0	0
T7	136751	0	0	0
T8	7275	620	0	0
T9	46086	1620	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	910	0	0
T39	0	639	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	804	0	0
T64	0	1582	0	0
T70	0	933	0	0
T71	0	1040	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7217119	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23164	0	0
T6	12030	11575	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	397	0	0
T5	23603	6	0	0
T6	12030	0	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	0	0	0
T14	423	0	0	0
T22	715	0	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T64	0	16	0	0
T90	0	10	0	0
T91	0	10	0	0
T92	0	24	0	0
T95	0	2	0	0
T107	0	10	0	0
T111	0	8	0	0
T224	0	8	0	0
T261	0	23	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	81673	0	0
T6	12030	1075	0	0
T7	136751	0	0	0
T8	7275	1367	0	0
T9	46086	2812	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	617	0	0
T39	0	2137	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	390	0	0
T71	0	2117	0	0
T88	404	0	0	0
T121	0	1326	0	0
T123	0	652	0	0
T124	0	1397	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	993	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	13	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	12	0	0
T71	0	16	0	0
T88	404	0	0	0
T121	0	20	0	0
T123	0	7	0	0
T124	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6799750	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	20251	0	0
T6	12030	7237	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6801803	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	20259	0	0
T6	12030	7237	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1514	0	0
T5	23603	11	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	13	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	12	0	0
T64	0	29	0	0
T70	0	14	0	0
T71	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1477	0	0
T5	23603	11	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	13	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	12	0	0
T64	0	29	0	0
T70	0	14	0	0
T71	0	16	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	993	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	13	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	12	0	0
T71	0	16	0	0
T88	404	0	0	0
T121	0	20	0	0
T123	0	7	0	0
T124	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	993	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	20	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	13	0	0
T39	0	9	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	12	0	0
T71	0	16	0	0
T88	404	0	0	0
T121	0	20	0	0
T123	0	7	0	0
T124	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	80556	0	0
T6	12030	1048	0	0
T7	136751	0	0	0
T8	7275	1357	0	0
T9	46086	2780	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	604	0	0
T39	0	2125	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	378	0	0
T71	0	2096	0	0
T88	404	0	0	0
T121	0	1304	0	0
T123	0	645	0	0
T124	0	1369	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	851	0	0
T6	12030	23	0	0
T7	136751	0	0	0
T8	7275	10	0	0
T9	46086	8	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	13	0	0
T39	0	6	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	12	0	0
T71	0	11	0	0
T88	404	0	0	0
T121	0	18	0	0
T123	0	7	0	0
T124	0	28	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T76,T262,T263
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T49

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T6
1	-	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T1,T2,T6
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T6
DebounceSt->IdleSt	163	Covered	T27,T26,T75
DetectSt->IdleSt	186	Covered	T76,T262,T263
DetectSt->StableSt	191	Covered	T1,T2,T6
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T26,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T76,T262,T263
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	889	0	0
CntIncr_A	7861742	46432	0	0
CntNoWrap_A	7861742	7219221	0	0
DetectStDropOut_A	7861742	51	0	0
DetectedOut_A	7861742	16584	0	0
DetectedPulseOut_A	7861742	367	0	0
DisabledIdleSt_A	7861742	6844346	0	0
DisabledNoDetection_A	7861742	6845965	0	0
EnterDebounceSt_A	7861742	467	0	0
EnterDetectSt_A	7861742	422	0	0
EnterStableSt_A	7861742	367	0	0
PulseIsPulse_A	7861742	367	0	0
StayInStableSt	7861742	16184	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	889	0	0
T1	8172	2	0	0
T2	13431	4	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	4	0	0
T7	136751	0	0	0
T8	0	2	0	0
T9	0	14	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	6	0	0
T26	0	5	0	0
T27	0	11	0	0
T39	0	6	0	0
T71	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	46432	0	0
T1	8172	79	0	0
T2	13431	168	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	88	0	0
T7	136751	0	0	0
T8	0	67	0	0
T9	0	623	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	135	0	0
T26	0	348	0	0
T27	0	835	0	0
T39	0	267	0	0
T71	0	390	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219221	0	0
T1	8172	6966	0	0
T2	13431	13018	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	11621	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	51	0	0
T31	821	0	0	0
T32	1145	0	0	0
T72	117010	0	0	0
T73	1295	0	0	0
T76	13758	3	0	0
T92	6023	0	0	0
T96	0	11	0	0
T98	0	2	0	0
T111	10330	0	0	0
T112	14421	0	0	0
T117	0	11	0	0
T262	21243	6	0	0
T263	0	9	0	0
T264	0	1	0	0
T265	0	3	0	0
T266	0	2	0	0
T267	0	2	0	0
T268	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	16584	0	0
T1	8172	8	0	0
T2	13431	9	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	164	0	0
T7	136751	0	0	0
T8	0	56	0	0
T9	0	365	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	83	0	0
T26	0	32	0	0
T27	0	49	0	0
T39	0	105	0	0
T71	0	248	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	367	0	0
T1	8172	1	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T8	0	1	0	0
T9	0	7	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T39	0	3	0	0
T71	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6844346	0	0
T1	8172	4556	0	0
T2	13431	10073	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23186	0	0
T6	12030	10552	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6845965	0	0
T1	8172	4557	0	0
T2	13431	10073	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	10553	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	467	0	0
T1	8172	1	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T8	0	1	0	0
T9	0	7	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T26	0	3	0	0
T27	0	6	0	0
T39	0	3	0	0
T71	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	422	0	0
T1	8172	1	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T8	0	1	0	0
T9	0	7	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T39	0	3	0	0
T71	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	367	0	0
T1	8172	1	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T8	0	1	0	0
T9	0	7	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T39	0	3	0	0
T71	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	367	0	0
T1	8172	1	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T8	0	1	0	0
T9	0	7	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T39	0	3	0	0
T71	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	16184	0	0
T1	8172	7	0	0
T2	13431	7	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	162	0	0
T7	136751	0	0	0
T8	0	55	0	0
T9	0	351	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	80	0	0
T26	0	30	0	0
T27	0	44	0	0
T39	0	102	0	0
T71	0	243	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	329	0	0
T1	8172	1	0	0
T2	13431	2	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	0	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T8	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	3	0	0
T26	0	2	0	0
T27	0	5	0	0
T28	0	16	0	0
T39	0	3	0	0
T71	0	5	0	0