Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T8
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8
1	1	Covered	T5,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T8,T39,T71
1	0	Covered	T8,T39,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T9
0	1	Covered	T5,T6,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T6,T9
1	-	Covered	T5,T6,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T8
DetectSt	168	Covered	T5,T6,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T5,T6,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T8
DebounceSt->IdleSt	163	Covered	T49,T249,T250
DetectSt->IdleSt	186	Covered	T8,T39,T71
DetectSt->StableSt	191	Covered	T5,T6,T9
IdleSt->DebounceSt	148	Covered	T5,T6,T8
StableSt->IdleSt	206	Covered	T5,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T8
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T249,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T39,T71
DetectSt	-	-	-	-	0	1	-	Covered	T5,T6,T9
DetectSt	-	-	-	-	0	0	-	Covered	T5,T6,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T6,T9
StableSt	-	-	-	-	-	-	0	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	2870	0	0
CntIncr_A	7861742	93282	0	0
CntNoWrap_A	7861742	7217240	0	0
DetectStDropOut_A	7861742	421	0	0
DetectedOut_A	7861742	63951	0	0
DetectedPulseOut_A	7861742	791	0	0
DisabledIdleSt_A	7861742	6816368	0	0
DisabledNoDetection_A	7861742	6818445	0	0
EnterDebounceSt_A	7861742	1453	0	0
EnterDetectSt_A	7861742	1417	0	0
EnterStableSt_A	7861742	791	0	0
PulseIsPulse_A	7861742	791	0	0
StayInStableSt	7861742	63061	0	0
gen_high_event_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	692	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	2870	0	0
T5	23603	20	0	0
T6	12030	50	0	0
T7	136751	0	0	0
T8	7275	12	0	0
T9	46086	26	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	58	0	0
T39	0	44	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	56	0	0
T64	0	16	0	0
T70	0	28	0	0
T71	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	93282	0	0
T5	23603	430	0	0
T6	12030	1000	0	0
T7	136751	0	0	0
T8	7275	392	0	0
T9	46086	1027	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	2001	0	0
T39	0	2644	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	2184	0	0
T64	0	272	0	0
T70	0	868	0	0
T71	0	1713	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7217240	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23166	0	0
T6	12030	11575	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	421	0	0
T8	7275	2	0	0
T9	46086	0	0	0
T21	509	0	0	0
T39	0	13	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T51	856	0	0	0
T71	0	16	0	0
T88	404	0	0	0
T89	403	0	0	0
T90	0	4	0	0
T91	0	35	0	0
T92	0	23	0	0
T95	0	8	0	0
T111	0	2	0	0
T113	419	0	0	0
T224	0	13	0	0
T269	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	63951	0	0
T5	23603	2245	0	0
T6	12030	1325	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	1669	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	3059	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	2256	0	0
T64	0	177	0	0
T70	0	1359	0	0
T121	0	79	0	0
T123	0	605	0	0
T124	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	791	0	0
T5	23603	10	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	13	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	29	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	28	0	0
T64	0	8	0	0
T70	0	14	0	0
T121	0	6	0	0
T123	0	10	0	0
T124	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6816368	0	0
T1	8172	6968	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	18131	0	0
T6	12030	7237	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6818445	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	18131	0	0
T6	12030	7237	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1453	0	0
T5	23603	10	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	6	0	0
T9	46086	13	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	29	0	0
T39	0	22	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	28	0	0
T64	0	8	0	0
T70	0	14	0	0
T71	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	1417	0	0
T5	23603	10	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	6	0	0
T9	46086	13	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	29	0	0
T39	0	22	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	28	0	0
T64	0	8	0	0
T70	0	14	0	0
T71	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	791	0	0
T5	23603	10	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	13	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	29	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	28	0	0
T64	0	8	0	0
T70	0	14	0	0
T121	0	6	0	0
T123	0	10	0	0
T124	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	791	0	0
T5	23603	10	0	0
T6	12030	25	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	13	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	29	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	28	0	0
T64	0	8	0	0
T70	0	14	0	0
T121	0	6	0	0
T123	0	10	0	0
T124	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	63061	0	0
T5	23603	2227	0	0
T6	12030	1298	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	1649	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	3030	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	2228	0	0
T64	0	169	0	0
T70	0	1339	0	0
T121	0	73	0	0
T123	0	595	0	0
T124	0	99	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	692	0	0
T5	23603	2	0	0
T6	12030	23	0	0
T7	136751	0	0	0
T8	7275	0	0	0
T9	46086	6	0	0
T14	423	0	0	0
T22	715	0	0	0
T38	0	29	0	0
T45	402	0	0	0
T46	423	0	0	0
T47	542	0	0	0
T61	0	28	0	0
T64	0	8	0	0
T70	0	8	0	0
T121	0	6	0	0
T123	0	10	0	0
T124	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T5,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T5,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T26,T93,T49
1	0	Covered	T49,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T6
1	-	Covered	T1,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T6
DetectSt	168	Covered	T1,T5,T6
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T5,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T6
DebounceSt->IdleSt	163	Covered	T38,T27,T61
DetectSt->IdleSt	186	Covered	T26,T93,T49
DetectSt->StableSt	191	Covered	T1,T5,T6
IdleSt->DebounceSt	148	Covered	T1,T5,T6
StableSt->IdleSt	206	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T49,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T27,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T6
DetectSt	-	-	-	-	1	-	-	Covered	T26,T93,T49
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7861742	815	0	0
CntIncr_A	7861742	46329	0	0
CntNoWrap_A	7861742	7219295	0	0
DetectStDropOut_A	7861742	57	0	0
DetectedOut_A	7861742	12970	0	0
DetectedPulseOut_A	7861742	319	0	0
DisabledIdleSt_A	7861742	6864836	0	0
DisabledNoDetection_A	7861742	6866488	0	0
EnterDebounceSt_A	7861742	436	0	0
EnterDetectSt_A	7861742	380	0	0
EnterStableSt_A	7861742	319	0	0
PulseIsPulse_A	7861742	319	0	0
StayInStableSt	7861742	12621	0	0
gen_high_level_sva.HighLevelEvent_A	7861742	7222376	0	0
gen_not_sticky_sva.StableStDropOut_A	7861742	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	815	0	0
T1	8172	26	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	16	0	0
T6	12030	2	0	0
T7	136751	0	0	0
T9	0	6	0	0
T10	0	2	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	2	0	0
T26	0	2	0	0
T27	0	17	0	0
T38	0	5	0	0
T70	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	46329	0	0
T1	8172	702	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	536	0	0
T6	12030	74	0	0
T7	136751	0	0	0
T9	0	153	0	0
T10	0	169	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	58	0	0
T26	0	155	0	0
T27	0	1102	0	0
T38	0	250	0	0
T70	0	282	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7219295	0	0
T1	8172	6942	0	0
T2	13431	13022	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	23170	0	0
T6	12030	11623	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	57	0	0
T26	14698	1	0	0
T40	648	0	0	0
T41	722	0	0	0
T48	1001	0	0	0
T49	0	1	0	0
T61	9245	0	0	0
T62	576	0	0	0
T63	422	0	0	0
T64	8683	0	0	0
T66	526	0	0	0
T93	0	2	0	0
T161	0	1	0	0
T184	0	4	0	0
T253	0	1	0	0
T270	0	2	0	0
T271	0	5	0	0
T272	0	1	0	0
T273	0	3	0	0
T274	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	12970	0	0
T1	8172	449	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	355	0	0
T6	12030	179	0	0
T7	136751	0	0	0
T9	0	275	0	0
T10	0	65	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	14	0	0
T27	0	277	0	0
T38	0	116	0	0
T61	0	54	0	0
T70	0	392	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	319	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	8	0	0
T6	12030	1	0	0
T7	136751	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T27	0	8	0	0
T38	0	2	0	0
T61	0	1	0	0
T70	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6864836	0	0
T1	8172	4556	0	0
T2	13431	10073	0	0
T3	1179	778	0	0
T4	2117	113	0	0
T5	23603	20949	0	0
T6	12030	10302	0	0
T7	136751	134747	0	0
T12	524	123	0	0
T13	614	213	0	0
T14	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	6866488	0	0
T1	8172	4557	0	0
T2	13431	10073	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	20950	0	0
T6	12030	10303	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	436	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	8	0	0
T6	12030	1	0	0
T7	136751	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T26	0	1	0	0
T27	0	9	0	0
T38	0	3	0	0
T70	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	380	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	8	0	0
T6	12030	1	0	0
T7	136751	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T26	0	1	0	0
T27	0	8	0	0
T38	0	2	0	0
T70	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	319	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	8	0	0
T6	12030	1	0	0
T7	136751	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T27	0	8	0	0
T38	0	2	0	0
T61	0	1	0	0
T70	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	319	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	8	0	0
T6	12030	1	0	0
T7	136751	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T27	0	8	0	0
T38	0	2	0	0
T61	0	1	0	0
T70	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	12621	0	0
T1	8172	436	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	347	0	0
T6	12030	178	0	0
T7	136751	0	0	0
T9	0	272	0	0
T10	0	64	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	13	0	0
T27	0	269	0	0
T38	0	114	0	0
T61	0	53	0	0
T70	0	380	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	7222376	0	0
T1	8172	6971	0	0
T2	13431	13027	0	0
T3	1179	779	0	0
T4	2117	117	0	0
T5	23603	23195	0	0
T6	12030	11628	0	0
T7	136751	134751	0	0
T12	524	124	0	0
T13	614	214	0	0
T14	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7861742	287	0	0
T1	8172	13	0	0
T2	13431	0	0	0
T3	1179	0	0	0
T4	2117	0	0	0
T5	23603	8	0	0
T6	12030	1	0	0
T7	136751	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	524	0	0	0
T13	614	0	0	0
T14	423	0	0	0
T18	0	1	0	0
T27	0	8	0	0
T28	0	4	0	0
T38	0	2	0	0
T61	0	1	0	0