Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1321089303	9455	0	0
auto_block_debounce_ctl_rd_A	1321089303	2055	0	0
auto_block_out_ctl_rd_A	1321089303	2946	0	0
com_det_ctl_0_rd_A	1321089303	3625	0	0
com_det_ctl_1_rd_A	1321089303	3529	0	0
com_det_ctl_2_rd_A	1321089303	3569	0	0
com_det_ctl_3_rd_A	1321089303	3674	0	0
com_out_ctl_0_rd_A	1321089303	4499	0	0
com_out_ctl_1_rd_A	1321089303	4533	0	0
com_out_ctl_2_rd_A	1321089303	4272	0	0
com_out_ctl_3_rd_A	1321089303	4369	0	0
com_pre_det_ctl_0_rd_A	1321089303	1598	0	0
com_pre_det_ctl_1_rd_A	1321089303	1522	0	0
com_pre_det_ctl_2_rd_A	1321089303	1553	0	0
com_pre_det_ctl_3_rd_A	1321089303	1590	0	0
com_pre_sel_ctl_0_rd_A	1321089303	4334	0	0
com_pre_sel_ctl_1_rd_A	1321089303	4528	0	0
com_pre_sel_ctl_2_rd_A	1321089303	4707	0	0
com_pre_sel_ctl_3_rd_A	1321089303	4727	0	0
com_sel_ctl_0_rd_A	1321089303	4485	0	0
com_sel_ctl_1_rd_A	1321089303	4633	0	0
com_sel_ctl_2_rd_A	1321089303	4690	0	0
com_sel_ctl_3_rd_A	1321089303	4636	0	0
ec_rst_ctl_rd_A	1321089303	2389	0	0
intr_enable_rd_A	1321089303	2067	0	0
key_intr_ctl_rd_A	1321089303	5187	0	0
key_intr_debounce_ctl_rd_A	1321089303	1613	0	0
key_invert_ctl_rd_A	1321089303	6565	0	0
pin_allowed_ctl_rd_A	1321089303	7949	0	0
pin_out_ctl_rd_A	1321089303	5470	0	0
pin_out_value_rd_A	1321089303	5792	0	0
regwen_rd_A	1321089303	1756	0	0
ulp_ac_debounce_ctl_rd_A	1321089303	1609	0	0
ulp_ctl_rd_A	1321089303	1684	0	0
ulp_lid_debounce_ctl_rd_A	1321089303	1587	0	0
ulp_pwrb_debounce_ctl_rd_A	1321089303	1582	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	9455	0	0
T10	845936	7	0	0
T11	56659	0	0	0
T18	0	26	0	0
T20	0	8	0	0
T27	359779	0	0	0
T34	0	7	0	0
T38	243277	0	0	0
T39	311123	0	0	0
T44	0	8	0	0
T52	102584	0	0	0
T69	56575	0	0	0
T72	0	10	0	0
T112	0	16	0	0
T114	200373	0	0	0
T116	0	14	0	0
T296	0	14	0	0
T297	0	9	0	0
T298	129219	0	0	0
T299	49092	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	2055	0	0
T34	105892	0	0	0
T44	108578	37	0	0
T80	0	11	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T106	0	13	0	0
T139	0	12	0	0
T158	0	1	0	0
T205	98747	0	0	0
T229	0	3	0	0
T253	0	13	0	0
T294	0	6	0	0
T300	0	15	0	0
T301	0	9	0	0
T302	70858	0	0	0
T303	56349	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	2946	0	0
T34	105892	0	0	0
T44	108578	29	0	0
T80	0	17	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T106	0	10	0	0
T139	0	5	0	0
T158	0	13	0	0
T205	98747	0	0	0
T229	0	17	0	0
T253	0	12	0	0
T294	0	6	0	0
T301	0	12	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	47	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	3625	0	0
T6	288758	46	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	72	0	0
T39	0	50	0	0
T44	0	7	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	50	0	0
T76	0	75	0	0
T88	97161	0	0	0
T121	0	37	0	0
T123	0	42	0	0
T124	0	16	0	0
T263	0	73	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	3529	0	0
T6	288758	40	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	37	0	0
T39	0	48	0	0
T44	0	19	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	56	0	0
T76	0	83	0	0
T88	97161	0	0	0
T121	0	63	0	0
T123	0	53	0	0
T124	0	23	0	0
T263	0	68	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	3569	0	0
T6	288758	26	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	34	0	0
T39	0	38	0	0
T44	0	17	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	55	0	0
T76	0	68	0	0
T88	97161	0	0	0
T121	0	48	0	0
T123	0	39	0	0
T124	0	3	0	0
T263	0	70	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	3674	0	0
T6	288758	43	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	54	0	0
T39	0	61	0	0
T44	0	4	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	58	0	0
T76	0	55	0	0
T88	97161	0	0	0
T121	0	52	0	0
T123	0	47	0	0
T124	0	20	0	0
T263	0	87	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4499	0	0
T6	288758	48	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	46	0	0
T39	0	48	0	0
T44	0	20	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	51	0	0
T76	0	68	0	0
T88	97161	0	0	0
T121	0	49	0	0
T123	0	64	0	0
T124	0	33	0	0
T263	0	73	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4533	0	0
T6	288758	39	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	38	0	0
T39	0	42	0	0
T44	0	23	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	61	0	0
T76	0	77	0	0
T88	97161	0	0	0
T121	0	50	0	0
T123	0	48	0	0
T124	0	21	0	0
T263	0	96	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4272	0	0
T6	288758	51	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	45	0	0
T39	0	46	0	0
T44	0	19	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	70	0	0
T76	0	79	0	0
T88	97161	0	0	0
T121	0	48	0	0
T123	0	31	0	0
T124	0	24	0	0
T263	0	61	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4369	0	0
T6	288758	33	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	34	0	0
T39	0	43	0	0
T44	0	16	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	64	0	0
T76	0	55	0	0
T88	97161	0	0	0
T121	0	49	0	0
T123	0	50	0	0
T124	0	23	0	0
T263	0	68	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1598	0	0
T34	105892	0	0	0
T44	108578	13	0	0
T80	0	6	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T167	0	7	0	0
T184	0	24	0	0
T185	0	10	0	0
T193	0	40	0	0
T195	0	17	0	0
T205	98747	0	0	0
T253	0	1	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	15	0	0
T305	0	13	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1522	0	0
T34	105892	0	0	0
T44	108578	20	0	0
T80	0	17	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T167	0	10	0	0
T179	0	18	0	0
T184	0	37	0	0
T185	0	2	0	0
T193	0	19	0	0
T195	0	14	0	0
T205	98747	0	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	21	0	0
T305	0	3	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1553	0	0
T34	105892	0	0	0
T44	108578	16	0	0
T80	0	28	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T167	0	11	0	0
T184	0	20	0	0
T185	0	5	0	0
T193	0	16	0	0
T195	0	21	0	0
T205	98747	0	0	0
T253	0	4	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	20	0	0
T305	0	3	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1590	0	0
T34	105892	0	0	0
T44	108578	17	0	0
T80	0	6	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T167	0	16	0	0
T184	0	21	0	0
T185	0	5	0	0
T193	0	14	0	0
T195	0	13	0	0
T205	98747	0	0	0
T253	0	9	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	12	0	0
T305	0	10	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4334	0	0
T6	288758	53	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	38	0	0
T39	0	68	0	0
T44	0	15	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	53	0	0
T76	0	57	0	0
T88	97161	0	0	0
T121	0	49	0	0
T123	0	57	0	0
T124	0	25	0	0
T263	0	58	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4528	0	0
T6	288758	41	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	26	0	0
T39	0	66	0	0
T44	0	17	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	44	0	0
T76	0	75	0	0
T88	97161	0	0	0
T121	0	37	0	0
T123	0	28	0	0
T124	0	15	0	0
T263	0	66	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4707	0	0
T6	288758	36	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	47	0	0
T39	0	59	0	0
T44	0	15	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	54	0	0
T76	0	56	0	0
T88	97161	0	0	0
T121	0	46	0	0
T123	0	33	0	0
T124	0	10	0	0
T263	0	57	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4727	0	0
T6	288758	57	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	34	0	0
T39	0	46	0	0
T44	0	16	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	69	0	0
T76	0	59	0	0
T88	97161	0	0	0
T121	0	58	0	0
T123	0	38	0	0
T124	0	4	0	0
T263	0	73	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4485	0	0
T6	288758	34	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	29	0	0
T39	0	65	0	0
T44	0	15	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	50	0	0
T76	0	71	0	0
T88	97161	0	0	0
T121	0	45	0	0
T123	0	45	0	0
T124	0	32	0	0
T263	0	63	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4633	0	0
T6	288758	35	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	38	0	0
T39	0	54	0	0
T44	0	11	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	60	0	0
T76	0	75	0	0
T88	97161	0	0	0
T121	0	49	0	0
T123	0	34	0	0
T124	0	30	0	0
T263	0	70	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4690	0	0
T6	288758	40	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	44	0	0
T39	0	41	0	0
T44	0	14	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	59	0	0
T76	0	81	0	0
T88	97161	0	0	0
T121	0	30	0	0
T123	0	42	0	0
T124	0	22	0	0
T263	0	61	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	4636	0	0
T6	288758	74	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	42	0	0
T39	0	42	0	0
T44	0	12	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	55	0	0
T76	0	55	0	0
T88	97161	0	0	0
T121	0	67	0	0
T123	0	41	0	0
T124	0	26	0	0
T263	0	71	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	2389	0	0
T6	288758	4	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T9	576079	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T26	0	14	0	0
T39	0	21	0	0
T44	0	22	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T71	0	13	0	0
T76	0	21	0	0
T88	97161	0	0	0
T92	0	3	0	0
T121	0	1	0	0
T123	0	1	0	0
T306	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	2067	0	0
T34	105892	0	0	0
T44	108578	10	0	0
T80	0	14	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T184	0	27	0	0
T185	0	6	0	0
T193	0	60	0	0
T195	0	20	0	0
T205	98747	0	0	0
T229	0	9	0	0
T253	0	22	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	30	0	0
T305	0	13	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	5187	0	0
T26	698207	0	0	0
T29	253062	0	0	0
T35	105973	9	0	0
T40	155539	0	0	0
T44	0	27	0	0
T48	475879	0	0	0
T61	970718	0	0	0
T62	77874	0	0	0
T63	200512	0	0	0
T64	104194	0	0	0
T66	65813	0	0	0
T83	0	6	0	0
T143	0	2	0	0
T153	0	6	0	0
T158	0	3	0	0
T159	0	7	0	0
T180	0	8	0	0
T182	0	2	0	0
T307	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1613	0	0
T34	105892	0	0	0
T44	108578	11	0	0
T80	0	18	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T167	0	18	0	0
T184	0	19	0	0
T185	0	5	0	0
T193	0	26	0	0
T195	0	16	0	0
T205	98747	0	0	0
T253	0	3	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	24	0	0
T305	0	5	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	6565	0	0
T34	105892	0	0	0
T44	108578	86	0	0
T57	0	62	0	0
T59	0	68	0	0
T60	0	56	0	0
T80	0	22	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T149	0	61	0	0
T205	98747	0	0	0
T253	0	69	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T308	0	31	0	0
T309	0	88	0	0
T310	0	67	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	7949	0	0
T10	845936	0	0	0
T11	56659	0	0	0
T21	43294	65	0	0
T27	359779	0	0	0
T38	243277	0	0	0
T44	0	19	0	0
T51	239828	0	0	0
T65	0	33	0	0
T89	96722	0	0	0
T109	0	74	0	0
T113	75496	0	0	0
T114	200373	0	0	0
T159	0	67	0	0
T226	0	39	0	0
T253	0	142	0	0
T298	129219	0	0	0
T311	0	27	0	0
T312	0	28	0	0
T313	0	52	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	5470	0	0
T10	845936	0	0	0
T11	56659	0	0	0
T21	43294	58	0	0
T27	359779	0	0	0
T38	243277	0	0	0
T44	0	7	0	0
T51	239828	0	0	0
T65	0	44	0	0
T89	96722	0	0	0
T109	0	52	0	0
T113	75496	0	0	0
T114	200373	0	0	0
T159	0	51	0	0
T226	0	47	0	0
T253	0	111	0	0
T298	129219	0	0	0
T311	0	66	0	0
T312	0	30	0	0
T313	0	55	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	5792	0	0
T10	845936	0	0	0
T11	56659	0	0	0
T21	43294	57	0	0
T27	359779	0	0	0
T38	243277	0	0	0
T44	0	22	0	0
T51	239828	0	0	0
T65	0	38	0	0
T89	96722	0	0	0
T109	0	62	0	0
T113	75496	0	0	0
T114	200373	0	0	0
T159	0	40	0	0
T226	0	43	0	0
T253	0	121	0	0
T298	129219	0	0	0
T311	0	14	0	0
T312	0	50	0	0
T313	0	83	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1756	0	0
T34	105892	0	0	0
T44	108578	18	0	0
T80	0	12	0	0
T82	80051	0	0	0
T86	81010	0	0	0
T87	113884	0	0	0
T90	121649	0	0	0
T91	253342	0	0	0
T167	0	11	0	0
T179	0	18	0	0
T184	0	27	0	0
T185	0	6	0	0
T193	0	29	0	0
T195	0	8	0	0
T205	98747	0	0	0
T302	70858	0	0	0
T303	56349	0	0	0
T304	0	17	0	0
T305	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1609	0	0
T3	222823	5	0	0
T5	318653	0	0	0
T6	288758	0	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T44	0	17	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T52	0	5	0	0
T73	0	9	0	0
T105	0	2	0	0
T127	0	10	0	0
T213	0	6	0	0
T253	0	8	0	0
T314	0	6	0	0
T315	0	10	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1684	0	0
T3	222823	10	0	0
T5	318653	0	0	0
T6	288758	0	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T44	0	27	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T52	0	6	0	0
T73	0	9	0	0
T79	0	4	0	0
T105	0	8	0	0
T213	0	4	0	0
T253	0	7	0	0
T314	0	5	0	0
T316	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1587	0	0
T3	222823	7	0	0
T5	318653	0	0	0
T6	288758	0	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T44	0	20	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T52	0	2	0	0
T73	0	3	0	0
T79	0	2	0	0
T127	0	8	0	0
T213	0	6	0	0
T253	0	12	0	0
T314	0	3	0	0
T316	0	5	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1321089303	1582	0	0
T3	222823	3	0	0
T5	318653	0	0	0
T6	288758	0	0	0
T7	674800	0	0	0
T8	291034	0	0	0
T14	106038	0	0	0
T22	89438	0	0	0
T44	0	30	0	0
T45	191243	0	0	0
T46	112142	0	0	0
T47	51492	0	0	0
T52	0	1	0	0
T73	0	10	0	0
T79	0	5	0	0
T105	0	7	0	0
T213	0	7	0	0
T253	0	3	0	0
T314	0	8	0	0
T316	0	5	0	0