Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1926

1

T1

10

T7

12

T11

4

auto[1]

651

1

T1

2

T10

6

T36

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1860

1

T1

12

T7

12

T10

4

auto[1]

717

1

T10

2

T12

13

T36

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1982

1

T1

12

T7

9

T10

6

auto[1]

595

1

T7

3

T12

11

T36

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1922

1

T1

11

T7

12

T10

3

auto[1]

655

1

T1

1

T10

3

T11

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2400

1

T1

11

T7

12

T10

6

auto[1]

177

1

T1

1

T11

1

T12

16

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2335

1

T1

11

T7

12

T10

6

auto[1]

242

1

T1

1

T12

3

T37

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2353

1

T1

12

T7

12

T10

6

auto[1]

224

1

T37

4

T75

1

T88

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2406

1

T1

10

T7

12

T10

6

auto[1]

171

1

T1

2

T37

1

T73

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2399

1

T1

12

T7

9

T10

6

auto[1]

178

1

T7

3

T12

5

T37

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1919

1

T1

11

T7

12

T10

2

auto[1]

658

1

T1

1

T10

4

T12

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

956

1

T10

6

T36

7

T51

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

52

1

T11

1

T12

4

T37

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T7

3

T74

6

T119

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T12

1

T75

2

T362

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

74

1

T1

2

T119

4

T107

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T74

3

T363

3

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T37

1

T365

4

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

68

1

T88

1

T366

3

T367

38

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T37

1

T119

3

T368

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T360

4

T369

6

T361

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T245

3

T370

4

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T79

5

T348

6

T217

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

11

1

T360

3

T371

1

T372

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

90

1

T107

4

T158

3

T245

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T1

1

T12

3

T91

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

19

1

T348

3

T355

7

T373

9

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T365

1

T374

2

T375

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

16

1

T268

1

T79

5

T366

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T91

5

T359

5

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T376

4

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T37

3

T158

2

T376

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T376

5

T377

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

10

1

T75

1

T370

3

T219

1

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

116

1

T1

2

T37

3

T107

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

105

1

T91

11

T106

10

T377

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

42

1

T10

3

T75

1

T107

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T11

1

T245

3

T365

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

61

1

T39

6

T119

2

T120

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

84

1

T1

1

T119

3

T158

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

50

1

T10

1

T245

10

T376

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

143

1

T7

3

T37

1

T91

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T38

6

T376

11

T378

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T167

10

T191

5

T266

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T269

1

T79

5

T366

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T36

4

T38

7

T374

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T92

3

T44

2

T350

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43

1

T12

3

T36

2

T53

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T379

1

T190

6

T380

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

171

1

T12

1

T53

13

T74

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

58

1

T39

6

T94

16

T379

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T271

4

T245

8

T360

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T79

5

T264

6

T363

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T360

4

T375

5

T364

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T10

2

T349

8

T188

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T37

1

T271

4

T44

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T43

3

T367

19

T381

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T37

2

T74

6

T365

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

54

1

T51

3

T119

2

T245

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

13

1

T39

1

T43

2

T180

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T380

1

T382

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T12

4

T158

3

T167

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T36

1

T92

2

T43

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T93

1

T44

1

T226

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T349

1

T188

1

T112

4

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded