Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T4

9

T6

11

T47

9

auto[1]

1066

1

T4

11

T6

9

T47

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T4

5

T6

5

T47

7

from_0to1

534

1

T4

6

T6

4

T47

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T4

7

T6

5

T47

6

auto[1]

1098

1

T4

13

T6

15

T47

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T4

11

T6

11

T47

12

auto[1]

1087

1

T4

9

T6

9

T47

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T4

1

T68

1

T396

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T6

1

T306

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T47

1

T68

2

T72

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T47

2

T68

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T4

1

T6

1

T68

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T4

1

T6

1

T68

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T4

2

T6

1

T47

2

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T47

1

T69

1

T72

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T4

1

T68

2

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T4

1

T69

2

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T4

1

T47

2

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T4

1

T6

4

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T4

2

T47

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T47

2

T68

1

T396

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T6

1

T72

1

T396

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T47

1

T72

1

T306

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T4

12

T6

7

T47

8

auto[1]

1091

1

T4

8

T6

13

T47

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

499

1

T4

3

T6

6

T47

4

from_0to1

510

1

T4

4

T6

6

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T4

10

T6

7

T47

9

auto[1]

1147

1

T4

10

T6

13

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T4

8

T6

15

T47

5

auto[1]

1120

1

T4

12

T6

5

T47

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T6

1

T68

1

T306

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T47

1

T307

1

T132

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T4

2

T6

1

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T69

1

T72

1

T396

1

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T68

2

T45

1

T199

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T4

1

T69

1

T72

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T6

2

T306

1

T307

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T4

2

T47

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T4

1

T6

1

T306

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T47

2

T69

2

T72

3

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T6

2

T69

1

T306

3

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T6

1

T72

1

T396

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T6

1

T47

1

T396

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T6

1

T47

1

T72

3

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T69

2

T307

1

T45

3

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T4

1

T6

2

T47

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T4

9

T6

10

T47

10

auto[1]

1099

1

T4

11

T6

10

T47

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T4

6

T6

5

T47

6

from_0to1

517

1

T4

5

T6

5

T47

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T4

12

T6

8

T47

6

auto[1]

1059

1

T4

8

T6

12

T47

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T4

9

T6

9

T47

9

auto[1]

1080

1

T4

11

T6

11

T47

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T4

1

T47

1

T396

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T4

1

T6

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T6

1

T68

1

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T4

1

T6

1

T47

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T4

2

T6

1

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T4

1

T68

1

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T4

1

T47

2

T69

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T6

2

T47

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T4

1

T68

1

T306

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T4

1

T6

1

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T4

1

T47

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T6

1

T47

2

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T6

1

T47

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T47

1

T68

3

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T4

1

T6

1

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T199

1

T127

1

T92

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T4

11

T6

14

T47

8

auto[1]

1098

1

T4

9

T6

6

T47

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T4

6

T6

3

T47

5

from_0to1

521

1

T4

5

T6

3

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T4

14

T6

13

T47

9

auto[1]

1064

1

T4

6

T6

7

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T4

8

T6

13

T47

11

auto[1]

1049

1

T4

12

T6

7

T47

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T4

2

T47

1

T306

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T4

2

T6

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T6

1

T47

1

T68

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T47

1

T306

2

T199

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T6

1

T47

1

T68

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T4

2

T69

1

T72

2

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T4

1

T6

1

T47

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T4

1

T6

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T4

1

T68

1

T127

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T69

1

T72

1

T306

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T4

1

T6

1

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T68

2

T72

1

T306

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T47

1

T69

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T4

1

T69

1

T72

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T47

2

T72

1

T45

2

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T396

1

T45

1

T92

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T4

6

T6

9

T47

11

auto[1]

1133

1

T4

14

T6

11

T47

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T4

5

T6

4

T47

4

from_0to1

518

1

T4

6

T6

3

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T4

11

T6

12

T47

9

auto[1]

1057

1

T4

9

T6

8

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T4

16

T6

9

T47

10

auto[1]

1074

1

T4

4

T6

11

T47

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T396

2

T307

1

T132

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T69

1

T45

1

T199

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T4

1

T6

1

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T6

1

T47

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T4

1

T6

1

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T47

1

T72

1

T307

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T47

1

T69

3

T306

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T306

1

T396

1

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T4

1

T47

1

T306

3

auto[1]

from_1to0

auto[0]

auto[1]

89

1

T4

2

T6

1

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T69

1

T396

1

T307

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T4

1

T6

1

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T4

3

T68

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T68

1

T72

1

T306

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T4

2

T6

2

T396

2

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T47

2

T68

2

T72

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T4

9

T6

12

T47

11

auto[1]

1064

1

T4

11

T6

8

T47

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T4

6

T6

5

T47

4

from_0to1

528

1

T4

6

T6

5

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T4

10

T6

12

T47

10

auto[1]

1065

1

T4

10

T6

8

T47

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T4

11

T6

6

T47

13

auto[1]

1044

1

T4

9

T6

14

T47

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T4

1

T47

1

T68

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T6

1

T68

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T47

1

T69

2

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T6

1

T47

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T69

1

T72

2

T307

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T4

1

T6

2

T47

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T4

2

T69

2

T72

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T6

1

T68

1

T307

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T4

1

T6

1

T306

2

auto[1]

from_1to0

auto[0]

auto[1]

83

1

T4

1

T6

1

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T4

2

T6

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T68

1

T69

1

T306

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T72

1

T396

1

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T4

2

T6

2

T68

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T47

1

T72

2

T396

3

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T4

1

T47

1

T69

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T4

8

T6

12

T47

10

auto[1]

1079

1

T4

12

T6

8

T47

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T4

3

T6

4

T47

6

from_0to1

520

1

T4

4

T6

4

T47

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T4

9

T6

8

T47

8

auto[1]

1074

1

T4

11

T6

12

T47

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T4

10

T6

9

T47

12

auto[1]

1025

1

T4

10

T6

11

T47

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T4

1

T47

2

T68

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T6

1

T69

1

T306

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T4

1

T72

1

T306

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T47

1

T72

2

T307

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T68

1

T72

1

T396

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T72

1

T306

1

T396

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T6

3

T47

2

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T4

1

T47

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T69

1

T72

1

T92

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T6

1

T47

1

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T6

1

T47

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T6

1

T68

1

T69

2

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T4

2

T68

1

T69

2

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T68

1

T69

2

T396

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T47

2

T72

1

T306

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T4

1

T6

1

T47

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T4

10

T6

11

T47

7

auto[1]

1054

1

T4

10

T6

9

T47

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T4

6

T6

5

T47

5

from_0to1

509

1

T4

6

T6

5

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T4

12

T6

11

T47

8

auto[1]

1027

1

T4

8

T6

9

T47

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T4

11

T6

4

T47

12

auto[1]

1034

1

T4

9

T6

16

T47

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T4

1

T47

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T4

1

T6

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T47

1

T68

1

T72

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T68

3

T69

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T4

1

T68

1

T69

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T6

3

T68

1

T69

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T6

1

T47

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T68

1

T396

1

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T4

1

T47

1

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T4

1

T6

1

T306

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T4

1

T47

2

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T4

1

T6

3

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T4

2

T47

2

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T4

1

T6

1

T47

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T68

1

T69

1

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T4

1

T47

1

T68

1