Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
51.52	51.52	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_wkup_event_cg	51.52	1	100	1	64	64

---

Group Instance : sysrst_ctrl_wkup_event_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
51.52	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00
Crosses	23	15	8	34.78

Variables for Group Instance sysrst_ctrl_wkup_event_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_h2l_pwrb	2	0	2	100.00	100	1	1	2
cp_h_ac_present	2	0	2	100.00	100	1	1	2
cp_interrupt_gen	2	1	1	50.00	100	1	1	2
cp_l2h_lid_open	2	0	2	100.00	100	1	1	2
cp_wakeup_sts	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_wkup_event_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_wkup_sts	23	15	8	34.78	100	1	1	0

Summary for Variable cp_h2l_pwrb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h2l_pwrb

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

849

1

T4

5

T6

3

T17

2

auto[1]

693

1

T4

6

T6

1

T17

4

---

Summary for Variable cp_h_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_h_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

919

1

T4

5

T6

2

T17

5

auto[1]

623

1

T4

6

T6

2

T17

1

---

Summary for Variable cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_interrupt_gen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1542

1

T4

11

T6

4

T17

6

---

Summary for Variable cp_l2h_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_l2h_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T4

4

T17

4

T3

4

auto[1]

595

1

T4

7

T6

4

T17

2

---

Summary for Variable cp_wakeup_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wakeup_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1482

1

T4

11

T6

4

T17

6

auto[1]

60

1

T3

2

T8

1

T27

1

---

Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	23	15	8	34.78	15
Automatically Generated Cross Bins	23	15	8	34.78	15
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_wkup_sts

Element holes

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	*	--	--	4

Uncovered bins

cp_wakeup_sts	cp_h2l_pwrb	cp_l2h_lid_open	cp_h_ac_present	cp_interrupt_gen	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_wakeup_sts

cp_h2l_pwrb

cp_l2h_lid_open

cp_h_ac_present

cp_interrupt_gen

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

371

1

T17

1

T47

1

T68

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

150

1

T4

3

T47

1

T68

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

157

1

T4

1

T6

2

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

171

1

T4

1

T6

1

T17

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

206

1

T4

1

T17

3

T3

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

160

1

T3

1

T19

1

T70

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

125

1

T4

3

T17

1

T19

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

142

1

T4

2

T6

1

T3

1

User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded