Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115667

1

T4

237

T5

17

T6

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137286	1			T4	255		T5	26		T6	62
values[0x0]	63654	1			T4	120		T5	9		T6	36
values[0x1]	64499	1			T4	95		T5	11		T6	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143749

1

T4

276

T5

19

T6

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	896	1			T1	2		T18	6		T7	2
valid_sources[0x01]	981	1			T7	28		T9	1		T11	12
valid_sources[0x02]	893	1			T1	3		T10	1		T12	10
valid_sources[0x03]	937	1			T20	1		T1	2		T2	2
valid_sources[0x04]	952	1			T7	8		T10	3		T11	9
valid_sources[0x05]	839	1			T6	5		T1	8		T10	2
valid_sources[0x06]	1096	1			T1	1		T7	5		T10	7
valid_sources[0x07]	1039	1			T6	4		T7	3		T19	1
valid_sources[0x08]	746	1			T1	4		T10	1		T47	1
valid_sources[0x09]	869	1			T16	2		T7	2		T10	1
valid_sources[0x0a]	1124	1			T6	3		T1	2		T2	6
valid_sources[0x0b]	1025	1			T6	5		T1	2		T7	3
valid_sources[0x0c]	784	1			T22	1		T7	2		T10	10
valid_sources[0x0d]	863	1			T1	4		T17	1		T10	4
valid_sources[0x0e]	1155	1			T1	1		T7	1		T10	2
valid_sources[0x0f]	855	1			T1	3		T17	1		T19	1
valid_sources[0x10]	926	1			T1	4		T17	1		T10	3
valid_sources[0x11]	879	1			T1	6		T10	3		T12	8
valid_sources[0x12]	842	1			T1	6		T17	1		T7	2
valid_sources[0x13]	892	1			T9	1		T11	23		T47	1
valid_sources[0x14]	833	1			T1	6		T12	9		T47	3
valid_sources[0x15]	921	1			T7	12		T10	1		T11	7
valid_sources[0x16]	1602	1			T7	3		T19	1		T12	5
valid_sources[0x17]	896	1			T1	10		T10	4		T12	1
valid_sources[0x18]	1076	1			T1	2		T17	1		T12	6
valid_sources[0x19]	1854	1			T23	6		T1	2		T7	3
valid_sources[0x1a]	882	1			T1	1		T10	4		T11	10
valid_sources[0x1b]	990	1			T4	12		T1	5		T7	2
valid_sources[0x1c]	905	1			T1	1		T11	5		T12	5
valid_sources[0x1d]	1323	1			T21	1		T1	3		T10	2
valid_sources[0x1e]	967	1			T1	2		T17	1		T11	8
valid_sources[0x1f]	786	1			T6	2		T1	3		T10	1
valid_sources[0x20]	888	1			T1	9		T10	6		T47	1
valid_sources[0x21]	865	1			T1	13		T17	1		T7	5
valid_sources[0x22]	1283	1			T1	7		T10	5		T12	3
valid_sources[0x23]	925	1			T4	20		T1	3		T7	14
valid_sources[0x24]	890	1			T1	9		T10	4		T11	1
valid_sources[0x25]	1282	1			T1	2		T7	8		T10	4
valid_sources[0x26]	1088	1			T6	3		T1	7		T2	1
valid_sources[0x27]	1031	1			T1	4		T7	6		T10	2
valid_sources[0x28]	898	1			T22	1		T1	2		T7	7
valid_sources[0x29]	1670	1			T1	7		T18	1		T19	1
valid_sources[0x2a]	1057	1			T10	1		T11	9		T68	1
valid_sources[0x2b]	994	1			T1	1		T10	1		T11	12
valid_sources[0x2c]	898	1			T6	1		T1	3		T7	25
valid_sources[0x2d]	1103	1			T1	3		T7	8		T10	2
valid_sources[0x2e]	944	1			T1	12		T58	1		T10	2
valid_sources[0x2f]	861	1			T1	3		T7	17		T9	1
valid_sources[0x30]	914	1			T1	3		T7	7		T19	1
valid_sources[0x31]	781	1			T23	1		T7	8		T12	9
valid_sources[0x32]	1330	1			T17	1		T7	6		T10	7
valid_sources[0x33]	998	1			T1	2		T7	3		T10	3
valid_sources[0x34]	836	1			T6	1		T1	4		T3	45
valid_sources[0x35]	1139	1			T6	3		T1	1		T17	1
valid_sources[0x36]	962	1			T1	4		T17	1		T10	5
valid_sources[0x37]	1009	1			T1	4		T19	1		T10	4
valid_sources[0x38]	898	1			T6	1		T58	1		T11	8
valid_sources[0x39]	968	1			T1	6		T12	4		T47	1
valid_sources[0x3a]	1330	1			T1	9		T7	6		T10	4
valid_sources[0x3b]	1065	1			T1	3		T12	1		T47	1
valid_sources[0x3c]	938	1			T6	4		T1	3		T10	3
valid_sources[0x3d]	1056	1			T1	2		T7	1		T12	5
valid_sources[0x3e]	928	1			T1	1		T17	1		T19	3
valid_sources[0x3f]	849	1			T6	1		T1	12		T19	1
valid_sources[0x40]	937	1			T1	2		T17	1		T7	3
valid_sources[0x41]	1492	1			T6	1		T1	9		T10	7
valid_sources[0x42]	913	1			T17	1		T7	2		T10	4
valid_sources[0x43]	1124	1			T4	55		T10	7		T12	2
valid_sources[0x44]	830	1			T6	3		T1	2		T7	2
valid_sources[0x45]	832	1			T1	2		T9	1		T10	1
valid_sources[0x46]	1043	1			T1	3		T10	2		T11	1
valid_sources[0x47]	782	1			T1	7		T11	23		T47	3
valid_sources[0x48]	2859	1			T1	6		T17	1		T10	2
valid_sources[0x49]	929	1			T1	8		T8	3		T10	6
valid_sources[0x4a]	1023	1			T1	1		T7	26		T19	1
valid_sources[0x4b]	1726	1			T6	1		T1	4		T2	2
valid_sources[0x4c]	962	1			T6	1		T1	4		T2	2
valid_sources[0x4d]	873	1			T1	4		T7	1		T10	1
valid_sources[0x4e]	886	1			T1	3		T47	2		T69	2
valid_sources[0x4f]	800	1			T22	1		T17	1		T7	10
valid_sources[0x50]	870	1			T1	4		T10	1		T12	1
valid_sources[0x51]	914	1			T6	1		T7	7		T12	1
valid_sources[0x52]	996	1			T1	10		T19	1		T11	24
valid_sources[0x53]	869	1			T1	2		T7	2		T10	5
valid_sources[0x54]	905	1			T1	8		T7	6		T10	2
valid_sources[0x55]	827	1			T1	8		T19	2		T29	1
valid_sources[0x56]	1268	1			T7	7		T12	2		T47	2
valid_sources[0x57]	817	1			T1	15		T10	3		T11	6
valid_sources[0x58]	937	1			T1	7		T17	1		T8	3
valid_sources[0x59]	977	1			T1	10		T17	1		T7	3
valid_sources[0x5a]	1758	1			T1	12		T7	1		T9	1
valid_sources[0x5b]	1263	1			T6	6		T22	1		T1	2
valid_sources[0x5c]	966	1			T1	2		T7	2		T10	3
valid_sources[0x5d]	1319	1			T1	2		T10	9		T12	2
valid_sources[0x5e]	969	1			T4	3		T1	2		T17	1
valid_sources[0x5f]	979	1			T1	3		T7	3		T10	2
valid_sources[0x60]	848	1			T22	1		T17	1		T19	2
valid_sources[0x61]	1111	1			T1	5		T10	7		T11	1
valid_sources[0x62]	826	1			T1	14		T7	7		T19	1
valid_sources[0x63]	891	1			T7	7		T10	1		T11	17
valid_sources[0x64]	1015	1			T7	7		T10	2		T47	2
valid_sources[0x65]	1019	1			T1	3		T17	1		T7	1
valid_sources[0x66]	919	1			T1	11		T7	12		T19	1
valid_sources[0x67]	910	1			T6	1		T1	3		T7	8
valid_sources[0x68]	1091	1			T1	6		T7	3		T19	1
valid_sources[0x69]	990	1			T1	1		T17	1		T7	4
valid_sources[0x6a]	881	1			T1	2		T12	1		T63	1
valid_sources[0x6b]	930	1			T1	3		T10	13		T12	1
valid_sources[0x6c]	829	1			T1	3		T12	5		T47	1
valid_sources[0x6d]	817	1			T1	10		T7	6		T19	1
valid_sources[0x6e]	1051	1			T1	4		T7	6		T10	1
valid_sources[0x6f]	835	1			T10	3		T12	4		T47	1
valid_sources[0x70]	927	1			T1	2		T17	2		T11	2
valid_sources[0x71]	1488	1			T7	4		T10	2		T12	1
valid_sources[0x72]	1215	1			T1	3		T7	3		T8	1
valid_sources[0x73]	985	1			T6	4		T1	9		T7	3
valid_sources[0x74]	865	1			T1	4		T7	5		T11	10
valid_sources[0x75]	899	1			T4	20		T7	17		T11	5
valid_sources[0x76]	873	1			T6	2		T1	12		T18	3
valid_sources[0x77]	1066	1			T1	1		T7	6		T11	24
valid_sources[0x78]	908	1			T6	1		T1	1		T10	3
valid_sources[0x79]	1112	1			T47	1		T36	95		T68	1
valid_sources[0x7a]	962	1			T1	9		T12	4		T47	1
valid_sources[0x7b]	1507	1			T12	4		T29	1		T67	2
valid_sources[0x7c]	1467	1			T1	8		T30	11		T53	1
valid_sources[0x7d]	1610	1			T1	4		T47	1		T68	1
valid_sources[0x7e]	857	1			T1	6		T10	5		T12	1
valid_sources[0x7f]	1024	1			T1	8		T7	6		T8	1
valid_sources[0x80]	1010	1			T6	3		T1	6		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62958

1

T4

148

T5

9

T6

32

values[0x0]

all_enables

biggest_size

30836

1

T4

60

T5

5

T6

19

values[0x1]

all_enables

biggest_size

21873

1

T4

29

T5

3

T6

7