Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T40,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T40,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T54,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T40,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T40,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T54,T56
0	1	Covered	T78,T100,T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T54,T56
0	1	Covered	T4,T54,T56
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T54,T56
1	-	Covered	T4,T54,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T40,T54
DetectSt	168	Covered	T4,T54,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T54,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T54,T56
DebounceSt->IdleSt	163	Covered	T4,T40,T55
DetectSt->IdleSt	186	Covered	T78,T100,T102
DetectSt->StableSt	191	Covered	T4,T54,T56
IdleSt->DebounceSt	148	Covered	T4,T40,T54
StableSt->IdleSt	206	Covered	T4,T54,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T40,T54
0	1	Covered	T4,T40,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T54,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T40,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T54,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T55,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T40,T54
DetectSt	-	-	-	-	1	-	-	Covered	T78,T100,T102
DetectSt	-	-	-	-	0	1	-	Covered	T4,T54,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T54,T56
StableSt	-	-	-	-	-	-	0	Covered	T4,T54,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	235	0	0
CntIncr_A	7718931	226989	0	0
CntNoWrap_A	7718931	7096098	0	0
DetectStDropOut_A	7718931	5	0	0
DetectedOut_A	7718931	643	0	0
DetectedPulseOut_A	7718931	101	0	0
DisabledIdleSt_A	7718931	6863873	0	0
DisabledNoDetection_A	7718931	6866132	0	0
EnterDebounceSt_A	7718931	131	0	0
EnterDetectSt_A	7718931	106	0	0
EnterStableSt_A	7718931	101	0	0
PulseIsPulse_A	7718931	101	0	0
StayInStableSt	7718931	542	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6730	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	101	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	235	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	5	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	13	0	0
T44	0	6	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	4	0	0
T89	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	226989	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	148	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T40	0	21	0	0
T42	0	16	0	0
T43	0	490	0	0
T44	0	123	0	0
T54	0	105	0	0
T55	0	47	0	0
T56	0	82	0	0
T57	0	162	0	0
T89	0	115	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096098	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4081	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	5	0	0
T78	26392	1	0	0
T83	10794	0	0	0
T100	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T108	695	0	0	0
T109	506	0	0	0
T110	10166	0	0	0
T111	27655	0	0	0
T112	35366	0	0	0
T113	441	0	0	0
T114	617	0	0	0
T115	658	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	643	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	20	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	35	0	0
T44	0	20	0	0
T54	0	16	0	0
T56	0	5	0	0
T57	0	10	0	0
T89	0	15	0	0
T116	0	12	0	0
T117	0	3	0	0
T118	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	101	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	2	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T54	0	3	0	0
T56	0	1	0	0
T57	0	2	0	0
T89	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6863873	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	3808	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6866132	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	3816	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	131	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	3	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	7	0	0
T44	0	3	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T89	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	106	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	2	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T54	0	3	0	0
T56	0	1	0	0
T57	0	2	0	0
T89	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	101	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	2	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T54	0	3	0	0
T56	0	1	0	0
T57	0	2	0	0
T89	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	101	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	2	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T54	0	3	0	0
T56	0	1	0	0
T57	0	2	0	0
T89	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	542	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	18	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	29	0	0
T44	0	17	0	0
T54	0	13	0	0
T56	0	4	0	0
T57	0	8	0	0
T89	0	12	0	0
T116	0	10	0	0
T117	0	2	0	0
T118	0	24	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6730	0	0
T1	12854	32	0	0
T2	737	1	0	0
T3	0	11	0	0
T4	7402	20	0	0
T5	1645	4	0	0
T6	505	5	0	0
T14	494	0	0	0
T17	0	5	0	0
T20	424	1	0	0
T21	422	6	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	101	0	0
T1	12854	0	0	0
T2	737	0	0	0
T4	7402	2	0	0
T5	1645	0	0	0
T6	505	0	0	0
T14	494	0	0	0
T20	424	0	0	0
T21	422	0	0	0
T22	410	0	0	0
T23	405	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T54	0	3	0	0
T56	0	1	0	0
T57	0	2	0	0
T89	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T27
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T59
0	1	Covered	T60,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T59
0	1	Unreachable
1	0	Covered	T8,T27,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T27
DetectSt	168	Covered	T8,T27,T59
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T27,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T59
DebounceSt->IdleSt	163	Covered	T3,T40,T42
DetectSt->IdleSt	186	Covered	T60,T86,T87
DetectSt->StableSt	191	Covered	T8,T27,T59
IdleSt->DebounceSt	148	Covered	T3,T8,T27
StableSt->IdleSt	206	Covered	T8,T27,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T27
0	1	Covered	T3,T8,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T59
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T43,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	1	-	-	Covered	T60,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T59
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	156	0	0
CntIncr_A	7718931	354980	0	0
CntNoWrap_A	7718931	7096177	0	0
DetectStDropOut_A	7718931	10	0	0
DetectedOut_A	7718931	22582	0	0
DetectedPulseOut_A	7718931	41	0	0
DisabledIdleSt_A	7718931	6174213	0	0
DisabledNoDetection_A	7718931	6176512	0	0
EnterDebounceSt_A	7718931	107	0	0
EnterDetectSt_A	7718931	51	0	0
EnterStableSt_A	7718931	41	0	0
PulseIsPulse_A	7718931	41	0	0
StayInStableSt	7718931	22541	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6730	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_sticky_sva.StableStDropOut_A	7718931	396220	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	156	0	0
T3	2496	6	0	0
T7	8323	0	0	0
T8	1841	2	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T44	0	2	0	0
T58	815	0	0	0
T59	0	2	0	0
T60	0	4	0	0
T62	0	2	0	0
T63	438	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	354980	0	0
T3	2496	600	0	0
T7	8323	0	0	0
T8	1841	99	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	98	0	0
T40	0	14	0	0
T42	0	54	0	0
T43	0	224	0	0
T44	0	65	0	0
T58	815	0	0	0
T59	0	27	0	0
T60	0	186	0	0
T62	0	22	0	0
T63	438	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096177	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	10	0	0
T42	6381	0	0	0
T60	1543	2	0	0
T61	8114	0	0	0
T86	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T124	0	2	0	0
T125	0	2	0	0
T126	523	0	0	0
T127	503	0	0	0
T128	428	0	0	0
T129	4915	0	0	0
T130	453	0	0	0
T131	422	0	0	0
T132	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	22582	0	0
T8	1841	301	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	10	0	0
T29	522	0	0	0
T44	0	55	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	16	0	0
T62	0	6	0	0
T63	438	0	0	0
T77	0	397	0	0
T85	0	72	0	0
T120	0	75	0	0
T121	0	395	0	0
T122	0	31	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	41	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	1	0	0
T29	522	0	0	0
T44	0	1	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	438	0	0	0
T77	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6174213	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6176512	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	107	0	0
T3	2496	6	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	51	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	1	0	0
T29	522	0	0	0
T44	0	1	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	41	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	1	0	0
T29	522	0	0	0
T44	0	1	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	438	0	0	0
T77	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	41	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	1	0	0
T29	522	0	0	0
T44	0	1	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T63	438	0	0	0
T77	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	22541	0	0
T8	1841	300	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	9	0	0
T29	522	0	0	0
T44	0	54	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	15	0	0
T62	0	5	0	0
T63	438	0	0	0
T77	0	396	0	0
T85	0	71	0	0
T120	0	74	0	0
T121	0	393	0	0
T122	0	30	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6730	0	0
T1	12854	32	0	0
T2	737	1	0	0
T3	0	11	0	0
T4	7402	20	0	0
T5	1645	4	0	0
T6	505	5	0	0
T14	494	0	0	0
T17	0	5	0	0
T20	424	1	0	0
T21	422	6	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	396220	0	0
T8	1841	61	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T27	0	73	0	0
T29	522	0	0	0
T44	0	30	0	0
T47	4272	0	0	0
T58	815	0	0	0
T59	0	32	0	0
T62	0	117	0	0
T63	438	0	0	0
T77	0	96	0	0
T85	0	361850	0	0
T120	0	206	0	0
T121	0	139	0	0
T122	0	65	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T27
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T59
0	1	Covered	T3,T43,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T59
0	1	Unreachable
1	0	Covered	T3,T8,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T27
DetectSt	168	Covered	T3,T8,T59
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T59
DebounceSt->IdleSt	163	Covered	T27,T40,T42
DetectSt->IdleSt	186	Covered	T3,T43,T85
DetectSt->StableSt	191	Covered	T3,T8,T59
IdleSt->DebounceSt	148	Covered	T3,T8,T27
StableSt->IdleSt	206	Covered	T3,T8,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T27
0	1	Covered	T3,T8,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T59
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T43,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	1	-	-	Covered	T3,T43,T85
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T59
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	184	0	0
CntIncr_A	7718931	32552	0	0
CntNoWrap_A	7718931	7096149	0	0
DetectStDropOut_A	7718931	23	0	0
DetectedOut_A	7718931	15560	0	0
DetectedPulseOut_A	7718931	48	0	0
DisabledIdleSt_A	7718931	6174213	0	0
DisabledNoDetection_A	7718931	6176512	0	0
EnterDebounceSt_A	7718931	115	0	0
EnterDetectSt_A	7718931	71	0	0
EnterStableSt_A	7718931	48	0	0
PulseIsPulse_A	7718931	48	0	0
StayInStableSt	7718931	15512	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_sticky_sva.StableStDropOut_A	7718931	584916	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	184	0	0
T3	2496	6	0	0
T7	8323	0	0	0
T8	1841	2	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	7	0	0
T44	0	2	0	0
T58	815	0	0	0
T59	0	2	0	0
T60	0	4	0	0
T62	0	2	0	0
T63	438	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	32552	0	0
T3	2496	243	0	0
T7	8323	0	0	0
T8	1841	31	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	19	0	0
T40	0	14	0	0
T42	0	52	0	0
T43	0	368	0	0
T44	0	43	0	0
T58	815	0	0	0
T59	0	55	0	0
T60	0	196	0	0
T62	0	82	0	0
T63	438	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096149	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	23	0	0
T3	2496	1	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T43	0	3	0	0
T58	815	0	0	0
T63	438	0	0	0
T85	0	1	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	3	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	15560	0	0
T3	2496	247	0	0
T7	8323	0	0	0
T8	1841	203	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	12	0	0
T60	0	85	0	0
T62	0	32	0	0
T63	438	0	0	0
T85	0	87	0	0
T120	0	181	0	0
T121	0	334	0	0
T122	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	48	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6174213	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6176512	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	115	0	0
T3	2496	3	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	71	0	0
T3	2496	3	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	48	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	48	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	15512	0	0
T3	2496	245	0	0
T7	8323	0	0	0
T8	1841	202	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T58	815	0	0	0
T59	0	11	0	0
T60	0	83	0	0
T62	0	31	0	0
T63	438	0	0	0
T77	0	245	0	0
T85	0	86	0	0
T120	0	180	0	0
T121	0	332	0	0
T122	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	584916	0	0
T3	2496	518	0	0
T7	8323	0	0	0
T8	1841	242	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T44	0	116	0	0
T58	815	0	0	0
T59	0	28	0	0
T60	0	68	0	0
T62	0	32	0	0
T63	438	0	0	0
T85	0	144604	0	0
T120	0	63	0	0
T121	0	194	0	0
T122	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T27
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T27
0	1	Covered	T8,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T27
0	1	Unreachable
1	0	Covered	T3,T8,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T27
DetectSt	168	Covered	T3,T8,T27
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T27
DebounceSt->IdleSt	163	Covered	T40,T59,T60
DetectSt->IdleSt	186	Covered	T8,T81,T82
DetectSt->StableSt	191	Covered	T3,T8,T27
IdleSt->DebounceSt	148	Covered	T3,T8,T27
StableSt->IdleSt	206	Covered	T3,T8,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T27
0	1	Covered	T3,T8,T27
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T27
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T60,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	1	-	-	Covered	T8,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T27
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	151	0	0
CntIncr_A	7718931	154003	0	0
CntNoWrap_A	7718931	7096182	0	0
DetectStDropOut_A	7718931	7	0	0
DetectedOut_A	7718931	321921	0	0
DetectedPulseOut_A	7718931	43	0	0
DisabledIdleSt_A	7718931	6174213	0	0
DisabledNoDetection_A	7718931	6176512	0	0
EnterDebounceSt_A	7718931	103	0	0
EnterDetectSt_A	7718931	50	0	0
EnterStableSt_A	7718931	43	0	0
PulseIsPulse_A	7718931	43	0	0
StayInStableSt	7718931	321878	0	0
gen_high_event_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_sticky_sva.StableStDropOut_A	7718931	148385	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	151	0	0
T3	2496	4	0	0
T7	8323	0	0	0
T8	1841	6	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	2	0	0
T63	438	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	154003	0	0
T3	2496	192	0	0
T7	8323	0	0	0
T8	1841	216	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	89	0	0
T40	0	17	0	0
T42	0	55	0	0
T43	0	30	0	0
T44	0	21	0	0
T58	815	0	0	0
T59	0	13	0	0
T60	0	68	0	0
T62	0	12	0	0
T63	438	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096182	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7	0	0
T8	1841	2	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T47	4272	0	0	0
T58	815	0	0	0
T63	438	0	0	0
T81	0	2	0	0
T82	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	321921	0	0
T3	2496	660	0	0
T7	8323	0	0	0
T8	1841	75	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	77	0	0
T43	0	207	0	0
T44	0	2	0	0
T58	815	0	0	0
T62	0	3	0	0
T63	438	0	0	0
T85	0	309670	0	0
T120	0	166	0	0
T121	0	302	0	0
T122	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	43	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T58	815	0	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6174213	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6176512	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	103	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	3	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T58	815	0	0	0
T59	0	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T63	438	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	50	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	3	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T58	815	0	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	43	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T58	815	0	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	43	0	0
T3	2496	2	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T58	815	0	0	0
T62	0	1	0	0
T63	438	0	0	0
T85	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	321878	0	0
T3	2496	658	0	0
T7	8323	0	0	0
T8	1841	74	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	76	0	0
T43	0	206	0	0
T44	0	1	0	0
T58	815	0	0	0
T62	0	2	0	0
T63	438	0	0	0
T85	0	309668	0	0
T120	0	165	0	0
T121	0	300	0	0
T122	0	7	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	148385	0	0
T3	2496	271	0	0
T7	8323	0	0	0
T8	1841	99	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T19	494	0	0	0
T27	0	24	0	0
T43	0	345	0	0
T44	0	146	0	0
T58	815	0	0	0
T62	0	148	0	0
T63	438	0	0	0
T85	0	257	0	0
T120	0	91	0	0
T121	0	245	0	0
T122	0	145	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T40,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T40,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T40,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T13,T40,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T42
0	1	Covered	T43,T44,T142
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T40,T42
1	-	Covered	T43,T44,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T40,T42
DetectSt	168	Covered	T13,T40,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T40,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T40,T42
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T40,T42
IdleSt->DebounceSt	148	Covered	T13,T40,T42
StableSt->IdleSt	206	Covered	T40,T42,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T40,T42
0	1	Covered	T13,T40,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T40,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T40,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T40,T42
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T40,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T40,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T13,T40,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	60	0	0
CntIncr_A	7718931	1679	0	0
CntNoWrap_A	7718931	7096273	0	0
DetectStDropOut_A	7718931	0	0	0
DetectedOut_A	7718931	1835	0	0
DetectedPulseOut_A	7718931	30	0	0
DisabledIdleSt_A	7718931	7022478	0	0
DisabledNoDetection_A	7718931	7024735	0	0
EnterDebounceSt_A	7718931	30	0	0
EnterDetectSt_A	7718931	30	0	0
EnterStableSt_A	7718931	30	0	0
PulseIsPulse_A	7718931	30	0	0
StayInStableSt	7718931	1788	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	60	0	0
T13	647	2	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	6	0	0
T44	0	4	0	0
T47	4272	0	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	2	0	0
T142	0	4	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1679	0	0
T13	647	43	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	246	0	0
T44	0	99	0	0
T47	4272	0	0	0
T49	0	22	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	76	0	0
T142	0	76	0	0
T143	0	28	0	0
T144	0	72	0	0
T145	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096273	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1835	0	0
T13	647	43	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	11	0	0
T42	0	6	0	0
T43	0	134	0	0
T44	0	136	0	0
T47	4272	0	0	0
T49	0	41	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	41	0	0
T142	0	86	0	0
T143	0	41	0	0
T144	0	37	0	0
T145	425	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	30	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T47	4272	0	0	0
T49	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	425	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7022478	0	0
T1	12854	12447	0	0
T2	737	3	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7024735	0	0
T1	12854	12451	0	0
T2	737	3	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	30	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T47	4272	0	0	0
T49	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	30	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T47	4272	0	0	0
T49	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	425	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	30	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T47	4272	0	0	0
T49	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	425	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	30	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T47	4272	0	0	0
T49	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	425	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1788	0	0
T13	647	41	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	10	0	0
T42	0	5	0	0
T43	0	130	0	0
T44	0	133	0	0
T47	4272	0	0	0
T49	0	39	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	39	0	0
T142	0	83	0	0
T143	0	39	0	0
T144	0	35	0	0
T145	425	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	11	0	0
T43	114339	2	0	0
T44	15103	1	0	0
T94	37287	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	529	0	0	0
T153	403	0	0	0
T154	497	0	0	0
T155	495	0	0	0
T156	402	0	0	0
T157	504	0	0	0
T158	14747	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T47,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T47,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T47,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T47,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T47,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T47,T40
0	1	Covered	T76,T159
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T47,T40
0	1	Covered	T47,T48,T43
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T47,T40
1	-	Covered	T47,T48,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T47,T40
DetectSt	168	Covered	T8,T47,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T47,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T47,T40
DebounceSt->IdleSt	163	Covered	T43,T160,T161
DetectSt->IdleSt	186	Covered	T76,T159
DetectSt->StableSt	191	Covered	T8,T47,T40
IdleSt->DebounceSt	148	Covered	T8,T47,T40
StableSt->IdleSt	206	Covered	T47,T40,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T47,T40
0	1	Covered	T8,T47,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T47,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T47,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T47,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T160,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T47,T40
DetectSt	-	-	-	-	1	-	-	Covered	T76,T159
DetectSt	-	-	-	-	0	1	-	Covered	T8,T47,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T40,T48
StableSt	-	-	-	-	-	-	0	Covered	T8,T47,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	107	0	0
CntIncr_A	7718931	3943	0	0
CntNoWrap_A	7718931	7096226	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	3827	0	0
DetectedPulseOut_A	7718931	49	0	0
DisabledIdleSt_A	7718931	7080724	0	0
DisabledNoDetection_A	7718931	7082982	0	0
EnterDebounceSt_A	7718931	57	0	0
EnterDetectSt_A	7718931	51	0	0
EnterStableSt_A	7718931	49	0	0
PulseIsPulse_A	7718931	49	0	0
StayInStableSt	7718931	3760	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	2537	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	107	0	0
T8	1841	2	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	5	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	4	0	0
T48	0	2	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	4	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3943	0	0
T8	1841	22	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	246	0	0
T45	0	75	0	0
T46	0	52	0	0
T47	4272	108	0	0
T48	0	95	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	76	0	0
T162	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096226	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T76	604	1	0	0
T122	770	0	0	0
T143	176308	0	0	0
T144	2243	0	0	0
T159	0	1	0	0
T163	495	0	0	0
T164	560	0	0	0
T165	675	0	0	0
T166	497	0	0	0
T167	38576	0	0	0
T168	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3827	0	0
T8	1841	54	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	12	0	0
T42	0	6	0	0
T43	0	41	0	0
T45	0	51	0	0
T46	0	44	0	0
T47	4272	81	0	0
T48	0	137	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	39	0	0
T162	0	277	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	49	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	2	0	0
T48	0	1	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	2	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7080724	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7082982	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	57	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	2	0	0
T48	0	1	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	2	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	51	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	2	0	0
T48	0	1	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	2	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	49	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	2	0	0
T48	0	1	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	2	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	49	0	0
T8	1841	1	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	2	0	0
T48	0	1	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	2	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3760	0	0
T8	1841	52	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	11	0	0
T42	0	5	0	0
T43	0	39	0	0
T45	0	49	0	0
T46	0	42	0	0
T47	4272	78	0	0
T48	0	136	0	0
T58	815	0	0	0
T63	438	0	0	0
T142	0	37	0	0
T162	0	275	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2537	0	0
T1	12854	0	0	0
T2	737	1	0	0
T4	7402	16	0	0
T5	1645	4	0	0
T6	505	5	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	494	0	0	0
T17	0	4	0	0
T19	0	5	0	0
T20	424	0	0	0
T21	422	3	0	0
T22	410	0	0	0
T23	405	0	0	0
T63	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	29	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T43	0	2	0	0
T47	4272	1	0	0
T48	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T96	0	2	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	425	0	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	2	0	0
T172	422	0	0	0
T173	422	0	0	0