Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T40,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T40,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T40,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T13,T40,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T45
0	1	Covered	T83,T174
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T45
0	1	Covered	T13,T45,T43
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T40,T45
1	-	Covered	T13,T45,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T40,T45
DetectSt	168	Covered	T13,T40,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T40,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T40,T45
DebounceSt->IdleSt	163	Covered	T175,T176,T177
DetectSt->IdleSt	186	Covered	T83,T174
DetectSt->StableSt	191	Covered	T13,T40,T45
IdleSt->DebounceSt	148	Covered	T13,T40,T45
StableSt->IdleSt	206	Covered	T13,T40,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T40,T45
0	1	Covered	T13,T40,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T40,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T40,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T40,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T175,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T40,T45
DetectSt	-	-	-	-	1	-	-	Covered	T83,T174
DetectSt	-	-	-	-	0	1	-	Covered	T13,T40,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T13,T40,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	70	0	0
CntIncr_A	7718931	1984	0	0
CntNoWrap_A	7718931	7096263	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	2182	0	0
DetectedPulseOut_A	7718931	32	0	0
DisabledIdleSt_A	7718931	7079511	0	0
DisabledNoDetection_A	7718931	7081765	0	0
EnterDebounceSt_A	7718931	37	0	0
EnterDetectSt_A	7718931	34	0	0
EnterStableSt_A	7718931	32	0	0
PulseIsPulse_A	7718931	32	0	0
StayInStableSt	7718931	2135	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	70	0	0
T13	647	2	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	6	0	0
T44	0	2	0	0
T45	0	4	0	0
T47	4272	0	0	0
T50	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	4	0	0
T145	425	0	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1984	0	0
T13	647	43	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	17	0	0
T41	0	66	0	0
T42	0	16	0	0
T43	0	174	0	0
T44	0	96	0	0
T45	0	124	0	0
T47	4272	0	0	0
T50	0	90	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	90	0	0
T145	425	0	0	0
T178	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096263	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T83	10794	1	0	0
T111	27655	0	0	0
T112	35366	0	0	0
T113	441	0	0	0
T114	617	0	0	0
T115	658	0	0	0
T147	789	0	0	0
T174	0	1	0	0
T179	14045	0	0	0
T180	5227	0	0	0
T181	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2182	0	0
T13	647	104	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	10	0	0
T41	0	46	0	0
T42	0	5	0	0
T43	0	142	0	0
T44	0	91	0	0
T45	0	77	0	0
T47	4272	0	0	0
T50	0	39	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	143	0	0
T145	425	0	0	0
T178	0	231	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	32	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	4272	0	0	0
T50	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7079511	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7081765	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	37	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	4272	0	0	0
T50	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	34	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	4272	0	0	0
T50	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	32	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	4272	0	0	0
T50	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	32	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	4272	0	0	0
T50	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2135	0	0
T13	647	103	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	9	0	0
T41	0	44	0	0
T42	0	4	0	0
T43	0	137	0	0
T44	0	90	0	0
T45	0	74	0	0
T47	4272	0	0	0
T50	0	37	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	140	0	0
T145	425	0	0	0
T178	0	230	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	15	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	4272	0	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T145	425	0	0	0
T147	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T13,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T13,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T40
0	1	Covered	T77,T183
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T40
0	1	Covered	T45,T41,T43
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T40
1	-	Covered	T45,T41,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T13,T40
DetectSt	168	Covered	T9,T13,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T40
DebounceSt->IdleSt	163	Covered	T13,T43,T178
DetectSt->IdleSt	186	Covered	T77,T183
DetectSt->StableSt	191	Covered	T9,T13,T40
IdleSt->DebounceSt	148	Covered	T9,T13,T40
StableSt->IdleSt	206	Covered	T40,T45,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T13,T40
0	1	Covered	T9,T13,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T13,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T43,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T13,T40
DetectSt	-	-	-	-	1	-	-	Covered	T77,T183
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T45,T41
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	137	0	0
CntIncr_A	7718931	4240	0	0
CntNoWrap_A	7718931	7096196	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	6414	0	0
DetectedPulseOut_A	7718931	63	0	0
DisabledIdleSt_A	7718931	7017632	0	0
DisabledNoDetection_A	7718931	7019879	0	0
EnterDebounceSt_A	7718931	72	0	0
EnterDetectSt_A	7718931	65	0	0
EnterStableSt_A	7718931	63	0	0
PulseIsPulse_A	7718931	63	0	0
StayInStableSt	7718931	6323	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	2876	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	137	0	0
T9	783	2	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	3	0	0
T29	522	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	4272	0	0	0
T49	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	4240	0	0
T9	783	63	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	86	0	0
T29	522	0	0	0
T40	0	17	0	0
T41	0	66	0	0
T42	0	16	0	0
T43	0	164	0	0
T45	0	124	0	0
T46	0	52	0	0
T47	4272	0	0	0
T49	0	22	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096196	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T77	70715	1	0	0
T183	0	1	0	0
T185	524	0	0	0
T186	741	0	0	0
T187	502	0	0	0
T188	12245	0	0	0
T189	287074	0	0	0
T190	22999	0	0	0
T191	36157	0	0	0
T192	1333	0	0	0
T193	1462	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6414	0	0
T9	783	311	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	43	0	0
T29	522	0	0	0
T40	0	10	0	0
T41	0	39	0	0
T42	0	6	0	0
T43	0	250	0	0
T45	0	113	0	0
T46	0	193	0	0
T47	4272	0	0	0
T49	0	52	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	63	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	4272	0	0	0
T49	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7017632	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7019879	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	72	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	2	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	4272	0	0	0
T49	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	65	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	4272	0	0	0
T49	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	63	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	4272	0	0	0
T49	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	63	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	4272	0	0	0
T49	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6323	0	0
T9	783	309	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	41	0	0
T29	522	0	0	0
T40	0	9	0	0
T41	0	38	0	0
T42	0	5	0	0
T43	0	249	0	0
T45	0	111	0	0
T46	0	191	0	0
T47	4272	0	0	0
T49	0	50	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0
T184	0	59	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2876	0	0
T1	12854	0	0	0
T2	737	1	0	0
T4	7402	16	0	0
T5	1645	3	0	0
T6	505	6	0	0
T14	494	2	0	0
T17	0	2	0	0
T19	0	5	0	0
T20	424	2	0	0
T21	422	2	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	33	0	0
T41	0	1	0	0
T43	0	1	0	0
T45	8461	2	0	0
T50	681	0	0	0
T59	974	0	0	0
T77	0	1	0	0
T91	28943	0	0	0
T119	20797	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T162	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	522	0	0	0
T197	418	0	0	0
T198	965	0	0	0
T199	502	0	0	0
T200	443	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T8,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Covered	T201,T202
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Covered	T13,T47,T184
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T13
1	-	Covered	T13,T47,T184

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T13
DetectSt	168	Covered	T2,T8,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T13
DebounceSt->IdleSt	163	Covered	T49,T142,T182
DetectSt->IdleSt	186	Covered	T201,T202
DetectSt->StableSt	191	Covered	T2,T8,T13
IdleSt->DebounceSt	148	Covered	T2,T8,T13
StableSt->IdleSt	206	Covered	T13,T47,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T13
0	1	Covered	T2,T8,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T142,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	1	-	-	Covered	T201,T202
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T47,T40
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	127	0	0
CntIncr_A	7718931	3881	0	0
CntNoWrap_A	7718931	7096206	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	5280	0	0
DetectedPulseOut_A	7718931	58	0	0
DisabledIdleSt_A	7718931	7077674	0	0
DisabledNoDetection_A	7718931	7079926	0	0
EnterDebounceSt_A	7718931	67	0	0
EnterDetectSt_A	7718931	60	0	0
EnterStableSt_A	7718931	58	0	0
PulseIsPulse_A	7718931	58	0	0
StayInStableSt	7718931	5200	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	127	0	0
T2	737	2	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	2	0	0
T13	0	2	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T47	0	4	0	0
T49	0	5	0	0
T58	815	0	0	0
T142	0	5	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3881	0	0
T2	737	53	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	22	0	0
T13	0	43	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T44	0	192	0	0
T47	0	108	0	0
T49	0	66	0	0
T58	815	0	0	0
T142	0	114	0	0
T184	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096206	0	0
T1	12854	12447	0	0
T2	737	334	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T201	17527	1	0	0
T202	0	1	0	0
T203	1050	0	0	0
T204	908	0	0	0
T205	428	0	0	0
T206	15938	0	0	0
T207	435	0	0	0
T208	421	0	0	0
T209	567	0	0	0
T210	942	0	0	0
T211	513	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	5280	0	0
T2	737	99	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	54	0	0
T13	0	103	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	10	0	0
T42	0	5	0	0
T44	0	228	0	0
T47	0	53	0	0
T49	0	33	0	0
T58	815	0	0	0
T142	0	122	0	0
T184	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	58	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T58	815	0	0	0
T142	0	2	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7077674	0	0
T1	12854	12447	0	0
T2	737	3	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7079926	0	0
T1	12854	12451	0	0
T2	737	3	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	67	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	3	0	0
T58	815	0	0	0
T142	0	3	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	60	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T58	815	0	0	0
T142	0	2	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	58	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T58	815	0	0	0
T142	0	2	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	58	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	1	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T58	815	0	0	0
T142	0	2	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	5200	0	0
T2	737	97	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	52	0	0
T13	0	102	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	9	0	0
T42	0	4	0	0
T44	0	226	0	0
T47	0	50	0	0
T49	0	31	0	0
T58	815	0	0	0
T142	0	119	0	0
T184	0	29	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	34	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T44	0	2	0	0
T47	4272	1	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T83	0	2	0	0
T85	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T145	425	0	0	0
T146	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T40,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T13,T40,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T40,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T13,T40,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T48
0	1	Covered	T48,T49,T43
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T40,T48
1	-	Covered	T48,T49,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T40,T48
DetectSt	168	Covered	T13,T40,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T40,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T40,T48
DebounceSt->IdleSt	163	Covered	T175
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T40,T48
IdleSt->DebounceSt	148	Covered	T13,T40,T48
StableSt->IdleSt	206	Covered	T40,T48,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T40,T48
0	1	Covered	T13,T40,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T40,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T40,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T40,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T175
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T40,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T40,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T48,T42
StableSt	-	-	-	-	-	-	0	Covered	T13,T40,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	85	0	0
CntIncr_A	7718931	2362	0	0
CntNoWrap_A	7718931	7096248	0	0
DetectStDropOut_A	7718931	0	0	0
DetectedOut_A	7718931	2682	0	0
DetectedPulseOut_A	7718931	42	0	0
DisabledIdleSt_A	7718931	7020085	0	0
DisabledNoDetection_A	7718931	7022336	0	0
EnterDebounceSt_A	7718931	43	0	0
EnterDetectSt_A	7718931	42	0	0
EnterStableSt_A	7718931	42	0	0
PulseIsPulse_A	7718931	42	0	0
StayInStableSt	7718931	2622	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6478	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	85	0	0
T13	647	2	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T47	4272	0	0	0
T48	0	2	0	0
T49	0	6	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	4	0	0
T142	0	4	0	0
T145	425	0	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2362	0	0
T13	647	43	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	10	0	0
T44	0	192	0	0
T47	4272	0	0	0
T48	0	95	0	0
T49	0	66	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	68	0	0
T142	0	76	0	0
T145	425	0	0	0
T178	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096248	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2682	0	0
T13	647	44	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	12	0	0
T42	0	4	0	0
T43	0	40	0	0
T44	0	133	0	0
T47	4272	0	0	0
T48	0	245	0	0
T49	0	125	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	91	0	0
T142	0	85	0	0
T145	425	0	0	0
T178	0	93	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	42	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	0	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7020085	0	0
T1	12854	12447	0	0
T2	737	3	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7022336	0	0
T1	12854	12451	0	0
T2	737	3	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	43	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	0	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	42	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	0	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	42	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	0	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	42	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	0	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2622	0	0
T13	647	42	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	11	0	0
T42	0	3	0	0
T43	0	39	0	0
T44	0	130	0	0
T47	4272	0	0	0
T48	0	244	0	0
T49	0	121	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T77	0	88	0	0
T142	0	83	0	0
T145	425	0	0	0
T178	0	92	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6478	0	0
T1	12854	30	0	0
T2	737	0	0	0
T3	0	11	0	0
T4	7402	18	0	0
T5	1645	3	0	0
T6	505	4	0	0
T7	0	30	0	0
T14	494	0	0	0
T17	0	7	0	0
T19	0	10	0	0
T20	424	3	0	0
T21	422	1	0	0
T22	410	0	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	22	0	0
T39	9014	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	8461	0	0	0
T48	1068	1	0	0
T49	0	2	0	0
T50	681	0	0	0
T59	974	0	0	0
T77	0	1	0	0
T91	28943	0	0	0
T142	0	2	0	0
T148	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T196	522	0	0	0
T197	418	0	0	0
T198	965	0	0	0
T199	502	0	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T13,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T13,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T47
0	1	Covered	T149,T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T47
0	1	Covered	T13,T47,T45
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T47
1	-	Covered	T13,T47,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T13,T47
DetectSt	168	Covered	T9,T13,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T47
DebounceSt->IdleSt	163	Covered	T142,T213,T214
DetectSt->IdleSt	186	Covered	T149,T201
DetectSt->StableSt	191	Covered	T9,T13,T47
IdleSt->DebounceSt	148	Covered	T9,T13,T47
StableSt->IdleSt	206	Covered	T13,T47,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T13,T47
0	1	Covered	T9,T13,T47
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T13,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T214,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T13,T47
DetectSt	-	-	-	-	1	-	-	Covered	T149,T201
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T47,T40
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	162	0	0
CntIncr_A	7718931	6066	0	0
CntNoWrap_A	7718931	7096171	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	6453	0	0
DetectedPulseOut_A	7718931	76	0	0
DisabledIdleSt_A	7718931	7014924	0	0
DisabledNoDetection_A	7718931	7017160	0	0
EnterDebounceSt_A	7718931	86	0	0
EnterDetectSt_A	7718931	78	0	0
EnterStableSt_A	7718931	76	0	0
PulseIsPulse_A	7718931	76	0	0
StayInStableSt	7718931	6348	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	162	0	0
T9	783	2	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	2	0	0
T29	522	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T46	0	4	0	0
T47	4272	2	0	0
T49	0	6	0	0
T50	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6066	0	0
T9	783	63	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	43	0	0
T29	522	0	0	0
T40	0	17	0	0
T41	0	66	0	0
T42	0	16	0	0
T45	0	137	0	0
T46	0	104	0	0
T47	4272	54	0	0
T49	0	66	0	0
T50	0	90	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096171	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T149	3297	1	0	0
T201	0	1	0	0
T215	11629	0	0	0
T216	1354	0	0	0
T217	14132	0	0	0
T218	741	0	0	0
T219	16793	0	0	0
T220	503	0	0	0
T221	770	0	0	0
T222	36556	0	0	0
T223	696	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6453	0	0
T9	783	149	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	20	0	0
T29	522	0	0	0
T40	0	12	0	0
T41	0	153	0	0
T42	0	5	0	0
T45	0	331	0	0
T46	0	120	0	0
T47	4272	171	0	0
T49	0	171	0	0
T50	0	52	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	76	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7014924	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7017160	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	86	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	78	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	76	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	76	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	1	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6348	0	0
T9	783	147	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	19	0	0
T29	522	0	0	0
T40	0	11	0	0
T41	0	151	0	0
T42	0	4	0	0
T45	0	328	0	0
T46	0	117	0	0
T47	4272	170	0	0
T49	0	167	0	0
T50	0	51	0	0
T63	438	0	0	0
T67	524	0	0	0
T145	425	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	45	0	0
T13	647	1	0	0
T29	522	0	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	1	0	0
T142	0	1	0	0
T145	425	0	0	0
T162	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T13,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T13,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T13,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T13,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T40
0	1	Covered	T2,T48,T46
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T40
1	-	Covered	T2,T48,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T40
DetectSt	168	Covered	T2,T13,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T13,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T40
DebounceSt->IdleSt	163	Covered	T195
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T13,T40
IdleSt->DebounceSt	148	Covered	T2,T13,T40
StableSt->IdleSt	206	Covered	T2,T40,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T40
0	1	Covered	T2,T13,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T195
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	77	0	0
CntIncr_A	7718931	2334	0	0
CntNoWrap_A	7718931	7096256	0	0
DetectStDropOut_A	7718931	0	0	0
DetectedOut_A	7718931	2639	0	0
DetectedPulseOut_A	7718931	38	0	0
DisabledIdleSt_A	7718931	7018477	0	0
DisabledNoDetection_A	7718931	7020724	0	0
EnterDebounceSt_A	7718931	39	0	0
EnterDetectSt_A	7718931	38	0	0
EnterStableSt_A	7718931	38	0	0
PulseIsPulse_A	7718931	38	0	0
StayInStableSt	7718931	2583	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6026	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	77	0	0
T2	737	2	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	2	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T58	815	0	0	0
T142	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2334	0	0
T2	737	53	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	43	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T44	0	96	0	0
T45	0	62	0	0
T46	0	52	0	0
T48	0	95	0	0
T50	0	90	0	0
T58	815	0	0	0
T142	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096256	0	0
T1	12854	12447	0	0
T2	737	334	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2639	0	0
T2	737	9	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	44	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	11	0	0
T42	0	5	0	0
T44	0	40	0	0
T45	0	37	0	0
T46	0	42	0	0
T48	0	94	0	0
T50	0	38	0	0
T58	815	0	0	0
T142	0	213	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T58	815	0	0	0
T142	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7018477	0	0
T1	12854	12447	0	0
T2	737	3	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7020724	0	0
T1	12854	12451	0	0
T2	737	3	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	39	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T58	815	0	0	0
T142	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T58	815	0	0	0
T142	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T58	815	0	0	0
T142	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	1	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T58	815	0	0	0
T142	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2583	0	0
T2	737	8	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T13	0	42	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	10	0	0
T42	0	4	0	0
T44	0	38	0	0
T45	0	35	0	0
T46	0	41	0	0
T48	0	93	0	0
T50	0	36	0	0
T58	815	0	0	0
T142	0	210	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6026	0	0
T1	12854	25	0	0
T2	737	1	0	0
T4	7402	17	0	0
T5	1645	1	0	0
T6	505	3	0	0
T7	0	32	0	0
T14	494	0	0	0
T17	0	6	0	0
T20	424	1	0	0
T21	422	2	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	18	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T58	815	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T96	0	1	0	0
T142	0	1	0	0
T194	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0