Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T47,T40,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T47,T40,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T47,T40,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T47,T40,T48
1	0	Covered	T4,T5,T6
1	1	Covered	T47,T40,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T40,T48
0	1	Covered	T226,T141
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T40,T48
0	1	Covered	T47,T48,T44
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T40,T48
1	-	Covered	T47,T48,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T40,T48
DetectSt	168	Covered	T47,T40,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T47,T40,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T40,T48
DebounceSt->IdleSt	163	Covered	T178,T164,T227
DetectSt->IdleSt	186	Covered	T226,T141
DetectSt->StableSt	191	Covered	T47,T40,T48
IdleSt->DebounceSt	148	Covered	T47,T40,T48
StableSt->IdleSt	206	Covered	T47,T40,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T47,T40,T48
0	1	Covered	T47,T40,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T47,T40,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T40,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T40,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T164,T228
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T40,T48
DetectSt	-	-	-	-	1	-	-	Covered	T226,T141
DetectSt	-	-	-	-	0	1	-	Covered	T47,T40,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T40,T48
StableSt	-	-	-	-	-	-	0	Covered	T47,T40,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	129	0	0
CntIncr_A	7718931	53869	0	0
CntNoWrap_A	7718931	7096204	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	14013	0	0
DetectedPulseOut_A	7718931	61	0	0
DisabledIdleSt_A	7718931	7019650	0	0
DisabledNoDetection_A	7718931	7021906	0	0
EnterDebounceSt_A	7718931	67	0	0
EnterDetectSt_A	7718931	63	0	0
EnterStableSt_A	7718931	61	0	0
PulseIsPulse_A	7718931	61	0	0
StayInStableSt	7718931	13925	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	129	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T47	4272	2	0	0
T48	0	4	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	2	0	0
T85	0	4	0	0
T142	0	4	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	53869	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	49306	0	0
T44	0	142	0	0
T47	4272	54	0	0
T48	0	190	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	76	0	0
T85	0	90	0	0
T142	0	76	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096204	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T100	83895	0	0	0
T101	17392	0	0	0
T102	6531	0	0	0
T123	492	0	0	0
T141	0	1	0	0
T226	28906	1	0	0
T229	156767	0	0	0
T230	489	0	0	0
T231	491	0	0	0
T232	492	0	0	0
T233	959	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	14013	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	12	0	0
T42	0	6	0	0
T43	0	8875	0	0
T44	0	135	0	0
T47	4272	112	0	0
T48	0	276	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	119	0	0
T85	0	75	0	0
T142	0	131	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	61	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	1	0	0
T48	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T85	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7019650	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7021906	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	67	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	1	0	0
T48	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T85	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	63	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	1	0	0
T48	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T85	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	61	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	1	0	0
T48	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T85	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	61	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	4272	1	0	0
T48	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	1	0	0
T85	0	2	0	0
T142	0	2	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	13925	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	11	0	0
T42	0	5	0	0
T43	0	8873	0	0
T44	0	132	0	0
T47	4272	111	0	0
T48	0	273	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T76	0	117	0	0
T85	0	73	0	0
T142	0	128	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T178	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	32	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T44	0	1	0	0
T47	4272	1	0	0
T48	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T83	0	2	0	0
T85	0	2	0	0
T142	0	1	0	0
T145	425	0	0	0
T146	0	1	0	0
T147	0	2	0	0
T161	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0
T234	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T47,T40,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T47,T40,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T47,T40,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T47,T40,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T40,T48
0	1	Covered	T235
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T40,T48
0	1	Covered	T48,T49,T43
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T40,T48
1	-	Covered	T48,T49,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T40,T48
DetectSt	168	Covered	T47,T40,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T47,T40,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T40,T48
DebounceSt->IdleSt	163	Covered	T184,T161,T176
DetectSt->IdleSt	186	Covered	T235
DetectSt->StableSt	191	Covered	T47,T40,T48
IdleSt->DebounceSt	148	Covered	T47,T40,T48
StableSt->IdleSt	206	Covered	T47,T40,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T47,T40,T48
0	1	Covered	T47,T40,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T47,T40,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T40,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T40,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T184,T161,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T40,T48
DetectSt	-	-	-	-	1	-	-	Covered	T235
DetectSt	-	-	-	-	0	1	-	Covered	T47,T40,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T48,T42
StableSt	-	-	-	-	-	-	0	Covered	T47,T40,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	81	0	0
CntIncr_A	7718931	2171	0	0
CntNoWrap_A	7718931	7096252	0	0
DetectStDropOut_A	7718931	1	0	0
DetectedOut_A	7718931	2581	0	0
DetectedPulseOut_A	7718931	38	0	0
DisabledIdleSt_A	7718931	7077009	0	0
DisabledNoDetection_A	7718931	7079255	0	0
EnterDebounceSt_A	7718931	43	0	0
EnterDetectSt_A	7718931	39	0	0
EnterStableSt_A	7718931	38	0	0
PulseIsPulse_A	7718931	38	0	0
StayInStableSt	7718931	2528	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6130	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	81	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T47	4272	2	0	0
T48	0	2	0	0
T49	0	4	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	4	0	0
T142	0	2	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T184	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2171	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	10	0	0
T44	0	53	0	0
T47	4272	54	0	0
T48	0	95	0	0
T49	0	44	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	90	0	0
T142	0	38	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T184	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096252	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1	0	0
T125	9984	0	0	0
T141	6422	0	0	0
T235	877	1	0	0
T236	505	0	0	0
T237	6950	0	0	0
T238	26807	0	0	0
T239	13708	0	0	0
T240	16413	0	0	0
T241	871	0	0	0
T242	801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2581	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	10	0	0
T42	0	4	0	0
T43	0	70	0	0
T44	0	95	0	0
T47	4272	97	0	0
T48	0	95	0	0
T49	0	83	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	188	0	0
T142	0	114	0	0
T145	425	0	0	0
T162	0	52	0	0
T172	422	0	0	0
T173	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	4272	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T142	0	1	0	0
T145	425	0	0	0
T162	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7077009	0	0
T1	12854	12447	0	0
T2	737	3	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7079255	0	0
T1	12854	12451	0	0
T2	737	3	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	43	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	4272	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T142	0	1	0	0
T145	425	0	0	0
T172	422	0	0	0
T173	422	0	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	39	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	4272	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T142	0	1	0	0
T145	425	0	0	0
T162	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	4272	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T142	0	1	0	0
T145	425	0	0	0
T162	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	4272	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	2	0	0
T142	0	1	0	0
T145	425	0	0	0
T162	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2528	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	9	0	0
T42	0	3	0	0
T43	0	69	0	0
T44	0	93	0	0
T47	4272	95	0	0
T48	0	94	0	0
T49	0	80	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T85	0	185	0	0
T142	0	113	0	0
T145	425	0	0	0
T162	0	51	0	0
T172	422	0	0	0
T173	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6130	0	0
T1	12854	27	0	0
T2	737	0	0	0
T4	7402	16	0	0
T5	1645	2	0	0
T6	505	4	0	0
T7	0	31	0	0
T14	494	0	0	0
T17	0	8	0	0
T19	0	11	0	0
T20	424	3	0	0
T21	422	3	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	21	0	0
T39	9014	0	0	0
T43	0	1	0	0
T45	8461	0	0	0
T48	1068	1	0	0
T49	0	1	0	0
T50	681	0	0	0
T59	974	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T91	28943	0	0	0
T142	0	1	0	0
T147	0	2	0	0
T149	0	3	0	0
T162	0	1	0	0
T195	0	1	0	0
T196	522	0	0	0
T197	418	0	0	0
T198	965	0	0	0
T199	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T40,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T40,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T40,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T13,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T40,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T40,T45
0	1	Covered	T44
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T40,T45
0	1	Covered	T45,T46,T43
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T40,T45
1	-	Covered	T45,T46,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T40,T45
DetectSt	168	Covered	T9,T40,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T40,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T40,T45
DebounceSt->IdleSt	163	Covered	T43,T178,T149
DetectSt->IdleSt	186	Covered	T44
DetectSt->StableSt	191	Covered	T9,T40,T45
IdleSt->DebounceSt	148	Covered	T9,T40,T45
StableSt->IdleSt	206	Covered	T40,T45,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T40,T45
0	1	Covered	T9,T40,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T40,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T40,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T40,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T178,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T40,T45
DetectSt	-	-	-	-	1	-	-	Covered	T44
DetectSt	-	-	-	-	0	1	-	Covered	T9,T40,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T9,T40,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	137	0	0
CntIncr_A	7718931	53309	0	0
CntNoWrap_A	7718931	7096196	0	0
DetectStDropOut_A	7718931	1	0	0
DetectedOut_A	7718931	15012	0	0
DetectedPulseOut_A	7718931	65	0	0
DisabledIdleSt_A	7718931	7017962	0	0
DisabledNoDetection_A	7718931	7020206	0	0
EnterDebounceSt_A	7718931	71	0	0
EnterDetectSt_A	7718931	66	0	0
EnterStableSt_A	7718931	65	0	0
PulseIsPulse_A	7718931	65	0	0
StayInStableSt	7718931	14922	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	137	0	0
T9	783	2	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	7	0	0
T44	0	8	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	2	0	0
T145	425	0	0	0
T178	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	53309	0	0
T9	783	63	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	17	0	0
T41	0	66	0	0
T42	0	16	0	0
T43	0	49480	0	0
T44	0	198	0	0
T45	0	62	0	0
T46	0	52	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	43	0	0
T145	425	0	0	0
T178	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096196	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1	0	0
T44	15103	1	0	0
T116	776	0	0	0
T142	806	0	0	0
T156	402	0	0	0
T157	504	0	0	0
T158	14747	0	0	0
T243	423	0	0	0
T244	794	0	0	0
T245	24030	0	0	0
T246	514	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	15012	0	0
T9	783	42	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	11	0	0
T41	0	220	0	0
T42	0	4	0	0
T43	0	9020	0	0
T44	0	176	0	0
T45	0	139	0	0
T46	0	43	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	95	0	0
T145	425	0	0	0
T178	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	65	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	1	0	0
T145	425	0	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7017962	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7020206	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	71	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	1	0	0
T145	425	0	0	0
T178	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	66	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	1	0	0
T145	425	0	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	65	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	1	0	0
T145	425	0	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	65	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	1	0	0
T145	425	0	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	14922	0	0
T9	783	40	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	10	0	0
T41	0	218	0	0
T42	0	3	0	0
T43	0	9016	0	0
T44	0	171	0	0
T45	0	138	0	0
T46	0	42	0	0
T47	4272	0	0	0
T63	438	0	0	0
T67	524	0	0	0
T120	0	93	0	0
T145	425	0	0	0
T178	0	90	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	8461	1	0	0
T46	0	1	0	0
T50	681	0	0	0
T59	974	0	0	0
T83	0	2	0	0
T91	28943	0	0	0
T119	20797	0	0	0
T146	0	2	0	0
T162	0	1	0	0
T178	0	1	0	0
T194	0	1	0	0
T196	522	0	0	0
T197	418	0	0	0
T198	965	0	0	0
T199	502	0	0	0
T200	443	0	0	0
T247	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T40,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T40,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T40,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T40,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T45
0	1	Covered	T201,T177
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T45
0	1	Covered	T2,T43,T44
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T45
1	-	Covered	T2,T43,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T40,T45
DetectSt	168	Covered	T2,T40,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T40,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T40,T45
DebounceSt->IdleSt	163	Covered	T248
DetectSt->IdleSt	186	Covered	T201,T177
DetectSt->StableSt	191	Covered	T2,T40,T45
IdleSt->DebounceSt	148	Covered	T2,T40,T45
StableSt->IdleSt	206	Covered	T2,T40,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T40,T45
0	1	Covered	T2,T40,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T40,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T40,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T40,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T248
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T40,T45
DetectSt	-	-	-	-	1	-	-	Covered	T201,T177
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	77	0	0
CntIncr_A	7718931	2184	0	0
CntNoWrap_A	7718931	7096256	0	0
DetectStDropOut_A	7718931	2	0	0
DetectedOut_A	7718931	3194	0	0
DetectedPulseOut_A	7718931	36	0	0
DisabledIdleSt_A	7718931	7018303	0	0
DisabledNoDetection_A	7718931	7020550	0	0
EnterDebounceSt_A	7718931	39	0	0
EnterDetectSt_A	7718931	38	0	0
EnterStableSt_A	7718931	36	0	0
PulseIsPulse_A	7718931	36	0	0
StayInStableSt	7718931	3137	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6115	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	77	0	0
T2	737	2	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	2	0	0
T46	0	2	0	0
T58	815	0	0	0
T77	0	2	0	0
T142	0	4	0	0
T212	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2184	0	0
T2	737	53	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	164	0	0
T44	0	99	0	0
T45	0	62	0	0
T46	0	52	0	0
T58	815	0	0	0
T77	0	34	0	0
T142	0	76	0	0
T212	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096256	0	0
T1	12854	12447	0	0
T2	737	334	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2	0	0
T177	0	1	0	0
T201	17527	1	0	0
T203	1050	0	0	0
T204	908	0	0	0
T205	428	0	0	0
T206	15938	0	0	0
T207	435	0	0	0
T208	421	0	0	0
T209	567	0	0	0
T210	942	0	0	0
T211	513	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3194	0	0
T2	737	105	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	12	0	0
T42	0	5	0	0
T43	0	331	0	0
T44	0	48	0	0
T45	0	213	0	0
T46	0	97	0	0
T58	815	0	0	0
T77	0	75	0	0
T142	0	158	0	0
T212	0	304	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	36	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	815	0	0	0
T77	0	1	0	0
T142	0	2	0	0
T212	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7018303	0	0
T1	12854	12447	0	0
T2	737	3	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7020550	0	0
T1	12854	12451	0	0
T2	737	3	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	39	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	815	0	0	0
T77	0	1	0	0
T142	0	2	0	0
T212	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	38	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	815	0	0	0
T77	0	1	0	0
T142	0	2	0	0
T212	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	36	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	815	0	0	0
T77	0	1	0	0
T142	0	2	0	0
T212	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	36	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T58	815	0	0	0
T77	0	1	0	0
T142	0	2	0	0
T212	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3137	0	0
T2	737	104	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	11	0	0
T42	0	4	0	0
T43	0	328	0	0
T44	0	46	0	0
T45	0	211	0	0
T46	0	95	0	0
T58	815	0	0	0
T77	0	73	0	0
T142	0	156	0	0
T212	0	302	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6115	0	0
T1	12854	32	0	0
T2	737	1	0	0
T4	7402	15	0	0
T5	1645	5	0	0
T6	505	5	0	0
T7	0	29	0	0
T14	494	0	0	0
T17	0	7	0	0
T20	424	3	0	0
T21	422	2	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	13	0	0
T2	737	1	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T8	1841	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T58	815	0	0	0
T96	0	1	0	0
T142	0	2	0	0
T149	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T235	0	1	0	0
T249	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T47,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T47,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T47,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T47,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T47,T40
0	1	Covered	T84,T159,T250
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T47,T40
0	1	Covered	T47,T48,T45
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T47,T40
1	-	Covered	T47,T48,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T47,T40
DetectSt	168	Covered	T9,T47,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T47,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T47,T40
DebounceSt->IdleSt	163	Covered	T9,T182,T160
DetectSt->IdleSt	186	Covered	T84,T159,T250
DetectSt->StableSt	191	Covered	T9,T47,T40
IdleSt->DebounceSt	148	Covered	T9,T47,T40
StableSt->IdleSt	206	Covered	T47,T40,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T47,T40
0	1	Covered	T9,T47,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T47,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T47,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T47,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T182,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T47,T40
DetectSt	-	-	-	-	1	-	-	Covered	T84,T159,T250
DetectSt	-	-	-	-	0	1	-	Covered	T9,T47,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T40,T48
StableSt	-	-	-	-	-	-	0	Covered	T9,T47,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	155	0	0
CntIncr_A	7718931	53848	0	0
CntNoWrap_A	7718931	7096178	0	0
DetectStDropOut_A	7718931	3	0	0
DetectedOut_A	7718931	5663	0	0
DetectedPulseOut_A	7718931	71	0	0
DisabledIdleSt_A	7718931	7018583	0	0
DisabledNoDetection_A	7718931	7020830	0	0
EnterDebounceSt_A	7718931	81	0	0
EnterDetectSt_A	7718931	74	0	0
EnterStableSt_A	7718931	71	0	0
PulseIsPulse_A	7718931	71	0	0
StayInStableSt	7718931	5566	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	155	0	0
T9	783	3	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	6	0	0
T45	0	6	0	0
T47	4272	4	0	0
T48	0	4	0	0
T49	0	4	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	4	0	0
T145	425	0	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	53848	0	0
T9	783	126	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	17	0	0
T42	0	16	0	0
T43	0	49326	0	0
T45	0	199	0	0
T47	4272	108	0	0
T48	0	190	0	0
T49	0	44	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	76	0	0
T145	425	0	0	0
T184	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096178	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3	0	0
T84	46119	1	0	0
T149	3297	0	0	0
T159	0	1	0	0
T215	11629	0	0	0
T216	1354	0	0	0
T250	0	1	0	0
T251	502	0	0	0
T252	537	0	0	0
T253	35052	0	0	0
T254	450	0	0	0
T255	755	0	0	0
T256	431	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	5663	0	0
T9	783	150	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	11	0	0
T42	0	6	0	0
T43	0	237	0	0
T45	0	102	0	0
T47	4272	112	0	0
T48	0	288	0	0
T49	0	61	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	86	0	0
T145	425	0	0	0
T184	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	71	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	4272	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	2	0	0
T145	425	0	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7018583	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7020830	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	81	0	0
T9	783	2	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	4272	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	2	0	0
T145	425	0	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	74	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	4272	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	2	0	0
T145	425	0	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	71	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	4272	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	2	0	0
T145	425	0	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	71	0	0
T9	783	1	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	4272	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	2	0	0
T145	425	0	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	5566	0	0
T9	783	148	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T40	0	10	0	0
T42	0	5	0	0
T43	0	232	0	0
T45	0	98	0	0
T47	4272	109	0	0
T48	0	285	0	0
T49	0	58	0	0
T63	438	0	0	0
T67	524	0	0	0
T142	0	83	0	0
T145	425	0	0	0
T184	0	137	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	43	0	0
T30	699	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	4272	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	13910	0	0	0
T67	524	0	0	0
T68	502	0	0	0
T142	0	1	0	0
T145	425	0	0	0
T146	0	1	0	0
T169	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0
T184	0	1	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T40,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T40,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T40,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T40,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T43,T44,T142
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T41,T42
1	-	Covered	T43,T44,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T41,T42
DetectSt	168	Covered	T40,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T40,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T41,T42
DebounceSt->IdleSt	163	Covered	T85,T242
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T41,T42
IdleSt->DebounceSt	148	Covered	T40,T41,T42
StableSt->IdleSt	206	Covered	T40,T42,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T41,T42
0	1	Covered	T40,T41,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T41,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T40,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	94	0	0
CntIncr_A	7718931	2823	0	0
CntNoWrap_A	7718931	7096239	0	0
DetectStDropOut_A	7718931	0	0	0
DetectedOut_A	7718931	2805	0	0
DetectedPulseOut_A	7718931	46	0	0
DisabledIdleSt_A	7718931	7020861	0	0
DisabledNoDetection_A	7718931	7023112	0	0
EnterDebounceSt_A	7718931	48	0	0
EnterDetectSt_A	7718931	46	0	0
EnterStableSt_A	7718931	46	0	0
PulseIsPulse_A	7718931	46	0	0
StayInStableSt	7718931	2735	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7718931	6730	0	0
gen_low_level_sva.LowLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	94	0	0
T37	17173	0	0	0
T40	6625	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	6	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	3	0	0
T120	0	2	0	0
T142	0	2	0	0
T212	0	2	0	0
T234	0	6	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2823	0	0
T37	17173	0	0	0
T40	6625	17	0	0
T41	0	66	0	0
T42	0	16	0	0
T43	0	92	0	0
T44	0	238	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	90	0	0
T120	0	43	0	0
T142	0	38	0	0
T212	0	79	0	0
T234	0	162	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7096239	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2805	0	0
T37	17173	0	0	0
T40	6625	10	0	0
T41	0	153	0	0
T42	0	5	0	0
T43	0	50	0	0
T44	0	87	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	18	0	0
T120	0	39	0	0
T142	0	159	0	0
T212	0	38	0	0
T234	0	119	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	46	0	0
T37	17173	0	0	0
T40	6625	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0
T212	0	1	0	0
T234	0	3	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7020861	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7023112	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	48	0	0
T37	17173	0	0	0
T40	6625	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	2	0	0
T120	0	1	0	0
T142	0	1	0	0
T212	0	1	0	0
T234	0	3	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	46	0	0
T37	17173	0	0	0
T40	6625	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0
T212	0	1	0	0
T234	0	3	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	46	0	0
T37	17173	0	0	0
T40	6625	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0
T212	0	1	0	0
T234	0	3	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	46	0	0
T37	17173	0	0	0
T40	6625	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	1	0	0
T120	0	1	0	0
T142	0	1	0	0
T212	0	1	0	0
T234	0	3	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2735	0	0
T37	17173	0	0	0
T40	6625	9	0	0
T41	0	151	0	0
T42	0	4	0	0
T43	0	48	0	0
T44	0	83	0	0
T72	504	0	0	0
T73	6680	0	0	0
T74	23255	0	0	0
T75	15060	0	0	0
T85	0	17	0	0
T120	0	37	0	0
T142	0	158	0	0
T212	0	36	0	0
T234	0	115	0	0
T257	401	0	0	0
T258	674	0	0	0
T259	403	0	0	0
T260	523	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6730	0	0
T1	12854	32	0	0
T2	737	1	0	0
T3	0	11	0	0
T4	7402	20	0	0
T5	1645	4	0	0
T6	505	5	0	0
T14	494	0	0	0
T17	0	5	0	0
T20	424	1	0	0
T21	422	6	0	0
T22	410	1	0	0
T23	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	20	0	0
T43	114339	2	0	0
T44	15103	2	0	0
T85	0	1	0	0
T94	37287	0	0	0
T142	0	1	0	0
T152	529	0	0	0
T153	403	0	0	0
T154	497	0	0	0
T155	495	0	0	0
T156	402	0	0	0
T157	504	0	0	0
T158	14747	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0
T225	0	1	0	0
T234	0	2	0	0