Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T11
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T11,T52,T40
1	0	Covered	T11,T40,T91

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T12
1	-	Covered	T1,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T52,T40,T42
DetectSt->IdleSt	186	Covered	T11,T52,T40
DetectSt->StableSt	191	Covered	T1,T7,T12
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T1,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T7,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T40,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T52,T40
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	2861	0	0
CntIncr_A	7718931	95338	0	0
CntNoWrap_A	7718931	7093472	0	0
DetectStDropOut_A	7718931	332	0	0
DetectedOut_A	7718931	79361	0	0
DetectedPulseOut_A	7718931	919	0	0
DisabledIdleSt_A	7718931	6607997	0	0
DisabledNoDetection_A	7718931	6610110	0	0
EnterDebounceSt_A	7718931	1447	0	0
EnterDetectSt_A	7718931	1414	0	0
EnterStableSt_A	7718931	919	0	0
PulseIsPulse_A	7718931	919	0	0
StayInStableSt	7718931	78343	0	0
gen_high_event_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	819	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2861	0	0
T1	12854	46	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	2	0	0
T11	0	8	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	2	0	0
T37	0	26	0	0
T40	0	16	0	0
T52	0	11	0	0
T73	0	24	0	0
T74	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	95338	0	0
T1	12854	874	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	46	0	0
T11	0	269	0	0
T12	0	938	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	21	0	0
T37	0	715	0	0
T40	0	380	0	0
T52	0	430	0	0
T73	0	648	0	0
T74	0	483	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7093472	0	0
T1	12854	12401	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	332	0	0
T11	9572	2	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T47	4272	0	0	0
T52	0	1	0	0
T63	438	0	0	0
T67	524	0	0	0
T79	0	14	0	0
T90	0	27	0	0
T91	0	16	0	0
T129	0	14	0	0
T145	425	0	0	0
T261	0	1	0	0
T262	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	79361	0	0
T1	12854	960	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	41	0	0
T12	0	1242	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	83	0	0
T37	0	609	0	0
T40	0	297	0	0
T73	0	1352	0	0
T74	0	143	0	0
T75	0	1643	0	0
T88	0	1086	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	919	0	0
T1	12854	23	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T37	0	13	0	0
T40	0	5	0	0
T73	0	12	0	0
T74	0	7	0	0
T75	0	11	0	0
T88	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6607997	0	0
T1	12854	9010	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6610110	0	0
T1	12854	9011	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1447	0	0
T1	12854	23	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T11	0	4	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T37	0	13	0	0
T40	0	9	0	0
T52	0	10	0	0
T73	0	12	0	0
T74	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1414	0	0
T1	12854	23	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T11	0	4	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T37	0	13	0	0
T40	0	7	0	0
T52	0	1	0	0
T73	0	12	0	0
T74	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	919	0	0
T1	12854	23	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T37	0	13	0	0
T40	0	5	0	0
T73	0	12	0	0
T74	0	7	0	0
T75	0	11	0	0
T88	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	919	0	0
T1	12854	23	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T37	0	13	0	0
T40	0	5	0	0
T73	0	12	0	0
T74	0	7	0	0
T75	0	11	0	0
T88	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	78343	0	0
T1	12854	935	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	40	0	0
T12	0	1227	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	81	0	0
T37	0	595	0	0
T40	0	292	0	0
T73	0	1340	0	0
T74	0	136	0	0
T75	0	1630	0	0
T88	0	1056	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	819	0	0
T1	12854	21	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	13	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	12	0	0
T40	0	5	0	0
T73	0	12	0	0
T74	0	7	0	0
T75	0	9	0	0
T88	0	28	0	0
T119	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T11
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T12,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T12,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T12,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T12,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T35
0	1	Covered	T92,T93,T94
1	0	Covered	T40,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T35
0	1	Covered	T1,T12,T35
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T35
1	-	Covered	T1,T12,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T35
DetectSt	168	Covered	T1,T12,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T12,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T35
DebounceSt->IdleSt	163	Covered	T36,T40,T42
DetectSt->IdleSt	186	Covered	T40,T42,T92
DetectSt->StableSt	191	Covered	T1,T12,T35
IdleSt->DebounceSt	148	Covered	T1,T12,T35
StableSt->IdleSt	206	Covered	T1,T12,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T35
0	1	Covered	T1,T12,T35
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T35
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T92,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T35
DetectSt	-	-	-	-	1	-	-	Covered	T40,T42,T92
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T35
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T35
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	959	0	0
CntIncr_A	7718931	55374	0	0
CntNoWrap_A	7718931	7095374	0	0
DetectStDropOut_A	7718931	44	0	0
DetectedOut_A	7718931	17138	0	0
DetectedPulseOut_A	7718931	396	0	0
DisabledIdleSt_A	7718931	6691106	0	0
DisabledNoDetection_A	7718931	6692630	0	0
EnterDebounceSt_A	7718931	518	0	0
EnterDetectSt_A	7718931	446	0	0
EnterStableSt_A	7718931	396	0	0
PulseIsPulse_A	7718931	396	0	0
StayInStableSt	7718931	16712	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	362	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	959	0	0
T1	12854	4	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	2	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	2	0	0
T36	0	12	0	0
T38	0	12	0	0
T40	0	8	0	0
T53	0	26	0	0
T73	0	6	0	0
T75	0	4	0	0
T88	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	55374	0	0
T1	12854	92	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	62	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	25	0	0
T36	0	565	0	0
T38	0	840	0	0
T40	0	148	0	0
T53	0	949	0	0
T73	0	174	0	0
T75	0	164	0	0
T88	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7095374	0	0
T1	12854	12443	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	44	0	0
T49	12976	0	0	0
T57	3242	0	0	0
T62	3038	0	0	0
T65	492	0	0	0
T66	7583	0	0	0
T84	0	3	0	0
T92	15658	9	0	0
T93	7885	3	0	0
T94	0	10	0	0
T95	0	4	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	2	0	0
T101	0	1	0	0
T105	422	0	0	0
T106	25326	0	0	0
T107	9140	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	17138	0	0
T1	12854	132	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	85	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	3	0	0
T36	0	377	0	0
T38	0	26	0	0
T40	0	82	0	0
T53	0	935	0	0
T73	0	345	0	0
T75	0	91	0	0
T88	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	396	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	1	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T36	0	5	0	0
T38	0	6	0	0
T40	0	1	0	0
T53	0	13	0	0
T73	0	3	0	0
T75	0	2	0	0
T88	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6691106	0	0
T1	12854	11489	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6692630	0	0
T1	12854	11491	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	518	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	1	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T36	0	7	0	0
T38	0	6	0	0
T40	0	5	0	0
T53	0	13	0	0
T73	0	3	0	0
T75	0	2	0	0
T88	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	446	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	1	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T36	0	5	0	0
T38	0	6	0	0
T40	0	3	0	0
T53	0	13	0	0
T73	0	3	0	0
T75	0	2	0	0
T88	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	396	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	1	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T36	0	5	0	0
T38	0	6	0	0
T40	0	1	0	0
T53	0	13	0	0
T73	0	3	0	0
T75	0	2	0	0
T88	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	396	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	1	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T36	0	5	0	0
T38	0	6	0	0
T40	0	1	0	0
T53	0	13	0	0
T73	0	3	0	0
T75	0	2	0	0
T88	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	16712	0	0
T1	12854	130	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	84	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	2	0	0
T36	0	372	0	0
T38	0	20	0	0
T40	0	81	0	0
T53	0	922	0	0
T73	0	342	0	0
T75	0	89	0	0
T88	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	362	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T12	0	1	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T35	0	1	0	0
T36	0	5	0	0
T38	0	6	0	0
T39	0	1	0	0
T53	0	13	0	0
T73	0	3	0	0
T75	0	2	0	0
T119	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T11
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T52,T40
1	0	Covered	T1,T40,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T12
0	1	Covered	T7,T11,T12
1	0	Covered	T263

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T12
1	-	Covered	T7,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T52,T40,T42
DetectSt->IdleSt	186	Covered	T1,T52,T40
DetectSt->StableSt	191	Covered	T7,T11,T12
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T7,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T7,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T40,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T1,T52,T40
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	3122	0	0
CntIncr_A	7718931	117767	0	0
CntNoWrap_A	7718931	7093211	0	0
DetectStDropOut_A	7718931	417	0	0
DetectedOut_A	7718931	86704	0	0
DetectedPulseOut_A	7718931	935	0	0
DisabledIdleSt_A	7718931	6599661	0	0
DisabledNoDetection_A	7718931	6601792	0	0
EnterDebounceSt_A	7718931	1581	0	0
EnterDetectSt_A	7718931	1541	0	0
EnterStableSt_A	7718931	935	0	0
PulseIsPulse_A	7718931	935	0	0
StayInStableSt	7718931	85687	0	0
gen_high_event_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	846	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	3122	0	0
T1	12854	56	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	58	0	0
T11	0	48	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	16	0	0
T40	0	16	0	0
T52	0	11	0	0
T73	0	40	0	0
T74	0	38	0	0
T75	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	117767	0	0
T1	12854	1445	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1914	0	0
T11	0	1536	0	0
T12	0	1078	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	472	0	0
T40	0	387	0	0
T52	0	430	0	0
T73	0	1081	0	0
T74	0	950	0	0
T75	0	704	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7093211	0	0
T1	12854	12391	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	417	0	0
T1	12854	9	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T52	0	1	0	0
T73	0	15	0	0
T90	0	29	0	0
T91	0	4	0	0
T129	0	21	0	0
T261	0	18	0	0
T262	0	25	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	86704	0	0
T7	8323	1981	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	1648	0	0
T12	12419	1845	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	538	0	0
T40	0	357	0	0
T42	0	317	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	2348	0	0
T75	0	1057	0	0
T88	0	932	0	0
T119	0	2167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	935	0	0
T7	8323	29	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	24	0	0
T12	12419	14	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	8	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	19	0	0
T75	0	8	0	0
T88	0	22	0	0
T119	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6599661	0	0
T1	12854	9676	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6601792	0	0
T1	12854	9679	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1581	0	0
T1	12854	28	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	29	0	0
T11	0	24	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	8	0	0
T40	0	9	0	0
T52	0	10	0	0
T73	0	20	0	0
T74	0	19	0	0
T75	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1541	0	0
T1	12854	28	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	29	0	0
T11	0	24	0	0
T12	0	14	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	8	0	0
T40	0	7	0	0
T52	0	1	0	0
T73	0	20	0	0
T74	0	19	0	0
T75	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	935	0	0
T7	8323	29	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	24	0	0
T12	12419	14	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	8	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	19	0	0
T75	0	8	0	0
T88	0	22	0	0
T119	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	935	0	0
T7	8323	29	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	24	0	0
T12	12419	14	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	8	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	19	0	0
T75	0	8	0	0
T88	0	22	0	0
T119	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	85687	0	0
T7	8323	1952	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	1623	0	0
T12	12419	1831	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	529	0	0
T40	0	352	0	0
T42	0	312	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	2323	0	0
T75	0	1049	0	0
T88	0	910	0	0
T119	0	2139	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	846	0	0
T7	8323	29	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	23	0	0
T12	12419	14	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	7	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	13	0	0
T75	0	8	0	0
T88	0	22	0	0
T119	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T10
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T51,T93,T43
1	0	Covered	T40,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
1	0	Covered	T40,T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T11
1	-	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T11
DetectSt	168	Covered	T7,T10,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T11
DebounceSt->IdleSt	163	Covered	T10,T36,T51
DetectSt->IdleSt	186	Covered	T51,T40,T42
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T7,T10,T11
StableSt->IdleSt	206	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T36,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T51,T40,T42
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	940	0	0
CntIncr_A	7718931	55893	0	0
CntNoWrap_A	7718931	7095393	0	0
DetectStDropOut_A	7718931	63	0	0
DetectedOut_A	7718931	14865	0	0
DetectedPulseOut_A	7718931	369	0	0
DisabledIdleSt_A	7718931	6696676	0	0
DisabledNoDetection_A	7718931	6698290	0	0
EnterDebounceSt_A	7718931	504	0	0
EnterDetectSt_A	7718931	438	0	0
EnterStableSt_A	7718931	369	0	0
PulseIsPulse_A	7718931	369	0	0
StayInStableSt	7718931	14474	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	344	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	940	0	0
T7	8323	6	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	3	0	0
T11	9572	2	0	0
T12	12419	8	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T40	0	8	0	0
T51	0	12	0	0
T53	0	10	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	55893	0	0
T7	8323	237	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	216	0	0
T11	9572	53	0	0
T12	12419	368	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	259	0	0
T37	0	94	0	0
T40	0	203	0	0
T51	0	1223	0	0
T53	0	690	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	296	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7095393	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	63	0	0
T28	496	0	0	0
T31	717	0	0	0
T43	0	4	0	0
T51	13910	5	0	0
T52	4799	0	0	0
T68	502	0	0	0
T69	507	0	0	0
T70	524	0	0	0
T71	523	0	0	0
T93	0	5	0	0
T95	0	12	0	0
T101	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0
T201	0	2	0	0
T264	0	1	0	0
T265	0	5	0	0
T266	0	6	0	0
T267	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	14865	0	0
T7	8323	160	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	10	0	0
T11	9572	82	0	0
T12	12419	224	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	6	0	0
T37	0	41	0	0
T40	0	84	0	0
T53	0	32	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	173	0	0
T75	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	369	0	0
T7	8323	3	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	1	0	0
T11	9572	1	0	0
T12	12419	4	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T53	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	4	0	0
T75	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6696676	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6698290	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	504	0	0
T7	8323	3	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	2	0	0
T11	9572	1	0	0
T12	12419	4	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	5	0	0
T51	0	7	0	0
T53	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	438	0	0
T7	8323	3	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	1	0	0
T11	9572	1	0	0
T12	12419	4	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	3	0	0
T51	0	5	0	0
T53	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	369	0	0
T7	8323	3	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	1	0	0
T11	9572	1	0	0
T12	12419	4	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T53	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	4	0	0
T75	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	369	0	0
T7	8323	3	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	1	0	0
T11	9572	1	0	0
T12	12419	4	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T53	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	4	0	0
T75	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	14474	0	0
T7	8323	157	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	9	0	0
T11	9572	81	0	0
T12	12419	220	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	5	0	0
T37	0	40	0	0
T40	0	83	0	0
T53	0	27	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	169	0	0
T75	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	344	0	0
T7	8323	3	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	1	0	0
T11	9572	1	0	0
T12	12419	4	0	0
T13	647	0	0	0
T19	494	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T53	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	4	0	0
T75	0	1	0	0
T88	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T11
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T11,T52,T40
1	0	Covered	T11,T40,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T12
1	-	Covered	T1,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T52,T40,T42
DetectSt->IdleSt	186	Covered	T11,T52,T40
DetectSt->StableSt	191	Covered	T1,T7,T12
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T1,T7,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T7,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T40,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T52,T40
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	2827	0	0
CntIncr_A	7718931	101146	0	0
CntNoWrap_A	7718931	7093506	0	0
DetectStDropOut_A	7718931	426	0	0
DetectedOut_A	7718931	60855	0	0
DetectedPulseOut_A	7718931	748	0	0
DisabledIdleSt_A	7718931	6616451	0	0
DisabledNoDetection_A	7718931	6618559	0	0
EnterDebounceSt_A	7718931	1435	0	0
EnterDetectSt_A	7718931	1392	0	0
EnterStableSt_A	7718931	748	0	0
PulseIsPulse_A	7718931	748	0	0
StayInStableSt	7718931	60003	0	0
gen_high_event_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	643	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2827	0	0
T1	12854	32	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	2	0	0
T11	0	32	0	0
T12	0	56	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	24	0	0
T40	0	16	0	0
T52	0	34	0	0
T73	0	12	0	0
T74	0	8	0	0
T75	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	101146	0	0
T1	12854	576	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	47	0	0
T11	0	1073	0	0
T12	0	2380	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	996	0	0
T40	0	331	0	0
T52	0	1032	0	0
T73	0	323	0	0
T74	0	248	0	0
T75	0	3524	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7093506	0	0
T1	12854	12415	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	426	0	0
T11	9572	11	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	16529	0	0	0
T40	0	1	0	0
T47	4272	0	0	0
T52	0	10	0	0
T63	438	0	0	0
T67	524	0	0	0
T73	0	3	0	0
T75	0	13	0	0
T90	0	27	0	0
T129	0	9	0	0
T145	425	0	0	0
T261	0	18	0	0
T262	0	24	0	0
T268	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	60855	0	0
T1	12854	1325	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	40	0	0
T12	0	2743	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	663	0	0
T40	0	360	0	0
T42	0	353	0	0
T74	0	109	0	0
T91	0	627	0	0
T107	0	1861	0	0
T119	0	1881	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	748	0	0
T1	12854	16	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	12	0	0
T40	0	5	0	0
T42	0	5	0	0
T74	0	4	0	0
T91	0	5	0	0
T107	0	22	0	0
T119	0	34	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6616451	0	0
T1	12854	8583	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6618559	0	0
T1	12854	8585	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1435	0	0
T1	12854	16	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T11	0	16	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	12	0	0
T40	0	9	0	0
T52	0	24	0	0
T73	0	6	0	0
T74	0	4	0	0
T75	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1392	0	0
T1	12854	16	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T11	0	16	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	12	0	0
T40	0	7	0	0
T52	0	10	0	0
T73	0	6	0	0
T74	0	4	0	0
T75	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	748	0	0
T1	12854	16	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	12	0	0
T40	0	5	0	0
T42	0	5	0	0
T74	0	4	0	0
T91	0	5	0	0
T107	0	22	0	0
T119	0	34	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	748	0	0
T1	12854	16	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	28	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	12	0	0
T40	0	5	0	0
T42	0	5	0	0
T74	0	4	0	0
T91	0	5	0	0
T107	0	22	0	0
T119	0	34	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	60003	0	0
T1	12854	1308	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	39	0	0
T12	0	2714	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	648	0	0
T40	0	355	0	0
T42	0	348	0	0
T74	0	105	0	0
T91	0	617	0	0
T107	0	1839	0	0
T119	0	1843	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	643	0	0
T1	12854	15	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	1	0	0
T12	0	27	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	9	0	0
T40	0	5	0	0
T42	0	4	0	0
T74	0	4	0	0
T107	0	22	0	0
T119	0	30	0	0
T158	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T10
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T10
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Covered	T51,T53,T40
1	0	Covered	T40,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T12
1	-	Covered	T1,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T1,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T12
DebounceSt->IdleSt	163	Covered	T10,T36,T51
DetectSt->IdleSt	186	Covered	T51,T53,T40
DetectSt->StableSt	191	Covered	T1,T10,T12
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T1,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T36,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T51,T53,T40
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T10,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	905	0	0
CntIncr_A	7718931	53155	0	0
CntNoWrap_A	7718931	7095428	0	0
DetectStDropOut_A	7718931	82	0	0
DetectedOut_A	7718931	16016	0	0
DetectedPulseOut_A	7718931	348	0	0
DisabledIdleSt_A	7718931	6710734	0	0
DisabledNoDetection_A	7718931	6712295	0	0
EnterDebounceSt_A	7718931	472	0	0
EnterDetectSt_A	7718931	433	0	0
EnterStableSt_A	7718931	348	0	0
PulseIsPulse_A	7718931	348	0	0
StayInStableSt	7718931	15648	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	327	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	905	0	0
T1	12854	2	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	7	0	0
T12	0	6	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	5	0	0
T37	0	4	0	0
T38	0	9	0	0
T39	0	6	0	0
T40	0	8	0	0
T51	0	17	0	0
T53	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	53155	0	0
T1	12854	36	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	430	0	0
T12	0	261	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	384	0	0
T37	0	152	0	0
T38	0	628	0	0
T39	0	459	0	0
T40	0	206	0	0
T51	0	1733	0	0
T53	0	722	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7095428	0	0
T1	12854	12445	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	82	0	0
T28	496	0	0	0
T31	717	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T40	0	1	0	0
T51	13910	7	0	0
T52	4799	0	0	0
T53	0	5	0	0
T68	502	0	0	0
T69	507	0	0	0
T70	524	0	0	0
T71	523	0	0	0
T96	0	1	0	0
T120	0	1	0	0
T172	422	0	0	0
T173	422	0	0	0
T191	0	1	0	0
T269	0	2	0	0
T270	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	16016	0	0
T1	12854	75	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	96	0	0
T12	0	183	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	72	0	0
T37	0	117	0	0
T40	0	82	0	0
T42	0	92	0	0
T91	0	133	0	0
T119	0	92	0	0
T271	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	348	0	0
T1	12854	1	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	3	0	0
T12	0	3	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T91	0	3	0	0
T119	0	2	0	0
T271	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6710734	0	0
T1	12854	11123	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6712295	0	0
T1	12854	11126	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	472	0	0
T1	12854	1	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	5	0	0
T39	0	3	0	0
T40	0	5	0	0
T51	0	10	0	0
T53	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	433	0	0
T1	12854	1	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	3	0	0
T12	0	3	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	3	0	0
T40	0	3	0	0
T51	0	7	0	0
T53	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	348	0	0
T1	12854	1	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	3	0	0
T12	0	3	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T91	0	3	0	0
T119	0	2	0	0
T271	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	348	0	0
T1	12854	1	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	3	0	0
T12	0	3	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T91	0	3	0	0
T119	0	2	0	0
T271	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	15648	0	0
T1	12854	74	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	93	0	0
T12	0	180	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	70	0	0
T37	0	115	0	0
T40	0	81	0	0
T42	0	91	0	0
T91	0	127	0	0
T119	0	90	0	0
T271	0	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	327	0	0
T1	12854	1	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	0	0	0
T10	0	3	0	0
T12	0	3	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T92	0	3	0	0
T119	0	2	0	0
T271	0	2	0	0