Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T11
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T52,T40,T73
1	0	Covered	T1,T11,T12

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T40,T37
0	1	Covered	T7,T40,T37
1	0	Covered	T79,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T40,T37
1	-	Covered	T7,T40,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T40,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T52,T40,T42
DetectSt->IdleSt	186	Covered	T1,T11,T12
DetectSt->StableSt	191	Covered	T7,T40,T37
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T7,T40,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T7,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T40,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T1,T11,T12
DetectSt	-	-	-	-	0	1	-	Covered	T7,T40,T37
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T40,T37
StableSt	-	-	-	-	-	-	0	Covered	T7,T40,T37
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	2904	0	0
CntIncr_A	7718931	116601	0	0
CntNoWrap_A	7718931	7093429	0	0
DetectStDropOut_A	7718931	366	0	0
DetectedOut_A	7718931	83034	0	0
DetectedPulseOut_A	7718931	858	0	0
DisabledIdleSt_A	7718931	6607883	0	0
DisabledNoDetection_A	7718931	6609983	0	0
EnterDebounceSt_A	7718931	1476	0	0
EnterDetectSt_A	7718931	1428	0	0
EnterStableSt_A	7718931	858	0	0
PulseIsPulse_A	7718931	858	0	0
StayInStableSt	7718931	82063	0	0
gen_high_event_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	740	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	2904	0	0
T1	12854	14	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	24	0	0
T11	0	20	0	0
T12	0	10	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	44	0	0
T40	0	17	0	0
T52	0	14	0	0
T73	0	34	0	0
T74	0	22	0	0
T75	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	116601	0	0
T1	12854	359	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	660	0	0
T11	0	678	0	0
T12	0	602	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	1254	0	0
T40	0	375	0	0
T52	0	559	0	0
T73	0	926	0	0
T74	0	913	0	0
T75	0	510	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7093429	0	0
T1	12854	12433	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	366	0	0
T27	975	0	0	0
T31	717	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T52	4799	1	0	0
T53	34889	0	0	0
T64	494	0	0	0
T73	0	12	0	0
T90	0	27	0	0
T129	0	8	0	0
T261	0	27	0	0
T262	0	29	0	0
T268	0	7	0	0
T272	0	1	0	0
T273	874	0	0	0
T274	404	0	0	0
T275	425	0	0	0
T276	8402	0	0	0
T277	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	83034	0	0
T7	8323	380	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	2412	0	0
T40	0	418	0	0
T42	0	276	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	787	0	0
T75	0	314	0	0
T91	0	2137	0	0
T107	0	1951	0	0
T119	0	1951	0	0
T158	0	1248	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	858	0	0
T7	8323	12	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	22	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	11	0	0
T75	0	6	0	0
T91	0	15	0	0
T107	0	26	0	0
T119	0	27	0	0
T158	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6607883	0	0
T1	12854	9681	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6609983	0	0
T1	12854	9684	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1476	0	0
T1	12854	7	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	12	0	0
T11	0	10	0	0
T12	0	5	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	22	0	0
T40	0	10	0	0
T52	0	13	0	0
T73	0	17	0	0
T74	0	11	0	0
T75	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	1428	0	0
T1	12854	7	0	0
T2	737	0	0	0
T3	2496	0	0	0
T7	8323	12	0	0
T11	0	10	0	0
T12	0	5	0	0
T14	494	0	0	0
T15	4402	0	0	0
T16	404	0	0	0
T17	495	0	0	0
T18	408	0	0	0
T19	494	0	0	0
T37	0	22	0	0
T40	0	7	0	0
T52	0	1	0	0
T73	0	17	0	0
T74	0	11	0	0
T75	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	858	0	0
T7	8323	12	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	22	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	11	0	0
T75	0	6	0	0
T91	0	15	0	0
T107	0	26	0	0
T119	0	27	0	0
T158	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	858	0	0
T7	8323	12	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	22	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	11	0	0
T75	0	6	0	0
T91	0	15	0	0
T107	0	26	0	0
T119	0	27	0	0
T158	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	82063	0	0
T7	8323	368	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	2388	0	0
T40	0	413	0	0
T42	0	271	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	773	0	0
T75	0	308	0	0
T91	0	2111	0	0
T107	0	1925	0	0
T119	0	1923	0	0
T158	0	1221	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	740	0	0
T7	8323	12	0	0
T8	1841	0	0	0
T9	783	0	0	0
T10	14308	0	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T19	494	0	0	0
T37	0	20	0	0
T40	0	5	0	0
T42	0	5	0	0
T58	815	0	0	0
T63	438	0	0	0
T74	0	8	0	0
T75	0	6	0	0
T91	0	4	0	0
T107	0	26	0	0
T119	0	26	0	0
T158	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T7,T10
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T10
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T36,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T36,T51

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T36,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T10,T36,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T36,T51
0	1	Covered	T53,T40,T92
1	0	Covered	T40,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T36,T51
0	1	Covered	T10,T36,T51
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T36,T51
1	-	Covered	T10,T36,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T36,T51
DetectSt	168	Covered	T10,T36,T51
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T36,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T36,T51
DebounceSt->IdleSt	163	Covered	T36,T40,T38
DetectSt->IdleSt	186	Covered	T53,T40,T42
DetectSt->StableSt	191	Covered	T10,T36,T51
IdleSt->DebounceSt	148	Covered	T10,T36,T51
StableSt->IdleSt	206	Covered	T10,T36,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T36,T51
0	1	Covered	T10,T36,T51
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T36,T51
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T36,T51
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T40,T42
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T36,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T38,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T36,T51
DetectSt	-	-	-	-	1	-	-	Covered	T53,T40,T42
DetectSt	-	-	-	-	0	1	-	Covered	T10,T36,T51
DetectSt	-	-	-	-	0	0	-	Covered	T10,T36,T51
StableSt	-	-	-	-	-	-	1	Covered	T10,T36,T51
StableSt	-	-	-	-	-	-	0	Covered	T10,T36,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7718931	888	0	0
CntIncr_A	7718931	50323	0	0
CntNoWrap_A	7718931	7095445	0	0
DetectStDropOut_A	7718931	76	0	0
DetectedOut_A	7718931	17880	0	0
DetectedPulseOut_A	7718931	339	0	0
DisabledIdleSt_A	7718931	6702151	0	0
DisabledNoDetection_A	7718931	6703737	0	0
EnterDebounceSt_A	7718931	470	0	0
EnterDetectSt_A	7718931	418	0	0
EnterStableSt_A	7718931	339	0	0
PulseIsPulse_A	7718931	339	0	0
StayInStableSt	7718931	17498	0	0
gen_high_level_sva.HighLevelEvent_A	7718931	7098636	0	0
gen_not_sticky_sva.StableStDropOut_A	7718931	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	888	0	0
T10	14308	4	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	5	0	0
T37	0	2	0	0
T38	0	15	0	0
T39	0	13	0	0
T40	0	8	0	0
T47	4272	0	0	0
T51	0	6	0	0
T53	0	12	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	6	0	0
T91	0	16	0	0
T145	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	50323	0	0
T10	14308	286	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	346	0	0
T37	0	64	0	0
T38	0	716	0	0
T39	0	890	0	0
T40	0	266	0	0
T47	4272	0	0	0
T51	0	339	0	0
T53	0	866	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	162	0	0
T91	0	360	0	0
T145	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7095445	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	76	0	0
T37	17173	0	0	0
T40	6625	1	0	0
T44	0	1	0	0
T53	34889	6	0	0
T92	0	1	0	0
T93	0	4	0	0
T96	0	1	0	0
T112	0	2	0	0
T120	0	3	0	0
T257	401	0	0	0
T258	674	0	0	0
T264	0	10	0	0
T274	404	0	0	0
T275	425	0	0	0
T276	8402	0	0	0
T277	406	0	0	0
T278	0	2	0	0
T279	255180	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	17880	0	0
T10	14308	13	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	110	0	0
T37	0	71	0	0
T38	0	347	0	0
T39	0	105	0	0
T40	0	83	0	0
T47	4272	0	0	0
T51	0	280	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	188	0	0
T91	0	411	0	0
T119	0	70	0	0
T145	425	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	339	0	0
T10	14308	2	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	7	0	0
T39	0	6	0	0
T40	0	1	0	0
T47	4272	0	0	0
T51	0	3	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	3	0	0
T91	0	8	0	0
T119	0	1	0	0
T145	425	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6702151	0	0
T1	12854	12447	0	0
T2	737	336	0	0
T4	7402	4086	0	0
T5	1645	42	0	0
T6	505	104	0	0
T14	494	93	0	0
T20	424	23	0	0
T21	422	21	0	0
T22	410	9	0	0
T23	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	6703737	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	470	0	0
T10	14308	2	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	8	0	0
T39	0	7	0	0
T40	0	5	0	0
T47	4272	0	0	0
T51	0	3	0	0
T53	0	6	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	3	0	0
T91	0	8	0	0
T145	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	418	0	0
T10	14308	2	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	7	0	0
T39	0	6	0	0
T40	0	3	0	0
T47	4272	0	0	0
T51	0	3	0	0
T53	0	6	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	3	0	0
T91	0	8	0	0
T145	425	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	339	0	0
T10	14308	2	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	7	0	0
T39	0	6	0	0
T40	0	1	0	0
T47	4272	0	0	0
T51	0	3	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	3	0	0
T91	0	8	0	0
T119	0	1	0	0
T145	425	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	339	0	0
T10	14308	2	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	7	0	0
T39	0	6	0	0
T40	0	1	0	0
T47	4272	0	0	0
T51	0	3	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	3	0	0
T91	0	8	0	0
T119	0	1	0	0
T145	425	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	17498	0	0
T10	14308	11	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	108	0	0
T37	0	70	0	0
T38	0	340	0	0
T39	0	99	0	0
T40	0	82	0	0
T47	4272	0	0	0
T51	0	277	0	0
T63	438	0	0	0
T67	524	0	0	0
T74	0	182	0	0
T91	0	395	0	0
T119	0	69	0	0
T145	425	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	7098636	0	0
T1	12854	12451	0	0
T2	737	337	0	0
T4	7402	4095	0	0
T5	1645	45	0	0
T6	505	105	0	0
T14	494	94	0	0
T20	424	24	0	0
T21	422	22	0	0
T22	410	10	0	0
T23	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7718931	294	0	0
T10	14308	2	0	0
T11	9572	0	0	0
T12	12419	0	0	0
T13	647	0	0	0
T29	522	0	0	0
T35	509	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	7	0	0
T39	0	6	0	0
T43	0	3	0	0
T47	4272	0	0	0
T51	0	3	0	0
T63	438	0	0	0
T67	524	0	0	0
T106	0	10	0	0
T107	0	2	0	0
T119	0	1	0	0
T145	425	0	0	0