Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1187298715	10527	0	0
auto_block_debounce_ctl_rd_A	1187298715	1876	0	0
auto_block_out_ctl_rd_A	1187298715	2997	0	0
com_det_ctl_0_rd_A	1187298715	4221	0	0
com_det_ctl_1_rd_A	1187298715	4404	0	0
com_det_ctl_2_rd_A	1187298715	4535	0	0
com_det_ctl_3_rd_A	1187298715	4646	0	0
com_out_ctl_0_rd_A	1187298715	5073	0	0
com_out_ctl_1_rd_A	1187298715	5048	0	0
com_out_ctl_2_rd_A	1187298715	5165	0	0
com_out_ctl_3_rd_A	1187298715	5050	0	0
com_pre_det_ctl_0_rd_A	1187298715	1488	0	0
com_pre_det_ctl_1_rd_A	1187298715	1448	0	0
com_pre_det_ctl_2_rd_A	1187298715	1370	0	0
com_pre_det_ctl_3_rd_A	1187298715	1338	0	0
com_pre_sel_ctl_0_rd_A	1187298715	5535	0	0
com_pre_sel_ctl_1_rd_A	1187298715	5516	0	0
com_pre_sel_ctl_2_rd_A	1187298715	5363	0	0
com_pre_sel_ctl_3_rd_A	1187298715	5334	0	0
com_sel_ctl_0_rd_A	1187298715	5286	0	0
com_sel_ctl_1_rd_A	1187298715	5454	0	0
com_sel_ctl_2_rd_A	1187298715	5431	0	0
com_sel_ctl_3_rd_A	1187298715	5465	0	0
ec_rst_ctl_rd_A	1187298715	2699	0	0
intr_enable_rd_A	1187298715	1784	0	0
key_intr_ctl_rd_A	1187298715	5048	0	0
key_intr_debounce_ctl_rd_A	1187298715	1442	0	0
key_invert_ctl_rd_A	1187298715	6330	0	0
pin_allowed_ctl_rd_A	1187298715	7452	0	0
pin_out_ctl_rd_A	1187298715	5442	0	0
pin_out_value_rd_A	1187298715	5948	0	0
regwen_rd_A	1187298715	1468	0	0
ulp_ac_debounce_ctl_rd_A	1187298715	1518	0	0
ulp_ctl_rd_A	1187298715	1622	0	0
ulp_lid_debounce_ctl_rd_A	1187298715	1565	0	0
ulp_pwrb_debounce_ctl_rd_A	1187298715	1601	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	10527	0	0
T1	141402	0	0	0
T2	298170	0	0	0
T4	181352	7	0	0
T5	822803	0	0	0
T6	63214	0	0	0
T14	59293	0	0	0
T20	53125	0	0	0
T21	171242	0	0	0
T22	98375	0	0	0
T23	50564	0	0	0
T43	0	23	0	0
T44	0	5	0	0
T45	0	5	0	0
T47	0	3	0	0
T49	0	13	0	0
T66	0	12	0	0
T85	0	10	0	0
T213	0	9	0	0
T297	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1876	0	0
T27	221661	0	0	0
T31	25118	3	0	0
T53	170956	0	0	0
T64	239754	0	0	0
T77	0	18	0	0
T78	0	8	0	0
T83	0	24	0	0
T108	0	7	0	0
T117	0	2	0	0
T189	0	27	0	0
T273	419732	0	0	0
T274	82941	0	0	0
T275	53276	0	0	0
T276	403318	0	0	0
T277	50817	0	0	0
T279	102072	0	0	0
T298	0	14	0	0
T299	0	9	0	0
T300	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	2997	0	0
T28	59655	0	0	0
T30	76899	12	0	0
T31	0	11	0	0
T51	688574	0	0	0
T52	215982	0	0	0
T68	241246	0	0	0
T69	63370	0	0	0
T70	125855	0	0	0
T71	128294	0	0	0
T77	0	24	0	0
T78	0	7	0	0
T108	0	9	0	0
T172	211413	0	0	0
T173	206947	0	0	0
T189	0	33	0	0
T298	0	14	0	0
T299	0	8	0	0
T300	0	13	0	0
T301	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	4221	0	0
T7	399530	18	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	84	0	0
T37	0	85	0	0
T39	0	55	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	35	0	0
T74	0	73	0	0
T75	0	61	0	0
T91	0	70	0	0
T106	0	68	0	0
T158	0	51	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	4404	0	0
T7	399530	19	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	47	0	0
T37	0	75	0	0
T39	0	61	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	28	0	0
T74	0	66	0	0
T75	0	66	0	0
T91	0	49	0	0
T106	0	82	0	0
T158	0	55	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	4535	0	0
T7	399530	20	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	71	0	0
T37	0	59	0	0
T39	0	55	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	43	0	0
T74	0	70	0	0
T75	0	51	0	0
T91	0	61	0	0
T106	0	69	0	0
T158	0	35	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	4646	0	0
T7	399530	40	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	103	0	0
T37	0	70	0	0
T39	0	86	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	45	0	0
T74	0	66	0	0
T75	0	64	0	0
T91	0	81	0	0
T106	0	66	0	0
T158	0	44	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5073	0	0
T7	399530	1	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	65	0	0
T37	0	65	0	0
T39	0	65	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	34	0	0
T74	0	65	0	0
T75	0	77	0	0
T91	0	86	0	0
T106	0	72	0	0
T158	0	49	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5048	0	0
T7	399530	12	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	73	0	0
T37	0	57	0	0
T39	0	72	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	28	0	0
T74	0	73	0	0
T75	0	69	0	0
T91	0	55	0	0
T106	0	83	0	0
T158	0	67	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5165	0	0
T7	399530	26	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	80	0	0
T37	0	66	0	0
T39	0	87	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	42	0	0
T74	0	43	0	0
T75	0	67	0	0
T91	0	90	0	0
T106	0	73	0	0
T158	0	52	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5050	0	0
T7	399530	28	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	60	0	0
T37	0	57	0	0
T39	0	62	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	41	0	0
T74	0	53	0	0
T75	0	78	0	0
T91	0	94	0	0
T106	0	67	0	0
T158	0	41	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1488	0	0
T77	264804	46	0	0
T83	0	27	0	0
T84	0	18	0	0
T139	0	8	0	0
T140	0	14	0	0
T185	68137	0	0	0
T186	370828	0	0	0
T187	125823	0	0	0
T188	153059	0	0	0
T189	134430	10	0	0
T190	977423	0	0	0
T191	397726	0	0	0
T192	33722	0	0	0
T193	638323	0	0	0
T301	0	10	0	0
T302	0	32	0	0
T303	0	17	0	0
T304	0	16	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1448	0	0
T77	264804	44	0	0
T83	0	12	0	0
T84	0	10	0	0
T139	0	1	0	0
T140	0	14	0	0
T185	68137	0	0	0
T186	370828	0	0	0
T187	125823	0	0	0
T188	153059	0	0	0
T189	134430	14	0	0
T190	977423	0	0	0
T191	397726	0	0	0
T192	33722	0	0	0
T193	638323	0	0	0
T301	0	11	0	0
T302	0	14	0	0
T303	0	23	0	0
T304	0	21	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1370	0	0
T77	264804	11	0	0
T83	0	22	0	0
T84	0	10	0	0
T139	0	1	0	0
T140	0	24	0	0
T185	68137	0	0	0
T186	370828	0	0	0
T187	125823	0	0	0
T188	153059	0	0	0
T189	134430	4	0	0
T190	977423	0	0	0
T191	397726	0	0	0
T192	33722	0	0	0
T193	638323	0	0	0
T301	0	2	0	0
T302	0	22	0	0
T303	0	28	0	0
T304	0	21	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1338	0	0
T77	264804	17	0	0
T83	0	20	0	0
T84	0	6	0	0
T139	0	4	0	0
T140	0	10	0	0
T185	68137	0	0	0
T186	370828	0	0	0
T187	125823	0	0	0
T188	153059	0	0	0
T189	134430	16	0	0
T190	977423	0	0	0
T191	397726	0	0	0
T192	33722	0	0	0
T193	638323	0	0	0
T301	0	4	0	0
T302	0	41	0	0
T303	0	13	0	0
T304	0	10	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5535	0	0
T28	59655	0	0	0
T30	76899	0	0	0
T36	173557	79	0	0
T37	0	47	0	0
T39	0	56	0	0
T51	688574	0	0	0
T68	241246	0	0	0
T69	63370	0	0	0
T70	125855	0	0	0
T71	128294	0	0	0
T73	0	33	0	0
T74	0	52	0	0
T75	0	75	0	0
T91	0	84	0	0
T106	0	82	0	0
T120	0	71	0	0
T158	0	43	0	0
T172	211413	0	0	0
T173	206947	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5516	0	0
T7	399530	38	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	65	0	0
T37	0	76	0	0
T39	0	74	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	26	0	0
T74	0	58	0	0
T75	0	57	0	0
T91	0	85	0	0
T106	0	69	0	0
T158	0	54	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5363	0	0
T7	399530	16	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	47	0	0
T37	0	71	0	0
T39	0	66	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	47	0	0
T74	0	45	0	0
T75	0	77	0	0
T91	0	83	0	0
T106	0	79	0	0
T158	0	53	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5334	0	0
T7	399530	36	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	56	0	0
T37	0	40	0	0
T39	0	76	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	47	0	0
T74	0	52	0	0
T75	0	79	0	0
T91	0	86	0	0
T106	0	57	0	0
T158	0	53	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5286	0	0
T7	399530	24	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	87	0	0
T37	0	39	0	0
T39	0	85	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	46	0	0
T74	0	64	0	0
T75	0	71	0	0
T91	0	75	0	0
T106	0	70	0	0
T158	0	48	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5454	0	0
T7	399530	6	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	83	0	0
T37	0	65	0	0
T39	0	75	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	39	0	0
T74	0	54	0	0
T75	0	49	0	0
T91	0	92	0	0
T106	0	67	0	0
T158	0	34	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5431	0	0
T7	399530	21	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	74	0	0
T37	0	93	0	0
T39	0	68	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	33	0	0
T74	0	59	0	0
T75	0	63	0	0
T91	0	94	0	0
T106	0	86	0	0
T158	0	53	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5465	0	0
T7	399530	31	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T12	149026	0	0	0
T13	127006	0	0	0
T19	118557	0	0	0
T36	0	62	0	0
T37	0	75	0	0
T39	0	62	0	0
T58	375030	0	0	0
T63	17560	0	0	0
T73	0	46	0	0
T74	0	59	0	0
T75	0	50	0	0
T91	0	86	0	0
T106	0	85	0	0
T158	0	51	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	2699	0	0
T28	59655	0	0	0
T30	76899	0	0	0
T36	173557	8	0	0
T37	0	20	0	0
T39	0	8	0	0
T51	688574	0	0	0
T52	0	5	0	0
T68	241246	0	0	0
T69	63370	0	0	0
T70	125855	0	0	0
T71	128294	0	0	0
T73	0	2	0	0
T74	0	19	0	0
T75	0	14	0	0
T90	0	4	0	0
T172	211413	0	0	0
T173	206947	0	0	0
T198	0	3	0	0
T279	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1784	0	0
T1	141402	0	0	0
T2	298170	0	0	0
T5	822803	7	0	0
T6	63214	0	0	0
T14	59293	0	0	0
T15	220125	0	0	0
T20	53125	0	0	0
T21	171242	0	0	0
T22	98375	0	0	0
T23	50564	0	0	0
T77	0	32	0	0
T83	0	27	0	0
T84	0	74	0	0
T189	0	20	0	0
T301	0	8	0	0
T302	0	33	0	0
T303	0	15	0	0
T304	0	50	0	0
T305	0	20	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5048	0	0
T13	127006	5	0	0
T29	245460	0	0	0
T30	76899	0	0	0
T35	124899	0	0	0
T36	173557	0	0	0
T42	0	54	0	0
T47	206877	0	0	0
T50	0	4	0	0
T51	688574	0	0	0
T67	128444	0	0	0
T68	241246	0	0	0
T77	0	14	0	0
T83	0	16	0	0
T143	0	1	0	0
T145	53122	0	0	0
T164	0	5	0	0
T170	0	7	0	0
T189	0	11	0	0
T301	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1442	0	0
T77	264804	31	0	0
T83	0	15	0	0
T84	0	8	0	0
T139	0	12	0	0
T140	0	32	0	0
T185	68137	0	0	0
T186	370828	0	0	0
T187	125823	0	0	0
T188	153059	0	0	0
T189	134430	6	0	0
T190	977423	0	0	0
T191	397726	0	0	0
T192	33722	0	0	0
T193	638323	0	0	0
T301	0	17	0	0
T302	0	40	0	0
T303	0	23	0	0
T304	0	11	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	6330	0	0
T3	61729	0	0	0
T7	399530	0	0	0
T8	118302	0	0	0
T9	300717	0	0	0
T10	150232	0	0	0
T11	430764	0	0	0
T17	232744	63	0	0
T18	44862	0	0	0
T19	118557	0	0	0
T28	0	60	0	0
T58	375030	0	0	0
T62	0	43	0	0
T65	0	71	0	0
T77	0	161	0	0
T120	0	64	0	0
T143	0	59	0	0
T154	0	60	0	0
T189	0	6	0	0
T301	0	7	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	7452	0	0
T27	221661	0	0	0
T28	59655	0	0	0
T31	25118	0	0	0
T52	215982	0	0	0
T53	170956	0	0	0
T64	239754	0	0	0
T69	63370	29	0	0
T70	125855	0	0	0
T71	128294	0	0	0
T77	0	86	0	0
T120	0	72	0	0
T143	0	57	0	0
T157	0	93	0	0
T246	0	55	0	0
T273	419732	0	0	0
T306	0	38	0	0
T307	0	91	0	0
T308	0	60	0	0
T309	0	70	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5442	0	0
T27	221661	0	0	0
T28	59655	0	0	0
T31	25118	0	0	0
T52	215982	0	0	0
T53	170956	0	0	0
T64	239754	0	0	0
T69	63370	36	0	0
T70	125855	0	0	0
T71	128294	0	0	0
T77	0	106	0	0
T120	0	53	0	0
T143	0	84	0	0
T157	0	86	0	0
T246	0	70	0	0
T273	419732	0	0	0
T306	0	37	0	0
T307	0	61	0	0
T308	0	53	0	0
T309	0	91	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	5948	0	0
T27	221661	0	0	0
T28	59655	0	0	0
T31	25118	0	0	0
T52	215982	0	0	0
T53	170956	0	0	0
T64	239754	0	0	0
T69	63370	58	0	0
T70	125855	0	0	0
T71	128294	0	0	0
T77	0	72	0	0
T120	0	65	0	0
T143	0	74	0	0
T157	0	86	0	0
T246	0	85	0	0
T273	419732	0	0	0
T306	0	42	0	0
T307	0	68	0	0
T308	0	83	0	0
T309	0	81	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1468	0	0
T77	264804	31	0	0
T83	0	11	0	0
T84	0	8	0	0
T139	0	11	0	0
T140	0	22	0	0
T185	68137	0	0	0
T186	370828	0	0	0
T187	125823	0	0	0
T188	153059	0	0	0
T189	134430	5	0	0
T190	977423	0	0	0
T191	397726	0	0	0
T192	33722	0	0	0
T193	638323	0	0	0
T301	0	2	0	0
T302	0	33	0	0
T303	0	19	0	0
T304	0	17	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1518	0	0
T77	0	37	0	0
T83	0	24	0	0
T120	885927	2	0	0
T121	250845	0	0	0
T122	0	7	0	0
T189	0	6	0	0
T192	0	7	0	0
T272	901211	0	0	0
T308	238346	0	0	0
T310	0	1	0	0
T311	0	2	0	0
T312	0	5	0	0
T313	0	3	0	0
T314	37977	0	0	0
T315	198923	0	0	0
T316	51030	0	0	0
T317	51212	0	0	0
T318	97011	0	0	0
T319	456424	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1622	0	0
T43	221137	0	0	0
T49	613827	0	0	0
T57	155638	0	0	0
T62	361820	3	0	0
T66	806496	0	0	0
T77	0	22	0	0
T83	0	34	0	0
T89	61395	0	0	0
T93	382498	0	0	0
T106	106370	0	0	0
T107	365622	0	0	0
T120	0	6	0	0
T122	0	11	0	0
T133	0	6	0	0
T189	0	10	0	0
T192	0	17	0	0
T193	0	1	0	0
T262	236109	0	0	0
T301	0	15	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1565	0	0
T77	0	36	0	0
T83	0	30	0	0
T120	885927	2	0	0
T121	250845	0	0	0
T122	0	2	0	0
T189	0	7	0	0
T192	0	4	0	0
T193	0	5	0	0
T272	901211	0	0	0
T301	0	10	0	0
T308	238346	0	0	0
T310	0	3	0	0
T311	0	2	0	0
T314	37977	0	0	0
T315	198923	0	0	0
T316	51030	0	0	0
T317	51212	0	0	0
T318	97011	0	0	0
T319	456424	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187298715	1601	0	0
T43	221137	0	0	0
T49	613827	0	0	0
T57	155638	0	0	0
T62	361820	3	0	0
T66	806496	0	0	0
T77	0	22	0	0
T83	0	29	0	0
T89	61395	0	0	0
T93	382498	0	0	0
T106	106370	0	0	0
T107	365622	0	0	0
T120	0	6	0	0
T122	0	5	0	0
T133	0	4	0	0
T189	0	16	0	0
T192	0	1	0	0
T262	236109	0	0	0
T301	0	14	0	0
T311	0	4	0	0