Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T14,T3
1	0	Covered	T1,T14,T3
1	1	Covered	T3,T8,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T14,T3
1	0	Covered	T3,T8,T27
1	1	Covered	T1,T14,T3

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	222555	0	0
SrcPulseCheck_M	2147483647	224781	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	222555
T1	3702144	68
T2	7472675	0
T3	1538904	0
T4	377508	18
T5	1648896	0
T6	127438	0
T7	9780149	17
T8	238445	0
T9	300717	0
T10	150232	80
T11	0	34
T12	0	34
T14	1434888	0
T15	5164121	0
T16	1868175	0
T17	5597241	0
T18	1086072	0
T19	2856730	0
T20	107098	0
T21	343328	0
T22	197570	0
T23	101938	0
T30	0	12
T31	0	10
T35	0	5
T36	0	84
T37	0	5
T40	0	123
T42	0	6
T49	0	12
T51	0	64
T52	0	17
T53	0	240
T54	0	14
T55	0	16
T56	0	14
T57	0	16
T58	750875	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	224781
T1	3702144	68
T2	7472675	0
T3	1479671	0
T4	377508	18
T5	1648896	0
T6	127438	0
T7	9388942	17
T8	121984	0
T9	783	0
T10	14308	80
T11	0	34
T12	0	34
T14	1434888	0
T15	5164121	0
T16	1868175	0
T17	5364992	0
T18	1041618	0
T19	2738667	0
T20	107098	0
T21	343328	0
T22	197570	0
T23	101938	0
T30	0	12
T31	0	10
T35	0	5
T36	0	84
T37	0	5
T40	0	123
T42	0	6
T49	0	12
T51	0	64
T52	0	17
T53	0	240
T54	0	14
T55	0	16
T56	0	14
T57	0	16
T58	376660	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T14,T7
1	0	Covered	T1,T14,T7
1	1	Covered	T24,T25,T328

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T14,T7
1	0	Covered	T24,T25,T328
1	1	Covered	T1,T14,T7

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1895	0	0
SrcPulseCheck_M	1187298715	1959	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1895
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	1
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T47	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1959
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	1
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T47	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T14,T7
1	0	Covered	T1,T14,T7
1	1	Covered	T24,T25,T328

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T14,T7
1	0	Covered	T24,T25,T328
1	1	Covered	T1,T14,T7

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1952	0	0
SrcPulseCheck_M	7955931	1952	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1952
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	1
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T47	0	1
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1952
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	1
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T47	0	1
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T27,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T27,T59
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	892	0	0
SrcPulseCheck_M	1187298715	958	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	892
T3	2496	3
T7	8323	0
T8	1841	1
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	815	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	438	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	958
T3	61729	3
T7	399530	0
T8	118302	1
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	375030	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	17560	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T27,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T27,T59
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	951	0	0
SrcPulseCheck_M	7955931	951	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	951
T3	61729	3
T7	399530	0
T8	118302	1
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	375030	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	17560	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	951
T3	2496	3
T7	8323	0
T8	1841	1
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	815	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	438	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T27,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T27,T59
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	909	0	0
SrcPulseCheck_M	1187298715	975	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	909
T3	2496	3
T7	8323	0
T8	1841	1
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	815	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	438	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	975
T3	61729	3
T7	399530	0
T8	118302	1
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	375030	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	17560	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T27,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T27,T59
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	967	0	0
SrcPulseCheck_M	7955931	967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	967
T3	61729	3
T7	399530	0
T8	118302	1
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	375030	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	17560	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	967
T3	2496	3
T7	8323	0
T8	1841	1
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	815	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	438	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T27,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T27,T59
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	897	0	0
SrcPulseCheck_M	1187298715	959	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	897
T3	2496	3
T7	8323	0
T8	1841	1
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	815	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	438	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	959
T3	61729	3
T7	399530	0
T8	118302	1
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	375030	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	17560	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T27,T59

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T27,T59
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	951	0	0
SrcPulseCheck_M	7955931	951	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	951
T3	61729	3
T7	399530	0
T8	118302	1
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	375030	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	17560	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	951
T3	2496	3
T7	8323	0
T8	1841	1
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	1
T42	0	1
T45	0	1
T58	815	0
T59	0	2
T60	0	3
T61	0	1
T62	0	1
T63	438	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T8,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	894	0	0
SrcPulseCheck_M	1187298715	960	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	894
T3	2496	4
T7	8323	0
T8	1841	2
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	3
T42	0	3
T43	0	2
T44	0	2
T58	815	0
T59	0	2
T60	0	4
T62	0	2
T63	438	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	960
T3	61729	4
T7	399530	0
T8	118302	2
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	4
T42	0	4
T43	0	2
T44	0	2
T58	375030	0
T59	0	2
T60	0	4
T62	0	2
T63	17560	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T8,T27

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T8,T27
1	0	Covered	T3,T8,T27
1	1	Covered	T3,T8,T27

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	951	0	0
SrcPulseCheck_M	7955931	951	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	951
T3	61729	4
T7	399530	0
T8	118302	2
T9	300717	0
T10	150232	0
T11	430764	0
T12	149026	0
T19	118557	0
T27	0	2
T40	0	4
T42	0	4
T43	0	2
T44	0	2
T58	375030	0
T59	0	2
T60	0	4
T62	0	2
T63	17560	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	951
T3	2496	4
T7	8323	0
T8	1841	2
T9	783	0
T10	14308	0
T11	9572	0
T12	12419	0
T19	494	0
T27	0	2
T40	0	4
T42	0	4
T43	0	2
T44	0	2
T58	815	0
T59	0	2
T60	0	4
T62	0	2
T63	438	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
1	1	Covered	T3,T7,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T7
1	0	Covered	T3,T7,T12
1	1	Covered	T1,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1060	0	0
SrcPulseCheck_M	1187298715	1129	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1060
T1	12854	3
T2	737	0
T3	2496	2
T7	8323	3
T8	0	1
T10	0	3
T11	0	1
T12	0	3
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T27	0	1
T36	0	1
T37	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1129
T1	141402	3
T2	298170	0
T3	61729	2
T7	399530	3
T8	0	1
T10	0	3
T11	0	1
T12	0	3
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T27	0	1
T36	0	1
T40	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T17,T19,T28
1	0	Covered	T17,T19,T28
1	1	Covered	T17,T19,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T17,T19,T28
1	0	Covered	T17,T19,T28
1	1	Covered	T17,T19,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	2854	0	0
SrcPulseCheck_M	1187298715	2920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	2854
T3	2496	0
T7	8323	0
T8	1841	0
T9	783	0
T10	14308	0
T11	9572	0
T17	495	20
T18	408	0
T19	494	20
T28	0	20
T43	0	20
T45	0	60
T57	0	20
T58	815	0
T62	0	20
T64	0	20
T65	0	20
T66	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	2920
T3	61729	0
T7	399530	0
T8	118302	0
T9	300717	0
T10	150232	0
T11	430764	0
T17	232744	20
T18	44862	0
T19	118557	20
T28	0	20
T43	0	20
T45	0	60
T57	0	20
T58	375030	0
T62	0	20
T64	0	20
T65	0	20
T66	0	40

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T17,T19,T28
1	0	Covered	T17,T19,T28
1	1	Covered	T17,T19,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T17,T19,T28
1	0	Covered	T17,T19,T28
1	1	Covered	T17,T19,T28

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	2912	0	0
SrcPulseCheck_M	7955931	2912	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	2912
T3	61729	0
T7	399530	0
T8	118302	0
T9	300717	0
T10	150232	0
T11	430764	0
T17	232744	20
T18	44862	0
T19	118557	20
T28	0	20
T43	0	20
T45	0	60
T57	0	20
T58	375030	0
T62	0	20
T64	0	20
T65	0	20
T66	0	40

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	2912
T3	2496	0
T7	8323	0
T8	1841	0
T9	783	0
T10	14308	0
T11	9572	0
T17	495	20
T18	408	0
T19	494	20
T28	0	20
T43	0	20
T45	0	60
T57	0	20
T58	815	0
T62	0	20
T64	0	20
T65	0	20
T66	0	40

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T6,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T17

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	6260	0	0
SrcPulseCheck_M	1187298715	6329	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	6260
T1	12854	0
T2	737	0
T4	7402	60
T5	1645	0
T6	505	20
T14	494	0
T17	0	1
T19	0	1
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	6329
T1	141402	0
T2	298170	0
T4	181352	60
T5	822803	0
T6	63214	20
T14	59293	0
T17	0	1
T19	0	1
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T6,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T17

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	6317	0	0
SrcPulseCheck_M	7955931	6317	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	6317
T1	141402	0
T2	298170	0
T4	181352	60
T5	822803	0
T6	63214	20
T14	59293	0
T17	0	1
T19	0	1
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	6317
T1	12854	0
T2	737	0
T4	7402	60
T5	1645	0
T6	505	20
T14	494	0
T17	0	1
T19	0	1
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T1

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	7429	0	0
SrcPulseCheck_M	1187298715	7501	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	7429
T1	12854	4
T2	737	0
T4	7402	60
T5	1645	0
T6	505	20
T7	0	1
T10	0	5
T11	0	2
T14	494	1
T17	0	1
T19	0	1
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	7501
T1	141402	4
T2	298170	0
T4	181352	60
T5	822803	0
T6	63214	20
T7	0	1
T10	0	5
T11	0	2
T14	59293	1
T17	0	1
T19	0	1
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T1

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	7491	0	0
SrcPulseCheck_M	7955931	7491	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	7491
T1	141402	4
T2	298170	0
T4	181352	60
T5	822803	0
T6	63214	20
T7	0	1
T10	0	5
T11	0	2
T14	59293	1
T17	0	1
T19	0	1
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T58	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	7491
T1	12854	4
T2	737	0
T4	7402	60
T5	1645	0
T6	505	20
T7	0	1
T10	0	5
T11	0	2
T14	494	1
T17	0	1
T19	0	1
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T58	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T29
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T29
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T29

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	6168	0	0
SrcPulseCheck_M	1187298715	6235	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	6168
T1	12854	0
T2	737	0
T4	7402	60
T5	1645	0
T6	505	20
T14	494	0
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20
T71	0	20
T72	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	6235
T1	141402	0
T2	298170	0
T4	181352	60
T5	822803	0
T6	63214	20
T14	59293	0
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20
T71	0	20
T72	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T29
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T29

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T29
1	0	Covered	T4,T6,T29
1	1	Covered	T4,T6,T29

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	6224	0	0
SrcPulseCheck_M	7955931	6224	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	6224
T1	141402	0
T2	298170	0
T4	181352	60
T5	822803	0
T6	63214	20
T14	59293	0
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20
T71	0	20
T72	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	6224
T1	12854	0
T2	737	0
T4	7402	60
T5	1645	0
T6	505	20
T14	494	0
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T29	0	20
T47	0	60
T67	0	20
T68	0	20
T69	0	20
T70	0	20
T71	0	20
T72	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T8,T9
1	0	Covered	T40,T42,T24
1	1	Covered	T2,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	907	0	0
SrcPulseCheck_M	1187298715	968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	907
T2	737	1
T3	2496	0
T7	8323	0
T8	1841	1
T9	0	1
T13	0	1
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T40	0	28
T41	0	1
T45	0	2
T47	0	1
T48	0	1
T50	0	1
T58	815	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	968
T2	298170	1
T3	61729	0
T7	399530	0
T8	118302	1
T9	0	1
T13	0	1
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T40	0	28
T41	0	1
T45	0	2
T47	0	1
T48	0	1
T50	0	1
T58	375030	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T8,T9
1	0	Covered	T40,T42,T24
1	1	Covered	T2,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	961	0	0
SrcPulseCheck_M	7955931	961	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	961
T2	298170	1
T3	61729	0
T7	399530	0
T8	118302	1
T9	0	1
T13	0	1
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T40	0	28
T41	0	1
T45	0	2
T47	0	1
T48	0	1
T50	0	1
T58	375030	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	961
T2	737	1
T3	2496	0
T7	8323	0
T8	1841	1
T9	0	1
T13	0	1
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T40	0	28
T41	0	1
T45	0	2
T47	0	1
T48	0	1
T50	0	1
T58	815	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T7
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1912	0	0
SrcPulseCheck_M	1187298715	1975	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1912
T1	12854	4
T2	737	1
T3	2496	0
T7	8323	1
T8	0	1
T9	0	1
T10	0	5
T11	0	2
T12	0	2
T13	0	1
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1975
T1	141402	4
T2	298170	1
T3	61729	0
T7	399530	1
T8	0	1
T9	0	1
T10	0	5
T11	0	2
T12	0	2
T13	0	1
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T7
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T2,T7

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1968	0	0
SrcPulseCheck_M	7955931	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1968
T1	141402	4
T2	298170	1
T3	61729	0
T7	399530	1
T8	0	1
T9	0	1
T10	0	5
T11	0	2
T12	0	2
T13	0	1
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T47	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1968
T1	12854	4
T2	737	1
T3	2496	0
T7	8323	1
T8	0	1
T9	0	1
T10	0	5
T11	0	2
T12	0	2
T13	0	1
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T47	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1184	0	0
SrcPulseCheck_M	1187298715	1251	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1184
T1	12854	0
T2	737	0
T4	7402	5
T5	1645	0
T6	505	0
T14	494	0
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T30	0	3
T31	0	3
T40	0	2
T42	0	2
T49	0	3
T54	0	4
T55	0	5
T56	0	4
T57	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1251
T1	141402	0
T2	298170	0
T4	181352	5
T5	822803	0
T6	63214	0
T14	59293	0
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T30	0	3
T31	0	3
T40	0	2
T42	0	2
T49	0	3
T54	0	4
T55	0	5
T56	0	4
T57	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1243	0	0
SrcPulseCheck_M	7955931	1243	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1243
T1	141402	0
T2	298170	0
T4	181352	5
T5	822803	0
T6	63214	0
T14	59293	0
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T30	0	3
T31	0	3
T40	0	2
T42	0	2
T49	0	3
T54	0	4
T55	0	5
T56	0	4
T57	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1243
T1	12854	0
T2	737	0
T4	7402	5
T5	1645	0
T6	505	0
T14	494	0
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T30	0	3
T31	0	3
T40	0	2
T42	0	2
T49	0	3
T54	0	4
T55	0	5
T56	0	4
T57	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1063	0	0
SrcPulseCheck_M	1187298715	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1063
T1	12854	0
T2	737	0
T4	7402	4
T5	1645	0
T6	505	0
T14	494	0
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T30	0	3
T31	0	2
T40	0	1
T42	0	1
T49	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1127
T1	141402	0
T2	298170	0
T4	181352	4
T5	822803	0
T6	63214	0
T14	59293	0
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T30	0	3
T31	0	2
T40	0	1
T42	0	1
T49	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	3

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1119	0	0
SrcPulseCheck_M	7955931	1119	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1119
T1	141402	0
T2	298170	0
T4	181352	4
T5	822803	0
T6	63214	0
T14	59293	0
T20	53125	0
T21	171242	0
T22	98375	0
T23	50564	0
T30	0	3
T31	0	2
T40	0	1
T42	0	1
T49	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1119
T1	12854	0
T2	737	0
T4	7402	4
T5	1645	0
T6	505	0
T14	494	0
T20	424	0
T21	422	0
T22	410	0
T23	405	0
T30	0	3
T31	0	2
T40	0	1
T42	0	1
T49	0	3
T54	0	3
T55	0	3
T56	0	3
T57	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	6901	0	0
SrcPulseCheck_M	1187298715	6960	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	6901
T1	12854	62
T2	737	0
T3	2496	0
T7	8323	87
T11	0	76
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T37	0	78
T40	0	11
T52	0	51
T73	0	51
T74	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	6960
T1	141402	62
T2	298170	0
T3	61729	0
T7	399530	87
T11	0	76
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T37	0	78
T40	0	11
T52	0	51
T73	0	51
T74	0	77

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	6955	0	0
SrcPulseCheck_M	7955931	6955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	6955
T1	141402	62
T2	298170	0
T3	61729	0
T7	399530	87
T11	0	76
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T37	0	78
T40	0	11
T52	0	51
T73	0	51
T74	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	6955
T1	12854	62
T2	737	0
T3	2496	0
T7	8323	87
T11	0	76
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T37	0	78
T40	0	11
T52	0	51
T73	0	51
T74	0	77

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	6869	0	0
SrcPulseCheck_M	1187298715	6936	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	6869
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	59
T11	0	52
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	83
T40	0	11
T52	0	51
T73	0	63
T74	0	65
T75	0	64

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	6936
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	59
T11	0	52
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	83
T40	0	11
T52	0	51
T73	0	63
T74	0	65
T75	0	64

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	6929	0	0
SrcPulseCheck_M	7955931	6929	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	6929
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	59
T11	0	52
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	83
T40	0	11
T52	0	51
T73	0	63
T74	0	65
T75	0	64

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	6929
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	59
T11	0	52
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	83
T40	0	11
T52	0	51
T73	0	63
T74	0	65
T75	0	64

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	7063	0	0
SrcPulseCheck_M	1187298715	7126	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	7063
T1	12854	69
T2	737	0
T3	2496	0
T7	8323	87
T11	0	76
T12	0	52
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	79
T40	0	11
T52	0	51
T73	0	63
T74	0	80
T75	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	7126
T1	141402	69
T2	298170	0
T3	61729	0
T7	399530	87
T11	0	76
T12	0	52
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	79
T40	0	11
T52	0	51
T73	0	63
T74	0	80
T75	0	72

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	7119	0	0
SrcPulseCheck_M	7955931	7119	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	7119
T1	141402	69
T2	298170	0
T3	61729	0
T7	399530	87
T11	0	76
T12	0	52
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	79
T40	0	11
T52	0	51
T73	0	63
T74	0	80
T75	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	7119
T1	12854	69
T2	737	0
T3	2496	0
T7	8323	87
T11	0	76
T12	0	52
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	79
T40	0	11
T52	0	51
T73	0	63
T74	0	80
T75	0	72

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	6927	0	0
SrcPulseCheck_M	1187298715	6993	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	6927
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	76
T11	0	76
T12	0	80
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	68
T40	0	11
T52	0	51
T73	0	63
T74	0	73
T75	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	6993
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	76
T11	0	76
T12	0	80
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	69
T40	0	11
T52	0	51
T73	0	63
T74	0	73
T75	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	6984	0	0
SrcPulseCheck_M	7955931	6984	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	6984
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	76
T11	0	76
T12	0	80
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	69
T40	0	11
T52	0	51
T73	0	63
T74	0	73
T75	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	6984
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	76
T11	0	76
T12	0	80
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	69
T40	0	11
T52	0	51
T73	0	63
T74	0	73
T75	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1080	0	0
SrcPulseCheck_M	1187298715	1144	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1080
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1144
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1135	0	0
SrcPulseCheck_M	7955931	1135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1135
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1135
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1091	0	0
SrcPulseCheck_M	1187298715	1155	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1091
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1155
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1147	0	0
SrcPulseCheck_M	7955931	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1147
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1147
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1083	0	0
SrcPulseCheck_M	1187298715	1149	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1083
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1149
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1141	0	0
SrcPulseCheck_M	7955931	1141	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1141
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1141
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1107	0	0
SrcPulseCheck_M	1187298715	1166	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1107
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1166
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T1,T7,T11
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T11
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1157	0	0
SrcPulseCheck_M	7955931	1157	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1157
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1157
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T37	0	5
T40	0	9
T52	0	1
T73	0	1
T74	0	8
T75	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	7570	0	0
SrcPulseCheck_M	1187298715	7636	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	7570
T1	12854	62
T2	737	0
T3	2496	0
T7	8323	87
T10	0	5
T11	0	76
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	7636
T1	141402	62
T2	298170	0
T3	61729	0
T7	399530	87
T10	0	5
T11	0	76
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	7628	0	0
SrcPulseCheck_M	7955931	7628	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	7628
T1	141402	62
T2	298170	0
T3	61729	0
T7	399530	87
T10	0	5
T11	0	76
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	7628
T1	12854	62
T2	737	0
T3	2496	0
T7	8323	87
T10	0	5
T11	0	76
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	7497	0	0
SrcPulseCheck_M	1187298715	7568	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	7497
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	59
T10	0	5
T11	0	52
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	7568
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	59
T10	0	5
T11	0	52
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	7558	0	0
SrcPulseCheck_M	7955931	7558	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	7558
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	59
T10	0	5
T11	0	52
T12	0	66
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	7558
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	59
T10	0	5
T11	0	52
T12	0	66
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	7660	0	0
SrcPulseCheck_M	1187298715	7721	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	7660
T1	12854	69
T2	737	0
T3	2496	0
T7	8323	87
T10	0	5
T11	0	76
T12	0	52
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	7721
T1	141402	69
T2	298170	0
T3	61729	0
T7	399530	87
T10	0	5
T11	0	76
T12	0	52
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	7715	0	0
SrcPulseCheck_M	7955931	7715	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	7715
T1	141402	69
T2	298170	0
T3	61729	0
T7	399530	87
T10	0	5
T11	0	76
T12	0	52
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	7715
T1	12854	69
T2	737	0
T3	2496	0
T7	8323	87
T10	0	5
T11	0	76
T12	0	52
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	7577	0	0
SrcPulseCheck_M	1187298715	7646	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	7577
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	76
T10	0	5
T11	0	76
T12	0	80
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	7646
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	76
T10	0	5
T11	0	76
T12	0	80
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T1,T7,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T11
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	7638	0	0
SrcPulseCheck_M	7955931	7638	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	7638
T1	141402	85
T2	298170	0
T3	61729	0
T7	399530	76
T10	0	5
T11	0	76
T12	0	80
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	7638
T1	12854	85
T2	737	0
T3	2496	0
T7	8323	76
T10	0	5
T11	0	76
T12	0	80
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	11
T51	0	4
T52	0	51
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1816	0	0
SrcPulseCheck_M	1187298715	1880	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1816
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1880
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1873	0	0
SrcPulseCheck_M	7955931	1873	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1873
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1873
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1755	0	0
SrcPulseCheck_M	1187298715	1825	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1755
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1825
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1814	0	0
SrcPulseCheck_M	7955931	1814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1814
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1814
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1762	0	0
SrcPulseCheck_M	1187298715	1830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1762
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1830
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1822	0	0
SrcPulseCheck_M	7955931	1822	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1822
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1822
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1745	0	0
SrcPulseCheck_M	1187298715	1812	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1745
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1812
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1803	0	0
SrcPulseCheck_M	7955931	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1803
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1803
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1788	0	0
SrcPulseCheck_M	1187298715	1854	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1788
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1854
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1847	0	0
SrcPulseCheck_M	7955931	1847	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1847
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1847
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T35	0	1
T36	0	6
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1763	0	0
SrcPulseCheck_M	1187298715	1830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1763
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1830
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1822	0	0
SrcPulseCheck_M	7955931	1822	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1822
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1822
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1738	0	0
SrcPulseCheck_M	1187298715	1801	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1738
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1801
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1794	0	0
SrcPulseCheck_M	7955931	1794	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1794
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1794
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7955931	1748	0	0
SrcPulseCheck_M	1187298715	1812	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7955931	1748
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1187298715	1812
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T7,T10
1	1	Covered	T40,T42,T24

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T7,T10
1	0	Covered	T40,T42,T24
1	1	Covered	T1,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1187298715	1803	0	0
SrcPulseCheck_M	7955931	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1187298715	1803
T1	141402	4
T2	298170	0
T3	61729	0
T7	399530	1
T10	0	5
T11	0	2
T12	0	2
T14	59293	0
T15	220125	0
T16	80821	0
T17	232744	0
T18	44862	0
T19	118557	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7955931	1803
T1	12854	4
T2	737	0
T3	2496	0
T7	8323	1
T10	0	5
T11	0	2
T12	0	2
T14	494	0
T15	4402	0
T16	404	0
T17	495	0
T18	408	0
T19	494	0
T36	0	5
T40	0	9
T51	0	4
T52	0	1
T53	0	15

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc