Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_intr_status_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_intr_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	0	28	100.00

Variables for Group Instance sysrst_ctrl_key_intr_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_h2l	2	0	2	100.00	100	1	1	2
cp_ac_present_l2h	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_h2l	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_l2h	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_h2l	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_l2h	2	0	2	100.00	100	1	1	2
cp_key0_in_h2l	2	0	2	100.00	100	1	1	2
cp_key0_in_l2h	2	0	2	100.00	100	1	1	2
cp_key1_in_h2l	2	0	2	100.00	100	1	1	2
cp_key1_in_l2h	2	0	2	100.00	100	1	1	2
cp_key2_in_h2l	2	0	2	100.00	100	1	1	2
cp_key2_in_l2h	2	0	2	100.00	100	1	1	2
cp_pwrb_h2l	2	0	2	100.00	100	1	1	2
cp_pwrb_l2h	2	0	2	100.00	100	1	1	2

Summary for Variable cp_ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T3

8

T8

33

T9

9

auto[1]

152

1

T8

2

T9

1

T11

4

---

Summary for Variable cp_ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T3

6

T8

30

T9

10

auto[1]

144

1

T3

2

T8

5

T44

3

---

Summary for Variable cp_ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T3

6

T8

35

T9

8

auto[1]

153

1

T3

2

T9

2

T11

10

---

Summary for Variable cp_ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T3

8

T8

35

T9

6

auto[1]

114

1

T9

4

T11

5

T12

1

---

Summary for Variable cp_flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T3

6

T8

34

T9

10

auto[1]

156

1

T3

2

T8

1

T11

4

---

Summary for Variable cp_flash_wp_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T3

8

T8

34

T9

7

auto[1]

103

1

T8

1

T9

3

T11

2

---

Summary for Variable cp_key0_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T3

8

T8

30

T9

9

auto[1]

112

1

T8

5

T9

1

T44

1

---

Summary for Variable cp_key0_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1145

1

T3

8

T8

35

T9

10

auto[1]

120

1

T12

1

T36

5

T39

2

---

Summary for Variable cp_key1_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T3

8

T8

31

T9

6

auto[1]

104

1

T8

4

T9

4

T11

3

---

Summary for Variable cp_key1_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T3

8

T8

30

T9

10

auto[1]

149

1

T8

5

T11

9

T41

1

---

Summary for Variable cp_key2_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T3

8

T8

34

T9

6

auto[1]

115

1

T8

1

T9

4

T11

6

---

Summary for Variable cp_key2_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T3

8

T8

30

T9

10

auto[1]

142

1

T8

5

T44

1

T36

4

---

Summary for Variable cp_pwrb_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T3

6

T8

33

T9

7

auto[1]

115

1

T3

2

T8

2

T9

3

---

Summary for Variable cp_pwrb_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T3

6

T8

26

T9

10

auto[1]

153

1

T3

2

T8

9

T11

4