Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1602

1

T6

7

T1

13

T48

5

auto[1]

636

1

T6

13

T1

4

T2

22

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680

1

T6

20

T1

15

T2

10

auto[1]

558

1

T1

2

T2

12

T48

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T6

20

T1

13

T2

12

auto[1]

622

1

T1

4

T2

10

T7

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1688

1

T6

13

T1

16

T2

22

auto[1]

550

1

T6

7

T1

1

T48

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2049

1

T6

20

T1

17

T2

22

auto[1]

189

1

T7

3

T45

2

T38

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2070

1

T6

20

T1

17

T2

22

auto[1]

168

1

T7

9

T45

2

T38

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2041

1

T6

20

T1

17

T2

22

auto[1]

197

1

T46

22

T253

7

T254

20

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2053

1

T6

20

T1

17

T2

22

auto[1]

185

1

T7

2

T46

11

T71

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2013

1

T6

20

T1

17

T2

22

auto[1]

225

1

T7

3

T38

3

T46

11

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T6

13

T2

18

T7

32

auto[1]

585

1

T6

7

T1

17

T2

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	817	1			T6	20		T1	16		T2	22
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	67	1			T67	3		T258	5		T269	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	65	1			T38	3		T71	2		T253	7
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T7	3		T358	2		T359	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	45	1			T71	2		T253	8		T315	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	5	1			T315	1		T269	1		T359	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	52	1			T46	6		T254	34		T315	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	9	1			T360	1		T361	3		T357	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	89	1			T46	7		T254	20		T362	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	8	1			T46	5		T255	3		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	13	1			T363	8		T266	1		T242	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T364	1		T229	1		T365	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	24	1			T253	7		T258	3		T366	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	9	1			T315	1		T367	8		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T353	2		T266	1		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	1	1			T219	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	71	1			T7	7		T46	3		T67	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	26	1			T45	2		T38	3		T368	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	19	1			T254	9		T82	3		T355	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T369	5		T353	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	16	1			T7	2		T255	5		T370	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T255	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	1	1			T371	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T371	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T363	2		T369	3		T372	2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

134

1

T6

13

T261

5

T265

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T1

13

T8

1

T265

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

49

1

T80

1

T369

3

T81

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T7

3

T36

1

T347

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

63

1

T261

3

T373

5

T374

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

77

1

T6

7

T38

3

T260

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T46

3

T156

4

T262

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

140

1

T7

2

T46

6

T255

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

71

1

T2

10

T36

1

T75

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T37

7

T269

1

T366

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T1

2

T89

3

T348

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T7

7

T45

2

T263

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T71

2

T254

9

T373

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T50

1

T326

2

T80

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T260

1

T259

2

T78

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

82

1

T36

1

T75

1

T253

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

60

1

T2

8

T38

3

T254

17

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T48

5

T49

1

T326

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

39

1

T2

4

T253

7

T294

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T37

7

T88

6

T255

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T375

2

T164

1

T96

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T46

7

T83

2

T215

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T48

1

T260

2

T259

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T260

7

T99

3

T80

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

41

1

T71

2

T254

17

T91

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

11

1

T326

1

T347

4

T374

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T37

1

T265

1

T89

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

14

1

T326

2

T91

1

T127

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T376

1

T351

1

T377

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T67

3

T92

2

T181

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T1

1

T267

1

T349

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded