Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1258

1

T15

12

T66

8

T3

19

auto[1]

1226

1

T15

8

T66

12

T3

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

600

1

T15

7

T66

6

T3

10

from_0to1

597

1

T15

6

T66

5

T3

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1243

1

T15

11

T66

9

T3

22

auto[1]

1241

1

T15

9

T66

11

T3

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1248

1

T15

13

T66

11

T3

21

auto[1]

1236

1

T15

7

T66

9

T3

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T15

2

T50

1

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T66

1

T8

2

T50

1

auto[0]

from_1to0

auto[1]

auto[0]

85

1

T15

2

T66

1

T3

3

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T66

1

T3

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T15

2

T3

3

T8

2

auto[0]

from_0to1

auto[0]

auto[1]

88

1

T15

2

T3

2

T50

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T66

1

T3

1

T50

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T3

1

T8

1

T36

2

auto[1]

from_1to0

auto[0]

auto[0]

89

1

T15

1

T66

1

T138

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T3

2

T8

3

T36

2

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T15

1

T66

1

T3

2

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T15

1

T66

1

T3

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T15

1

T66

1

T3

1

auto[1]

from_0to1

auto[0]

auto[1]

83

1

T3

2

T8

1

T50

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T66

1

T36

1

T138

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T15

1

T66

2

T3

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1246

1

T15

10

T66

8

T3

23

auto[1]

1238

1

T15

10

T66

12

T3

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

606

1

T15

4

T66

5

T3

13

from_0to1

604

1

T15

5

T66

5

T3

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1294

1

T15

12

T66

15

T3

26

auto[1]

1190

1

T15

8

T66

5

T3

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1204

1

T15

10

T66

8

T3

22

auto[1]

1280

1

T15

10

T66

12

T3

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T15

1

T66

1

T3

3

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T15

2

T3

2

T50

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T3

1

T36

1

T54

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T3

3

T62

1

T72

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T15

1

T66

1

T3

2

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T15

1

T66

1

T3

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T15

1

T3

2

T36

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T8

1

T50

2

T54

1

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T66

1

T3

2

T36

3

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T66

1

T3

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T15

1

T50

1

T115

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T66

2

T3

1

T8

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T15

1

T66

1

T3

1

auto[1]

from_0to1

auto[0]

auto[1]

86

1

T66

1

T3

5

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T15

1

T3

2

T8

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T66

1

T50

1

T138

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1223

1

T15

11

T66

8

T3

20

auto[1]

1261

1

T15

9

T66

12

T3

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T15

5

T66

6

T3

10

from_0to1

589

1

T15

5

T66

6

T3

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1233

1

T15

13

T66

13

T3

16

auto[1]

1251

1

T15

7

T66

7

T3

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1208

1

T15

11

T66

10

T3

16

auto[1]

1276

1

T15

9

T66

10

T3

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T15

1

T3

1

T36

1

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T15

2

T66

2

T3

1

auto[0]

from_1to0

auto[1]

auto[0]

85

1

T15

1

T8

1

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T15

1

T66

1

T3

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T3

1

T138

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T15

1

T66

1

T3

3

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T66

1

T3

2

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T3

1

T8

1

T50

2

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T66

1

T138

1

T389

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T66

1

T3

2

T50

3

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T3

3

T8

1

T36

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T66

1

T3

2

T36

2

auto[1]

from_0to1

auto[0]

auto[0]

84

1

T15

2

T66

2

T8

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T15

1

T3

1

T8

2

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T66

1

T3

2

T36

2

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T15

1

T66

1

T36

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1253

1

T15

11

T66

14

T3

20

auto[1]

1231

1

T15

9

T66

6

T3

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

592

1

T15

4

T66

5

T3

10

from_0to1

583

1

T15

4

T66

4

T3

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1268

1

T15

13

T66

8

T3

18

auto[1]

1216

1

T15

7

T66

12

T3

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1237

1

T15

12

T66

12

T3

20

auto[1]

1247

1

T15

8

T66

8

T3

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T15

1

T66

1

T3

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T66

1

T3

1

T389

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T66

3

T3

1

T50

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T3

2

T8

1

T36

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T15

1

T3

1

T138

1

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T8

1

T36

1

T54

3

auto[0]

from_0to1

auto[1]

auto[0]

84

1

T15

1

T66

1

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T66

1

T3

2

T8

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T15

1

T3

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T15

1

T3

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T15

1

T3

1

T8

2

auto[1]

from_1to0

auto[1]

auto[1]

84

1

T3

1

T36

1

T138

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T15

1

T3

1

T8

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T15

1

T66

1

T3

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T66

1

T50

1

T138

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T3

3

T50

1

T36

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T15

10

T66

9

T3

23

auto[1]

1215

1

T15

10

T66

11

T3

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

580

1

T15

5

T66

4

T3

7

from_0to1

586

1

T15

4

T66

5

T3

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1231

1

T15

10

T66

10

T3

19

auto[1]

1253

1

T15

10

T66

10

T3

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T15

9

T66

9

T3

16

auto[1]

1292

1

T15

11

T66

11

T3

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T15

1

T50

1

T36

2

auto[0]

from_1to0

auto[0]

auto[1]

85

1

T8

1

T50

1

T138

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T3

1

T8

1

T138

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T66

1

T8

1

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T15

1

T3

2

T138

2

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T15

1

T66

1

T3

3

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T3

1

T8

2

T50

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T15

1

T66

1

T50

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T15

2

T66

1

T36

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T15

1

T3

2

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T66

2

T3

2

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

78

1

T15

1

T3

2

T36

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T66

1

T50

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T66

1

T3

1

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T15

1

T3

1

T36

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T66

1

T50

1

T36

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1251

1

T15

14

T66

14

T3

13

auto[1]

1233

1

T15

6

T66

6

T3

27

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

584

1

T15

5

T66

4

T3

8

from_0to1

588

1

T15

6

T66

4

T3

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1219

1

T15

14

T66

7

T3

24

auto[1]

1265

1

T15

6

T66

13

T3

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1227

1

T15

10

T66

8

T3

20

auto[1]

1257

1

T15

10

T66

12

T3

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T66

1

T3

1

T8

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T15

1

T66

2

T50

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T15

1

T66

1

T8

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T15

1

T8

1

T138

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T15

2

T66

1

T8

2

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T15

3

T3

3

T50

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T66

1

T50

1

T138

2

auto[0]

from_0to1

auto[1]

auto[1]

80

1

T66

2

T50

1

T36

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T15

2

T3

3

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

88

1

T3

1

T50

1

T36

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T3

2

T54

1

T302

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T3

1

T8

3

T50

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T3

2

T138

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T3

1

T8

1

T389

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T3

2

T8

1

T54

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T15

1

T3

1

T8

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1256

1

T15

9

T66

8

T3

17

auto[1]

1228

1

T15

11

T66

12

T3

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

569

1

T15

5

T66

4

T3

9

from_0to1

569

1

T15

6

T66

4

T3

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1231

1

T15

12

T66

10

T3

17

auto[1]

1253

1

T15

8

T66

10

T3

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1262

1

T15

14

T66

10

T3

17

auto[1]

1222

1

T15

6

T66

10

T3

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T15

2

T3

1

T8

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T15

1

T8

1

T50

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T66

1

T3

1

T50

1

auto[0]

from_1to0

auto[1]

auto[1]

87

1

T66

1

T3

1

T8

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T15

2

T3

1

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T3

1

T54

2

T389

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T15

1

T3

1

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T66

1

T3

2

T8

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T66

2

T138

1

T54

3

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T3

1

T8

1

T389

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T15

2

T3

2

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T3

3

T8

1

T50

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T15

3

T3

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T66

1

T8

2

T138

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T3

2

T8

1

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T66

2

T3

2

T36

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1282

1

T15

9

T66

12

T3

18

auto[1]

1202

1

T15

11

T66

8

T3

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

603

1

T15

5

T66

7

T3

10

from_0to1

591

1

T15

5

T66

6

T3

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1251

1

T15

10

T66

11

T3

18

auto[1]

1233

1

T15

10

T66

9

T3

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1228

1

T15

11

T66

13

T3

17

auto[1]

1256

1

T15

9

T66

7

T3

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T15

1

T66

2

T8

1

auto[0]

from_1to0

auto[0]

auto[1]

85

1

T66

1

T3

1

T8

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T66

1

T50

1

T36

1

auto[0]

from_1to0

auto[1]

auto[1]

84

1

T66

1

T3

2

T36

2

auto[0]

from_0to1

auto[0]

auto[0]

88

1

T15

1

T66

1

T3

1

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T15

1

T66

1

T3

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T15

1

T66

1

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

83

1

T3

3

T8

1

T138

2

auto[1]

from_1to0

auto[0]

auto[0]

84

1

T3

2

T138

2

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T15

1

T66

1

T3

2

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T15

1

T66

1

T3

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T15

2

T3

2

T62

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T8

1

T36

1

T138

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T15

1

T3

1

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T15

1

T66

3

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T3

2

T8

2

T54

3